1301 lines
53 KiB
C
1301 lines
53 KiB
C
/* pdp10_dtc.c: 18b 551 DECtape simulator
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Copyright (c) 2017 Richard Cornwell
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Based on PDP18B/pdp18b_dt.c by:
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Copyright (c) 1993-2017, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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Except as contained in this notice, the name of Richard Cornwell shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Richard Cornwell.
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dt (PDP-4, PDP-7) Type 550/555 DECtape
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(PDP-6) Type 551 Dectape
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(PDP-9) TC02/TU55 DECtape
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(PDP-10) TD10/TU55 DECtape
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(PDP-15) TC15/TU56 DECtape
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18b DECtapes are represented in memory by fixed length buffer of 32b words.
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Three file formats are supported:
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18b/36b 256 words per block [256 x 18b]
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16b 256 words per block [256 x 16b]
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12b 129 words per block [129 x 12b]
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When a 16b or 12b DECtape file is read in, it is converted to 18b/36b format.
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DECtape motion is measured in 3b lines. Time between lines is 33.33us.
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Tape density is nominally 300 lines per inch. The format of a DECtape (as
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taken from the PDP-7 formatter) is:
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reverse end zone 7144 reverse end zone codes ~ 12 feet
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reverse buffer 200 interblock codes
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block 0
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:
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block n
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forward buffer 200 interblock codes
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forward end zone 7144 forward end zone codes ~ 12 feet
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A block consists of five 18b header words, a tape-specific number of data
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words, and five 18b trailer words. All systems except the PDP-8 use a
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standard block length of 256 words; the PDP-8 uses a standard block length
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of 86 words (x 18b = 129 words x 12b). PDP-4/7 DECtapes came in two
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formats. The first 5 controllers used a 4 word header/trailer (missing
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word 0/4). All later serial numbers used the standard header. The later,
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standard header/trailer is simulated here.
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Because a DECtape file only contains data, the simulator cannot support
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write timing and mark track and can only do a limited implementation
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of read all and write all. Read all assumes that the tape has been
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conventionally written forward:
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header word 0 0
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header word 1 block number (for forward reads)
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header words 2,3 0
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header word 4 checksum (for reverse reads)
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:
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trailer word 4 checksum (for forward reads)
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trailer words 3,2 0
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trailer word 1 block number (for reverse reads)
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trailer word 0 0
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Write all writes only the data words and dumps the interblock words in the
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bit bucket.
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*/
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#include "kx10_defs.h"
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#ifndef NUM_DEVS_DTC
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#define NUM_DEVS_DTC 0
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#endif
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#if (NUM_DEVS_DTC > 0)
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#define DTC_DEVNUM 0210
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#define DTC_NUMDR 8 /* #drives */
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#define UNIT_V_8FMT (UNIT_V_UF + 0) /* 12b format */
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#define UNIT_V_11FMT (UNIT_V_UF + 1) /* 16b format */
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#define UNIT_8FMT (1 << UNIT_V_8FMT)
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#define UNIT_11FMT (1 << UNIT_V_11FMT)
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/* System independent DECtape constants */
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#define DT_LPERMC 6 /* lines per mark track */
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#define DT_BLKWD 1 /* blk no word in h/t */
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#define DT_CSMWD 4 /* checksum word in h/t */
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#define DT_HTWRD 5 /* header/trailer words */
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#define DT_EZLIN (8192 * DT_LPERMC) /* end zone length */
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#define DT_BFLIN (200 * DT_LPERMC) /* buffer length */
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#define DT_BLKLN (DT_BLKWD * DT_LPERMC) /* blk no line in h/t */
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#define DT_CSMLN (DT_CSMWD * DT_LPERMC) /* csum line in h/t */
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#define DT_HTLIN (DT_HTWRD * DT_LPERMC) /* header/trailer lines */
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/* 16b, 18b, 36b DECtape constants */
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#define D18_WSIZE 6 /* word size in lines */
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#define D18_BSIZE 256 /* block size in 18b */
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#define D18_TSIZE 578 /* tape size */
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#define D18_LPERB (DT_HTLIN + (D18_BSIZE * DT_WSIZE) + DT_HTLIN)
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#define D18_FWDEZ (DT_EZLIN + (D18_LPERB * D18_TSIZE))
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#define D18_CAPAC (D18_TSIZE * D18_BSIZE) /* tape capacity */
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#define D11_FILSIZ (D18_CAPAC * sizeof (int16))
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/* 12b DECtape constants */
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#define D8_WSIZE 4 /* word size in lines */
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#define D8_BSIZE 86 /* block size in 18b */
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#define D8_TSIZE 1474 /* tape size */
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#define D8_LPERB (DT_HTLIN + (D8_BSIZE * DT_WSIZE) + DT_HTLIN)
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#define D8_FWDEZ (DT_EZLIN + (D8_LPERB * D8_TSIZE))
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#define D8_CAPAC (D8_TSIZE * D8_BSIZE) /* tape capacity */
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#define D8_NBSIZE ((D8_BSIZE * D18_WSIZE) / D8_WSIZE)
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#define D8_FILSIZ (D8_NBSIZE * D8_TSIZE * sizeof (int16))
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/* This controller */
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#define DT_CAPAC D18_CAPAC /* default */
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#define DT_WSIZE D18_WSIZE
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/* Calculated constants, per unit */
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#define DTU_BSIZE(u) (((u)->flags & UNIT_8FMT)? D8_BSIZE: D18_BSIZE)
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#define DTU_TSIZE(u) (((u)->flags & UNIT_8FMT)? D8_TSIZE: D18_TSIZE)
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#define DTU_LPERB(u) (((u)->flags & UNIT_8FMT)? D8_LPERB: D18_LPERB)
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#define DTU_FWDEZ(u) (((u)->flags & UNIT_8FMT)? D8_FWDEZ: D18_FWDEZ)
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#define DTU_CAPAC(u) (((u)->flags & UNIT_8FMT)? D8_CAPAC: D18_CAPAC)
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#define DT_LIN2BL(p,u) (((p) - DT_EZLIN) / DTU_LPERB (u))
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#define DT_LIN2OF(p,u) (((p) - DT_EZLIN) % DTU_LPERB (u))
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#define DT_LIN2WD(p,u) ((DT_LIN2OF (p,u) - DT_HTLIN) / DT_WSIZE)
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#define DT_BLK2LN(p,u) (((p) * DTU_LPERB (u)) + DT_EZLIN)
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#define DT_QREZ(u) (((u)->pos) < DT_EZLIN)
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#define DT_QFEZ(u) (((u)->pos) >= ((uint32) DTU_FWDEZ (u)))
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#define DT_QEZ(u) (DT_QREZ (u) || DT_QFEZ (u))
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/* Command register, status A */
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#define CMD u3
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#define DTC_FLAG_PIA 07 /* PI Channel */
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#define DTC_V_UNIT 3 /* unit select */
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#define DTC_M_UNIT 07
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#define DTC_V_FNC 6
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#define DTC_M_FNC 07
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#define FNC_MOVE 00 /* move */
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#define FNC_RALL 01 /* read all */
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#define FNC_SRCH 02 /* search */
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#define FNC_READ 03 /* read */
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#define FNC_WMRK 04 /* write timing */
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#define FNC_WALL 05 /* write All */
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#define FNC_WBLK 06 /* Write Block */
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#define FNC_WRIT 07 /* write data */
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#define DTC_DELAY 0003000 /* Initial delay time */
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#define DTC_TIME 0004000 /* Delay */
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#define DTC_RVDRV 0010000 /* Move unit reverse */
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#define DTC_START 0020000 /* Start unit */
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#define DTC_JDONE 0040000 /* Enable Job done */
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#define DTC_ETF 0100000 /* Enable End of tape flag */
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#define DTC_SEL 0200000 /* Select unit */
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/* Flags in lower bits of u3 (unit position) */
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#define DTC_FNC_STOP 010 /* Unit stopping */
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#define DTC_FNC_START DTC_START /* Start unit motion */
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#define DTC_FNC_REV DTC_RVDRV /* Unit to change direction */
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#define DTC_GETFNC(x) (((x) >> DTC_V_FNC) & DTC_M_FNC)
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#define DTC_GETUNI(x) (((x) >> DTC_V_UNIT) & DTC_M_UNIT)
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/* Status register B */
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#define DTB_DONE 0000001
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#define DTB_EOT 0000002
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#define DTB_ILL 0000004
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#define DTB_PAR 0000010
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#define DTB_TIME 0000020
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#define DTB_WR 0000040
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#define DTB_INCBLK 0000100
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#define DTB_NULL 0000200
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#define DTB_ACT 0000400
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#define DTB_REQ 0001000
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#define DTB_DLY 0002000
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#define DSTATE u5 /* Dectape current state */
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/* Current Dectape state in u5 */
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#define DTC_FEND 0 /* Tape in endzone */
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#define DTC_FBLK 1 /* In forward block number */
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#define DTC_FCHK 2 /* In forward checksum */
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#define DTC_BLOCK 3 /* In block */
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#define DTC_RCHK 4 /* In reverse checksum */
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#define DTC_RBLK 5 /* In reverse block number */
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#define DTC_REND 7 /* In final endzone */
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#define DTC_MOTMASK 0370
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#define DTC_MOT 0010 /* Tape in motion */
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#define DTC_REV 0020 /* Tape in reverse */
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#define DTC_XFR 0040 /* Tranfer block */
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#define DTC_STOP 0100 /* Tape to stop */
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#define DTC_ACCL 0200 /* Tape accel or decl */
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#define DTC_V_WORD 8 /* Shift for word count */
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#define DTC_M_WORD 0177 /* 128 words per block */
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#define DTC_V_BLK 16 /* Shift for Block number */
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#define DTC_M_BLK 01777 /* Block mask */
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#define DELAY u4 /* Hold delay time in DT WORDS */
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/* Logging */
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#define LOG_MS 00200 /* move, search */
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#define LOG_RW 00400 /* read, write */
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#define LOG_RA 01000 /* read all */
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#define LOG_BL 02000 /* block # lblk */
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#define ABS(x) (((x) < 0)? (-(x)): (x))
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#define DT_WRDTIM 15000
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#define WRITTEN u6
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int32 dtc_dtsa = 0; /* status A */
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int32 dtc_dtsb = 0; /* status B */
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int dtc_dct = 0;
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t_stat dtc_devio(uint32 dev, uint64 *data);
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t_stat dtc_svc (UNIT *uptr);
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t_stat dtc_boot(int32 unit_num, DEVICE * dptr);
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t_stat dtc_set_dct (UNIT *, int32, CONST char *, void *);
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t_stat dtc_show_dct (FILE *, UNIT *, int32, CONST void *);
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t_stat dtc_reset (DEVICE *dptr);
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t_stat dtc_attach (UNIT *uptr, CONST char *cptr);
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void dtc_flush (UNIT *uptr);
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t_stat dtc_detach (UNIT *uptr);
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/* DT data structures
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dtc_dev DTC device descriptor
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dtc_unit DTC unit list
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dtc_reg DTC register list
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dtc_mod DTC modifier list
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*/
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#if !PDP6
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#define D DEV_DIS
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#else
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#define D 0
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#endif
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DIB dtc_dib = { DTC_DEVNUM, 2, &dtc_devio, NULL};
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UNIT dtc_unit[] = {
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) },
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{ UDATA (&dtc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, DT_CAPAC) }
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};
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REG dtc_reg[] = {
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{ ORDATA (DTSA, dtc_dtsa, 18) },
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{ URDATA (POS, dtc_unit[0].pos, 10, T_ADDR_W, 0,
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DTC_NUMDR, PV_LEFT | REG_RO) },
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{ NULL }
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};
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MTAB dtc_mod[] = {
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{ MTAB_XTD|MTAB_VUN, 0, "write enabled", "WRITEENABLED",
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&set_writelock, &show_writelock, NULL, "Write enable tape drive" },
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{ MTAB_XTD|MTAB_VUN, 1, NULL, "LOCKED",
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&set_writelock, NULL, NULL, "Write lock tape drive" },
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{ UNIT_8FMT + UNIT_11FMT, 0, "18b", NULL, NULL },
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{ UNIT_8FMT + UNIT_11FMT, UNIT_8FMT, "12b", NULL, NULL },
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{ UNIT_8FMT + UNIT_11FMT, UNIT_11FMT, "16b", NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "DCT", "DCT",
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&dtc_set_dct, &dtc_show_dct, NULL},
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{ 0 }
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};
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DEBTAB dtc_deb[] = {
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{ "CMD", DEBUG_CMD, "Show command execution to devices"},
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{ "DATA", DEBUG_DATA, "Show data transfers"},
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{ "DETAIL", DEBUG_DETAIL, "Show details about device"},
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{ "EXP", DEBUG_EXP, "Show exception information"},
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{ "CONI", DEBUG_CONI, "Show coni instructions"},
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{ "CONO", DEBUG_CONO, "Show cono instructions"},
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{ "DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"},
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{ "MOTION", LOG_MS },
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{ "DATA", LOG_RW },
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{ "READALL", LOG_RA },
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{ "BLOCK", LOG_BL },
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{ NULL, 0 }
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};
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DEVICE dtc_dev = {
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"DTC", dtc_unit, dtc_reg, dtc_mod,
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DTC_NUMDR, 8, 24, 1, 8, 18,
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NULL, NULL, &dtc_reset, &dtc_boot, &dtc_attach, &dtc_detach,
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&dtc_dib, DEV_DISABLE | DEV_DEBUG | D, 0,
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dtc_deb, NULL, NULL
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};
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int delay[] = { 0, 50, 100, 500 };
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/* IOT routines */
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t_stat
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dtc_devio(uint32 dev, uint64 *data) {
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int i;
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switch(dev & 07) {
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case CONI:
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*data = (uint64)dtc_dtsa;
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sim_debug(DEBUG_CONI, &dtc_dev, "DTC %03o CONI %06o PC=%o\n",
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dev, (uint32)*data, PC);
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break;
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case CONO:
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clr_interrupt(dev);
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/* Copy over command and priority */
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dtc_dtsa = *data & (DTC_FLAG_PIA|(DTC_M_FNC << DTC_V_FNC)|DTC_TIME|DTC_RVDRV| \
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DTC_START|DTC_JDONE|DTC_ETF|DTC_SEL);
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dtc_dtsb = 0;
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sim_debug(DEBUG_CONO, &dtc_dev, "DTC %03o CONO %06o PC=%o\n",
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dev, (uint32)*data, PC);
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i = DTC_GETUNI(*data);
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#if DTC_NUMDR < 8
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if (i >= DTC_NUMDR) {
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dtc_dtsb |= DTB_ILL;
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set_interrupt(DTC_DEVNUM, dtc_dtsa);
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return SCPE_OK;
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}
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#endif
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if (*data & DTC_DELAY) {
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dtc_dtsb |= DTB_DLY;
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dtc_unit[i].DELAY = delay[(*data >> 9) & 3];
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}
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/* Check if we are selecting a drive or not */
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if (*data & DTC_SEL) {
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if ((dtc_unit[i].flags & UNIT_ATT) == 0) {
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dtc_dtsb |= DTB_ILL;
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set_interrupt(DTC_DEVNUM, dtc_dtsa);
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return SCPE_OK;
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}
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if ((*data & DTC_START) != 0) {
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/* Start the unit if not already running */
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dtc_unit[i].CMD = (dtc_dtsa & 0377707);
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if ((dtc_unit[i].DSTATE & DTC_MOT) == 0) {
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if (!sim_is_active(&dtc_unit[i])) {
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sim_activate(&dtc_unit[i], 10000);
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}
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}
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} else {
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dtc_unit[i].CMD |= DTC_FNC_STOP;
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}
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dtc_dtsb |= DTB_REQ;
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} else {
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/* If not selecting, but delaying, give it to a unit to handle */
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if (dtc_dtsb & DTB_DLY) {
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dtc_unit[i].CMD = (dtc_dtsa & 0007007);
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if ((dtc_unit[i].DSTATE & DTC_MOT) == 0) {
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if (!sim_is_active(&dtc_unit[i])) {
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sim_activate(&dtc_unit[i], 10000);
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}
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}
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}
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/* Not selecting any, stop all */
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for (i = 0; i < DTC_NUMDR; i++)
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dtc_unit[i].CMD = DTC_FNC_STOP;
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dtc_dtsb |= DTB_NULL;
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}
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break;
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case DATAI:
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break;
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case DATAO:
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break;
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case CONI|04:
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*data = dtc_dtsb;
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sim_debug(DEBUG_CONI, &dtc_dev, "DTB %03o CONI %012llo PC=%o\n",
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dev, *data, PC);
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break;
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case CONO|04:
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break;
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case DATAI|4:
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break;
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case DATAO|4:
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break;
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}
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return SCPE_OK;
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}
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/* Unit service
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Unit must be attached, detach cancels operation
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*/
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t_stat
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dtc_svc (UNIT *uptr)
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{
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|
int word;
|
|
uint64 data = 0;
|
|
uint32 *fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
int u = uptr-dtc_unit;
|
|
int blk;
|
|
int off;
|
|
/*
|
|
* Check if in motion or stopping.
|
|
*/
|
|
if (uptr->DSTATE & DTC_MOT) {
|
|
/* Check if stoping */
|
|
if ((uptr->CMD & DTC_FNC_STOP) != 0) {
|
|
/* Stop delay */
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o stopping\n", u);
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
uptr->DSTATE &= ~(DTC_MOT);
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = (0100 << DTC_V_WORD) | DTC_BLOCK | (uptr->DSTATE & DTC_MOTMASK);
|
|
if (uptr->DSTATE & DTC_REV) {
|
|
if (blk <= 0) {
|
|
blk = 0;
|
|
uptr->DSTATE = DTC_FEND | (uptr->DSTATE & DTC_MOTMASK);
|
|
} else {
|
|
blk--;
|
|
}
|
|
} else {
|
|
if (blk <= 01100)
|
|
blk++;
|
|
}
|
|
dtc_dtsb |= DTB_DONE;
|
|
if ((uptr->CMD & DTC_JDONE) != 0)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
|
|
/* If we were delaying, all done, notify CPU if it asked to know */
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
uptr->DELAY = 0;
|
|
dtc_dtsb |= DTB_TIME;
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
if(uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_ACT);
|
|
dtc_dtsb |= DTB_NULL;
|
|
uptr->CMD &= 077077;
|
|
uptr->DSTATE |= (blk << DTC_V_BLK);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Set tape to move in correct direction */
|
|
if (uptr->CMD & DTC_RVDRV) {
|
|
if ((uptr->DSTATE & DTC_REV) == 0) {
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o reversing\n", u);
|
|
uptr->DSTATE |= DTC_REV;
|
|
uptr->DELAY -= 10;
|
|
return SCPE_OK;
|
|
}
|
|
} else {
|
|
if ((uptr->DSTATE & DTC_REV) != 0) {
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o reversing\n", u);
|
|
uptr->DSTATE &= ~DTC_REV;
|
|
uptr->DELAY -= 10;
|
|
return SCPE_OK;
|
|
}
|
|
}
|
|
|
|
/* Moving in reverse direction */
|
|
if (uptr->DSTATE & DTC_REV) {
|
|
switch (uptr->DSTATE & 7) {
|
|
case DTC_FEND: /* Tape in endzone */
|
|
/* Set stop */
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o rev forward end\n", u);
|
|
dtc_dtsb |= DTB_EOT|DTB_NULL;
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_ACT);
|
|
if (uptr->CMD & DTC_ETF)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
uptr->DELAY = 0;
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
|
|
case DTC_FBLK: /* In forward block number */
|
|
sim_activate(uptr,DT_WRDTIM);
|
|
uptr->DELAY --;
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word--;
|
|
if (word <= 0)
|
|
uptr->DSTATE = DTC_FEND | (uptr->DSTATE & DTC_MOTMASK);
|
|
else
|
|
uptr->DSTATE = DTC_RBLK|(word << DTC_V_BLK) | (uptr->DSTATE & DTC_MOTMASK);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o rev forward block\n", u);
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_RALL:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
if (dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
case FNC_READ:
|
|
case FNC_WRIT:
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
dtc_dtsb &= ~DTB_REQ;
|
|
dtc_dtsb |= DTB_ACT;
|
|
}
|
|
break;
|
|
case FNC_SRCH:
|
|
case FNC_MOVE:
|
|
break;
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
(void)dct_read(dtc_dct, &data, 6);
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_FCHK: /* In forward checksum */
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o rev forward check\n", u);
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
/* Disconnect if DCT no longer attached */
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_is_connect(dtc_dct) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
uptr->DELAY -= 2;
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = DTC_FBLK|(word << DTC_V_BLK) | (uptr->DSTATE & DTC_MOTMASK);
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_RALL:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
if (blk < 075)
|
|
data = 0721200220107LL;
|
|
else if (blk > 075)
|
|
data = 0721200233107LL;
|
|
else
|
|
data = 0577777777777LL;
|
|
if (dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
case FNC_SRCH:
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
case FNC_READ:
|
|
case FNC_WBLK:
|
|
case FNC_MOVE:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_BLOCK: /* In block */
|
|
uptr->DELAY --;
|
|
sim_activate(uptr,DT_WRDTIM);
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word = (uptr->DSTATE >> DTC_V_WORD) & DTC_M_WORD;
|
|
off = ((blk << 7) + word) << 1;
|
|
/* Check if at end of block */
|
|
if (word == 0) {
|
|
uptr->DSTATE &= ~((DTC_M_WORD << DTC_V_WORD) | 7);
|
|
uptr->DSTATE |= DTC_FCHK; /* Move to Checksum */
|
|
} else {
|
|
uptr->DSTATE &= ~(DTC_M_WORD << DTC_V_WORD);
|
|
uptr->DSTATE |= (word - 1) << DTC_V_WORD;
|
|
}
|
|
if ((dtc_dtsb & DTB_DLY) || (dtc_dtsb & DTB_ACT) == 0)
|
|
break;
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_SRCH:
|
|
case FNC_WBLK:
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
case FNC_RALL:
|
|
case FNC_READ:
|
|
data = ((uint64)fbuf[off]) << 18;
|
|
data |= ((uint64)fbuf[off+1]);
|
|
if (dct_write(dtc_dct, &data, 6) == 0) {
|
|
dtc_dtsb &= ~DTB_ACT;
|
|
dtc_dtsb |= DTB_INCBLK|DTB_DONE;
|
|
}
|
|
break;
|
|
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
if (dct_read(dtc_dct, &data, 6) == 0) {
|
|
dtc_dtsb &= ~DTB_ACT;
|
|
dtc_dtsb |= DTB_INCBLK|DTB_DONE;
|
|
}
|
|
fbuf[off] = (data >> 18) & RMASK;
|
|
fbuf[off+1] = data & RMASK;
|
|
uptr->WRITTEN = 1;
|
|
uptr->hwmark = uptr->capac;
|
|
break;
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev,
|
|
"DTC %o rev data word %o:%o %012llo %d %06o %06o\n",
|
|
u, blk, word, data, off, fbuf[off], fbuf[off+1]);
|
|
break;
|
|
|
|
case DTC_RCHK: /* In reverse checksum */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
uptr->DELAY -= 2;
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o rev reverse check %06o %06o\n",
|
|
u, uptr->CMD, dtc_dtsb);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = DTC_BLOCK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
|
(uptr->DSTATE & DTC_MOTMASK);
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_is_connect(dtc_dct) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
case FNC_SRCH:
|
|
case FNC_RALL:
|
|
case FNC_MOVE:
|
|
case FNC_READ:
|
|
case FNC_WBLK:
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
dtc_dtsb |= DTB_ACT;
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_NULL);
|
|
}
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_RBLK: /* In reverse block number */
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
uptr->DELAY -= 2;
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
data = (uint64)word;
|
|
uptr->DSTATE = DTC_RCHK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
|
(uptr->DSTATE & DTC_MOTMASK);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o rev reverse block %04o\n", u, word);
|
|
dtc_dtsb &= ~DTB_EOT;
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_READ:
|
|
case FNC_WMRK:
|
|
case FNC_WRIT:
|
|
break;
|
|
case FNC_RALL:
|
|
if (dtc_dtsb & DTB_ACT && dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
break;
|
|
case FNC_SRCH:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
(void)dct_write(dtc_dct, &data, 6);
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
(void)dct_read(dtc_dct, &data, 6);
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
}
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o activate\n", u);
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_NULL);
|
|
dtc_dtsb |= DTB_ACT;
|
|
}
|
|
break;
|
|
|
|
case DTC_REND: /* In final endzone */
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
uptr->DELAY -= 10;
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word--;
|
|
uptr->DSTATE = DTC_RBLK|(word << DTC_V_BLK) | (uptr->DSTATE & DTC_MOTMASK);
|
|
dtc_dtsb &= ~DTB_EOT;
|
|
break;
|
|
}
|
|
} else {
|
|
/* Moving in forward direction */
|
|
switch (uptr->DSTATE & 7) {
|
|
case DTC_FEND: /* Tape in endzone */
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
uptr->DELAY -= 10;
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o forward end\n", u);
|
|
/* Move to first block */
|
|
uptr->DSTATE = DTC_FBLK | (uptr->DSTATE & DTC_MOTMASK);
|
|
break;
|
|
|
|
case DTC_FBLK: /* In forward block number */
|
|
uptr->DELAY -= 2;
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
dtc_dtsb &= ~DTB_EOT;
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
uptr->DSTATE = DTC_FCHK|(word << DTC_V_BLK) | (uptr->DSTATE & DTC_MOTMASK);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o forward block %04o %06o\n",
|
|
u, word, dtc_dtsb);
|
|
data = (uint64)word;
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_is_connect(dtc_dct) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_SRCH:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
(void)dct_write(dtc_dct, &data, 6);
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
case FNC_RALL:
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
break;
|
|
case FNC_READ:
|
|
case FNC_WRIT:
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_NULL);
|
|
dtc_dtsb |= DTB_ACT;
|
|
}
|
|
break;
|
|
case FNC_MOVE:
|
|
break;
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
(void)dct_read(dtc_dct, &data, 6);
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_FCHK: /* In forward checksum */
|
|
uptr->DELAY -= 2;
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o forward check %06o\n", u, dtc_dtsb);
|
|
uptr->DSTATE &= ~7;
|
|
uptr->DSTATE |= DTC_BLOCK; /* Move to datablock */
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_is_connect(dtc_dct) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_RALL:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
if (blk < 075)
|
|
data = 0721200220107LL;
|
|
else if (blk > 075)
|
|
data = 0721200233107LL;
|
|
else
|
|
data = 0577777777777LL;
|
|
if (dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
case FNC_SRCH:
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
case FNC_READ:
|
|
case FNC_WBLK:
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_NULL);
|
|
dtc_dtsb |= DTB_ACT;
|
|
}
|
|
break;
|
|
case FNC_MOVE:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_BLOCK: /* In block */
|
|
uptr->DELAY --;
|
|
sim_activate(uptr,DT_WRDTIM);
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word = (uptr->DSTATE >> DTC_V_WORD) & DTC_M_WORD;
|
|
off = ((blk << 7) + word) << 1;
|
|
/* Check if at end of block */
|
|
if (word == DTC_M_WORD) {
|
|
uptr->DSTATE &= ~7;
|
|
uptr->DSTATE |= DTC_RCHK; /* Move to checksum */
|
|
} else {
|
|
uptr->DSTATE &= ~(DTC_M_WORD << DTC_V_WORD);
|
|
uptr->DSTATE |= (word + 1) << DTC_V_WORD;
|
|
}
|
|
if (dtc_dtsb & DTB_DLY)
|
|
break;
|
|
if ((dtc_dtsb & DTB_ACT) == 0)
|
|
break;
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_MOVE:
|
|
case FNC_SRCH:
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
break;
|
|
case FNC_RALL:
|
|
case FNC_READ:
|
|
data = ((uint64)fbuf[off]) << 18;
|
|
data |= (uint64)fbuf[off+1];
|
|
if (dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
break;
|
|
case FNC_WRIT:
|
|
if (dct_read(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
fbuf[off] = (data >> 18) & RMASK;
|
|
fbuf[off+1] = data & RMASK;
|
|
uptr->WRITTEN = 1;
|
|
uptr->hwmark = uptr->capac;
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev,
|
|
"DTC %o data word %o:%o %012llo %d %06o %06o\n",
|
|
u, blk, word, data, off, fbuf[off], fbuf[off+1]);
|
|
break;
|
|
|
|
case DTC_RCHK: /* In reverse checksum */
|
|
uptr->DELAY -=2;
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o reverse check\n", u);
|
|
uptr->DSTATE &= ~(DTC_M_WORD << DTC_V_WORD) | 7;
|
|
uptr->DSTATE |= DTC_RBLK; /* Move to end of block */
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_is_connect(dtc_dct) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_RALL:
|
|
if (dtc_dtsb & DTB_ACT) {
|
|
blk = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
if (blk < 073)
|
|
data = 0721200220107LL;
|
|
else
|
|
data = 0721200233107LL;
|
|
if (dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
}
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
break;
|
|
case FNC_SRCH:
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
case FNC_READ:
|
|
case FNC_WBLK:
|
|
case FNC_MOVE:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case DTC_RBLK: /* In reverse block number */
|
|
uptr->DELAY -=2;
|
|
sim_activate(uptr,DT_WRDTIM*2);
|
|
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
|
word++;
|
|
if (word > 01101) {
|
|
uptr->DSTATE = DTC_REND|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
|
(uptr->DSTATE & DTC_MOTMASK);
|
|
} else {
|
|
uptr->DSTATE = DTC_FBLK|(word << DTC_V_BLK)|(uptr->DSTATE & DTC_MOTMASK);
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o reverse block %o\n", u, word);
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
if (uptr->DELAY < 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
break;
|
|
}
|
|
/* Check if DCC has disconnected */
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_is_connect(dtc_dct) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
/* Check if request pending */
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_NULL);
|
|
dtc_dtsb |= DTB_ACT;
|
|
}
|
|
switch (DTC_GETFNC(uptr->CMD)) {
|
|
case FNC_RALL:
|
|
if ((dtc_dtsb & DTB_ACT) != 0 && dct_write(dtc_dct, &data, 6) == 0)
|
|
dtc_dtsb |= DTB_DONE;
|
|
break;
|
|
case FNC_SRCH:
|
|
case FNC_MOVE:
|
|
case FNC_READ:
|
|
case FNC_WRIT:
|
|
case FNC_WALL:
|
|
case FNC_WBLK:
|
|
break;
|
|
case FNC_WMRK:
|
|
dtc_dtsb |= DTB_ILL;
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
break;
|
|
}
|
|
if (dtc_dtsb & DTB_REQ) {
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_NULL);
|
|
dtc_dtsb |= DTB_ACT;
|
|
}
|
|
break;
|
|
|
|
case DTC_REND: /* In final endzone */
|
|
/* Set stop */
|
|
uptr->CMD |= DTC_FNC_STOP;
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o reverse end\n", u);
|
|
dtc_dtsb |= DTB_EOT;
|
|
if (dtc_dtsa & DTC_ETF)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
dtc_dtsb |= DTB_TIME;
|
|
if (uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if ((dtc_dtsb & DTB_DONE) != 0) {
|
|
if ((uptr->CMD & DTC_JDONE) != 0) {
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o post done\n", u);
|
|
}
|
|
|
|
dtc_dtsb &= ~(DTB_REQ|DTB_ACT);
|
|
dtc_dtsb |= DTB_NULL;
|
|
uptr->CMD &= 077077;
|
|
}
|
|
|
|
if ((dtc_dtsb & (DTB_ILL|DTB_PAR|DTB_EOT)) != 0) {
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
uptr->CMD = DTC_FNC_STOP;
|
|
}
|
|
|
|
/* Check if starting */
|
|
} else if (uptr->CMD & DTC_START) {
|
|
/* Start up delay */
|
|
sim_activate(uptr, DT_WRDTIM*10);
|
|
if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
uptr->DELAY = 0;
|
|
dtc_dtsb |= DTB_TIME;
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
if(uptr->CMD & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
}
|
|
|
|
uptr->DSTATE |= DTC_MOT;
|
|
if (uptr->CMD & DTC_RVDRV) {
|
|
uptr->DSTATE |= DTC_REV;
|
|
} else {
|
|
uptr->DSTATE &= ~DTC_REV;
|
|
}
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o start %06o\n", u, uptr->CMD);
|
|
return SCPE_OK;
|
|
} else if ((dtc_dtsb & DTB_DLY) != 0) {
|
|
uptr->DELAY = 0;
|
|
dtc_dtsb |= DTB_TIME;
|
|
dtc_dtsb &= ~DTB_DLY;
|
|
if(dtc_dtsa & DTC_TIME)
|
|
set_interrupt(DTC_DEVNUM, dtc_dtsa);
|
|
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o delay over %06o\n", u, dtc_dtsa);
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Boot from given device */
|
|
t_stat
|
|
dtc_boot(int32 unit_num, DEVICE * dptr)
|
|
{
|
|
UNIT *uptr = &dptr->units[unit_num];
|
|
uint32 *fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
uint64 word = 0;
|
|
int off;
|
|
int wc, addr;
|
|
|
|
if ((uptr->flags & UNIT_ATT) == 0)
|
|
return SCPE_UNATT; /* attached? */
|
|
|
|
off = 0;
|
|
wc = fbuf[off++]+1;
|
|
addr = fbuf[off++];
|
|
while (wc != 0777777) {
|
|
wc = (wc + 1) & RMASK;
|
|
addr = (addr + 1) & RMASK;
|
|
word = ((uint64)fbuf[off++]) << 18;
|
|
word |= (uint64)fbuf[off++];
|
|
if (addr < 020)
|
|
FM[addr] = word;
|
|
else
|
|
M[addr] = word;
|
|
}
|
|
if (addr < 020)
|
|
FM[addr] = word;
|
|
else
|
|
M[addr] = word;
|
|
uptr->DSTATE = (1 << DTC_V_BLK) | DTC_BLOCK | DTC_MOT;
|
|
sim_activate(uptr,30000);
|
|
PC = word & RMASK;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* set DCT channel and unit. */
|
|
t_stat
|
|
dtc_set_dct (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
int32 dct;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
dct = (int32) get_uint (cptr, 8, 20, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
dtc_dct = dct;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat
|
|
dtc_show_dct (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
if (uptr == NULL)
|
|
return SCPE_IERR;
|
|
|
|
fprintf (st, "DCT=%02o", dtc_dct);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat
|
|
dtc_reset (DEVICE *dptr)
|
|
{
|
|
int i;
|
|
|
|
dtc_dtsb = dtc_dtsa = 0; /* clear status */
|
|
for (i = 0; i < DTC_NUMDR; i++) {
|
|
if ((dtc_unit[i].DSTATE & DTC_MOT) != 0)
|
|
dtc_unit[i].CMD |= DTC_FNC_STOP;
|
|
}
|
|
clr_interrupt(DTC_DEVNUM);
|
|
clr_interrupt(DTC_DEVNUM|4);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine
|
|
|
|
Determine 12b, 16b, or 18b/36b format
|
|
Allocate buffer
|
|
If 12b, read 12b format and convert to 18b in buffer
|
|
If 16b, read 16b format and convert to 18b in buffer
|
|
If 18b/36b, read data into buffer
|
|
*/
|
|
|
|
t_stat
|
|
dtc_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
uint16 pdp8b[D8_NBSIZE];
|
|
uint16 pdp11b[D18_BSIZE];
|
|
uint32 ba, sz, k, *fbuf;
|
|
int32 u = uptr - dtc_dev.units;
|
|
t_stat r;
|
|
|
|
r = attach_unit (uptr, cptr); /* attach */
|
|
if (r != SCPE_OK) /* error? */
|
|
return r;
|
|
if ((sim_switches & SIM_SW_REST) == 0) { /* not from rest? */
|
|
uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT); /* default 18b */
|
|
if (sim_switches & SWMASK ('T')) /* att 12b? */
|
|
uptr->flags = uptr->flags | UNIT_8FMT;
|
|
else if (sim_switches & SWMASK ('S')) /* att 16b? */
|
|
uptr->flags = uptr->flags | UNIT_11FMT;
|
|
else if (!(sim_switches & SWMASK ('A')) && /* autosize? */
|
|
(sz = sim_fsize (uptr->fileref))) {
|
|
if (sz == D8_FILSIZ)
|
|
uptr->flags = uptr->flags | UNIT_8FMT;
|
|
else if (sz == D11_FILSIZ)
|
|
uptr->flags = uptr->flags | UNIT_11FMT;
|
|
}
|
|
}
|
|
uptr->capac = DTU_CAPAC (uptr); /* set capacity */
|
|
uptr->filebuf = calloc (uptr->capac, sizeof (uint32));
|
|
if (uptr->filebuf == NULL) { /* can't alloc? */
|
|
detach_unit (uptr);
|
|
return SCPE_MEM;
|
|
}
|
|
fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
sim_printf ("%s%d: ", sim_dname (&dtc_dev), u);
|
|
if (uptr->flags & UNIT_8FMT)
|
|
sim_printf ("12b format");
|
|
else if (uptr->flags & UNIT_11FMT)
|
|
sim_printf ("16b format");
|
|
else sim_printf ("18b/36b format");
|
|
sim_printf (", buffering file in memory\n");
|
|
uptr->WRITTEN = 0;
|
|
uptr->io_flush = dtc_flush;
|
|
if (uptr->flags & UNIT_8FMT) { /* 12b? */
|
|
for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
|
|
k = fxread (pdp8b, sizeof (uint16), D8_NBSIZE, uptr->fileref);
|
|
if (k == 0)
|
|
break;
|
|
for ( ; k < D8_NBSIZE; k++)
|
|
pdp8b[k] = 0;
|
|
for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop thru blk */
|
|
fbuf[ba] = ((uint32) (pdp8b[k] & 07777) << 6) |
|
|
((uint32) (pdp8b[k + 1] >> 6) & 077);
|
|
fbuf[ba + 1] = ((uint32) (pdp8b[k + 1] & 077) << 12) |
|
|
((uint32) pdp8b[k + 2] & 07777);
|
|
ba = ba + 2; /* end blk loop */
|
|
}
|
|
} /* end file loop */
|
|
uptr->hwmark = ba;
|
|
} else if (uptr->flags & UNIT_11FMT) { /* 16b? */
|
|
for (ba = 0; ba < uptr->capac; ) { /* loop thru file */
|
|
k = fxread (pdp11b, sizeof (uint16), D18_BSIZE, uptr->fileref);
|
|
if (k == 0)
|
|
break;
|
|
for ( ; k < D18_BSIZE; k++)
|
|
pdp11b[k] = 0;
|
|
for (k = 0; k < D18_BSIZE; k++)
|
|
fbuf[ba++] = pdp11b[k];
|
|
}
|
|
uptr->hwmark = ba;
|
|
} else uptr->hwmark = fxread (uptr->filebuf, sizeof (uint32),
|
|
uptr->capac, uptr->fileref);
|
|
uptr->flags = uptr->flags | UNIT_BUF; /* set buf flag */
|
|
uptr->pos = DT_EZLIN; /* beyond leader */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Detach routine
|
|
|
|
Cancel in progress operation
|
|
If 12b, convert 18b buffer to 12b and write to file
|
|
If 16b, convert 18b buffer to 16b and write to file
|
|
If 18b/36b, write buffer to file
|
|
Deallocate buffer
|
|
*/
|
|
|
|
void
|
|
dtc_flush (UNIT* uptr)
|
|
{
|
|
uint16 pdp8b[D8_NBSIZE];
|
|
uint16 pdp11b[D18_BSIZE];
|
|
uint32 ba, k, *fbuf;
|
|
|
|
if (uptr->WRITTEN && uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) { /* any data? */
|
|
sim_printf ("%s: writing buffer to file: %s\n", sim_uname (uptr), uptr->filename);
|
|
fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
|
rewind (uptr->fileref); /* start of file */
|
|
if (uptr->flags & UNIT_8FMT) { /* 12b? */
|
|
for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
|
|
for (k = 0; k < D8_NBSIZE; k = k + 3) { /* loop blk */
|
|
pdp8b[k] = (fbuf[ba] >> 6) & 07777;
|
|
pdp8b[k + 1] = ((fbuf[ba] & 077) << 6) |
|
|
((fbuf[ba + 1] >> 12) & 077);
|
|
pdp8b[k + 2] = fbuf[ba + 1] & 07777;
|
|
ba = ba + 2;
|
|
} /* end loop blk */
|
|
fxwrite (pdp8b, sizeof (uint16), D8_NBSIZE, uptr->fileref);
|
|
if (ferror (uptr->fileref))
|
|
break;
|
|
} /* end loop file */
|
|
} else if (uptr->flags & UNIT_11FMT) { /* 16b? */
|
|
for (ba = 0; ba < uptr->hwmark; ) { /* loop thru file */
|
|
for (k = 0; k < D18_BSIZE; k++) /* loop blk */
|
|
pdp11b[k] = fbuf[ba++] & 0177777;
|
|
fxwrite (pdp11b, sizeof (uint16), D18_BSIZE, uptr->fileref);
|
|
if (ferror (uptr->fileref))
|
|
break;
|
|
} /* end loop file */
|
|
} else fxwrite (uptr->filebuf, sizeof (uint32), /* write file */
|
|
uptr->hwmark, uptr->fileref);
|
|
if (ferror (uptr->fileref))
|
|
sim_perror ("I/O error");
|
|
uptr->WRITTEN = 0;
|
|
} /* end if hwmark */
|
|
}
|
|
|
|
t_stat
|
|
dtc_detach (UNIT* uptr)
|
|
{
|
|
int32 u = uptr - dtc_dev.units;
|
|
|
|
if (!(uptr->flags & UNIT_ATT))
|
|
return SCPE_OK;
|
|
if (sim_is_active (uptr)) {
|
|
sim_cancel (uptr);
|
|
uptr->CMD = uptr->pos = 0;
|
|
}
|
|
if (uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) /* any data? */
|
|
dtc_flush (uptr); /* end if hwmark */
|
|
free (uptr->filebuf); /* release buf */
|
|
uptr->flags = uptr->flags & ~UNIT_BUF; /* clear buf flag */
|
|
uptr->filebuf = NULL; /* clear buf ptr */
|
|
uptr->flags = uptr->flags & ~(UNIT_8FMT | UNIT_11FMT); /* default fmt */
|
|
uptr->capac = DT_CAPAC; /* default size */
|
|
return detach_unit (uptr);
|
|
}
|
|
#endif
|