59aa4a73b1
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.2 GRI - Added support for the GRI-99 processor. 1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
246 lines
9.4 KiB
C
246 lines
9.4 KiB
C
/*************************************************************************
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* *
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* $Id: s100_ss1.c 1773 2008-01-11 05:46:19Z hharte $ *
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* *
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* Copyright (c) 2007-2008 Howard M. Harte. *
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* http://www.hartetec.com *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
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* NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
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* *
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* Except as contained in this notice, the name of Howard M. Harte shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* Howard M. Harte. *
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* *
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* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
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* *
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* Module Description: *
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* CompuPro System Support 1 module for SIMH. *
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* Note this does not include the Boot ROM on the System Support 1 Card *
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* *
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* Environment: *
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* User mode only *
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* *
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*************************************************************************/
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/*#define DBG_MSG */
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#include "altairz80_defs.h"
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#if defined (_WIN32)
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#include <windows.h>
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#endif
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#ifdef DBG_MSG
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#define DBG_PRINT(args) printf args
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#else
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#define DBG_PRINT(args)
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#endif
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#define TRACE_MSG 0x01
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#define DMA_MSG 0x02
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#define SS1_MAX_DRIVES 1
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#define UNIT_V_SS1_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
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#define UNIT_SS1_VERBOSE (1 << UNIT_V_SS1_VERBOSE)
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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} SS1_INFO;
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static SS1_INFO ss1_info_data = { { 0x0, 0, 0x50, 12 } };
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/* static SS1_INFO *ss1_info = &ss1_info_data;*/
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extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
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extern uint32 PCX;
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extern REG *sim_PC;
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/* These are needed for DMA. PIO Mode has not been implemented yet. */
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extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value);
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extern uint8 GetBYTEWrapper(const uint32 Addr);
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static t_stat ss1_reset(DEVICE *ss1_dev);
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static uint8 SS1_Read(const uint32 Addr);
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static uint8 SS1_Write(const uint32 Addr, uint8 cData);
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static int32 ss1dev(const int32 port, const int32 io, const int32 data);
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static int32 trace_level = 0x00; /* Disable all tracing by default */
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static UNIT ss1_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }
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};
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static REG ss1_reg[] = {
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{ HRDATA (TRACELEVEL, trace_level, 16), },
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{ NULL }
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};
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static MTAB ss1_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL },
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/* quiet, no warning messages */
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{ UNIT_SS1_VERBOSE, 0, "QUIET", "QUIET", NULL },
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/* verbose, show warning messages */
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{ UNIT_SS1_VERBOSE, UNIT_SS1_VERBOSE, "VERBOSE", "VERBOSE", NULL },
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{ 0 }
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};
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DEVICE ss1_dev = {
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"SS1", ss1_unit, ss1_reg, ss1_mod,
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SS1_MAX_DRIVES, 10, 31, 1, SS1_MAX_DRIVES, SS1_MAX_DRIVES,
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NULL, NULL, &ss1_reset,
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NULL, NULL, NULL,
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&ss1_info_data, (DEV_DISABLE | DEV_DIS), 0,
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NULL, NULL, NULL
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};
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/* Reset routine */
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static t_stat ss1_reset(DEVICE *dptr)
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{
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
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sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, TRUE);
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} else {
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/* Connect SS1 at base address */
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if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, FALSE) != 0) {
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printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
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return SCPE_ARG;
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}
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}
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return SCPE_OK;
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}
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static int32 ss1dev(const int32 port, const int32 io, const int32 data)
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{
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DBG_PRINT(("SS1: IO %s, Port %02x\n", io ? "WR" : "RD", port));
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if(io) {
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SS1_Write(port, data);
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return 0;
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} else {
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return(SS1_Read(port));
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}
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}
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#define SS1_M8259_L 0x00
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#define SS1_M8259_H 0x01
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#define SS1_S8259_L 0x02
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#define SS1_S8259_H 0x03
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#define SS1_8253_TC0 0x04
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#define SS1_8253_TC1 0x05
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#define SS1_8253_TC2 0x06
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#define SS1_8253_CTL 0x07
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#define SS1_9511A_DATA 0x08
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#define SS1_9511A_CMD 0x09
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#define SS1_RTC_CMD 0x0A
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#define SS1_RTC_DATA 0x0B
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#define SS1_UART_DATA 0x0C
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#define SS1_UART_STAT 0x0D
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#define SS1_UART_MODE 0x0E
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#define SS1_UART_CMD 0x0F
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extern int32 sio0d(const int32 port, const int32 io, const int32 data);
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extern int32 sio0s(const int32 port, const int32 io, const int32 data);
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static uint8 SS1_Read(const uint32 Addr)
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{
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uint8 cData = 0x00;
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switch(Addr & 0x0F) {
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case SS1_M8259_L:
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case SS1_M8259_H:
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case SS1_S8259_L:
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case SS1_S8259_H:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Interrupt Controller not Implemented." NLP, PCX));
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break;
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case SS1_8253_TC0:
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case SS1_8253_TC1:
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case SS1_8253_TC2:
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case SS1_8253_CTL:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Timer not Implemented." NLP, PCX));
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break;
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case SS1_9511A_DATA:
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case SS1_9511A_CMD:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Math Coprocessor not Implemented." NLP, PCX));
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break;
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case SS1_RTC_CMD:
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case SS1_RTC_DATA:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: RTC not Implemented." NLP, PCX));
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break;
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case SS1_UART_DATA:
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cData = sio0d(Addr, 0, 0);
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break;
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case SS1_UART_STAT:
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cData = sio0s(Addr, 0, 0);
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break;
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case SS1_UART_MODE:
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case SS1_UART_CMD:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: UART not Implemented." NLP, PCX));
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break;
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}
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return (cData);
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}
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static uint8 SS1_Write(const uint32 Addr, uint8 cData)
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{
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switch(Addr & 0x0F) {
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case SS1_M8259_L:
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case SS1_M8259_H:
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case SS1_S8259_L:
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case SS1_S8259_H:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Interrupt Controller not Implemented." NLP, PCX));
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break;
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case SS1_8253_TC0:
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case SS1_8253_TC1:
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case SS1_8253_TC2:
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case SS1_8253_CTL:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Timer not Implemented." NLP, PCX));
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break;
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case SS1_9511A_DATA:
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case SS1_9511A_CMD:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Math Coprocessor not Implemented." NLP, PCX));
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break;
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case SS1_RTC_CMD:
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case SS1_RTC_DATA:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: RTC not Implemented." NLP, PCX));
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break;
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case SS1_UART_DATA:
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sio0d(Addr, 1, cData);
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break;
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case SS1_UART_STAT:
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sio0s(Addr, 1, cData);
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break;
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case SS1_UART_MODE:
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case SS1_UART_CMD:
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TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: UART not Implemented." NLP, PCX));
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break;
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}
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return(0);
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}
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