5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
763 lines
28 KiB
C
763 lines
28 KiB
C
/* lgp_cpu.c: LGP CPU simulator
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Copyright (c) 2004-2008, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu LGP-30 [LGP-21] CPU
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22-Sep-05 RMS Fixed declarations (Sterling Garwood)
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04-Sep-05 RMS Fixed missing returns (Peter Schorn)
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04-Jan-05 RMS Modified VM pointer setup
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The system state for the LGP-30 [LGP-21] is:
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A<0:31> accumulator
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C<0:11> counter (PC)
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OVF overflow flag [LGP-21 only]
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The LGP-30 [LGP-21] has just one instruction format:
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1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
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0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|S| |opcode | | operand address | |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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LGP-30 instructions:
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<0,12:15> operation
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0 stop
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1 A <- M[ea]
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2 M[ea]<addr> <- A<addr>
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3 M[ea]<addr> <- C + 1
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4 input
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5 A <- A / M[ea]
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6 A <- A * M[ea], low result
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7 A <- A * M[ea], high result
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8 output
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9 A <- A & M[ea]
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A C <- ea
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B C <- ea if A < 0
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-B C <- ea if (A < 0) || T-switch set
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C M[ea] <- A
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D M[ea] <- A, A <- 0
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E A <- A + M[ea]
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F A <- A - M[ea]
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LGP-21 instructions:
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<0,12:15> operation
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0 stop; sense and skip
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-0 stop; sense overflow and skip
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1 A <- M[ea]
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2 M[ea]<addr> <- A<addr>
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3 M[ea]<addr> <- C + 1
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4 6b input
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-4 4b input
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5 A <- A / M[ea]
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6 A <- A * M[ea], low result
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7 A <- A * M[ea], high result
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8 6b output
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-8 4b output
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9 A <- A & M[ea]
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A C <- ea
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B C <- ea if A < 0
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-B C <- ea if (A < 0) || T-switch set
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C M[ea] <- A
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D M[ea] <- A, A <- 0
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E A <- A + M[ea]
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F A <- A - M[ea]
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The LGP-30 [LGP-21] has 4096 32b words of memory. The low order
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bit is always read and stored as 0. The LGP-30 uses a drum for
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memory, with 64 tracks of 64 words. The LGP-21 uses a disk for
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memory, with 32 tracks of 128 words.
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This routine is the instruction decode routine for the LGP-30
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[LGP-21]. It is called from the simulator control program to
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execute instructions in simulated memory, starting at the simulated
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PC. It runs until 'reason' is set non-zero.
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General notes:
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1. Reasons to stop. The simulator can be stopped by:
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STOP instruction
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breakpoint encountered
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overflow [LGP-30]
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I/O error in I/O simulator
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2. Interrupts. There are no interrupts.
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3. Non-existent memory. All of memory always exists.
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4. Adding I/O devices. The LGP-30 could not support additional
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I/O devices. The LGP-21 could but none are known.
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*/
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#include "lgp_defs.h"
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC - 1) & AMASK;
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#define M16 0xFFFF
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#define M32 0xFFFFFFFF
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#define NEG(x) ((~(x) + 1) & DMASK)
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#define ABS(x) (((x) & SIGN)? NEG (x): (x))
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uint32 M[MEMSIZE] = { 0 }; /* memory */
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uint32 PC = 0; /* counter */
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uint32 A = 0; /* accumulator */
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uint32 IR = 0; /* instr register */
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uint32 OVF = 0; /* overflow indicator */
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uint32 t_switch = 0; /* transfer switch */
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uint32 bp32 = 0; /* BP32 switch */
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uint32 bp16 = 0; /* BP16 switch */
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uint32 bp8 = 0; /* BP8 switch */
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uint32 bp4 = 0; /* BP4 switch */
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uint32 inp_strt = 0; /* input started */
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uint32 inp_done = 0; /* input done */
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uint32 out_strt = 0; /* output started */
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uint32 out_done = 0; /* output done */
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uint32 lgp21_sov = 0; /* LGP-21 sense pending */
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int32 delay = 0;
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int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat cpu_set_30opt (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_set_30opt_i (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_set_30opt_o (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_set_fill (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_set_exec (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat cpu_one_inst (uint32 opc, uint32 ir);
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uint32 Mul64 (uint32 a, uint32 b, uint32 *low);
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t_bool Div32 (uint32 dvd, uint32 dvr, uint32 *q);
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uint32 I_delay (uint32 opc, uint32 ea, uint32 op);
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uint32 shift_in (uint32 a, uint32 dat, uint32 sh4);
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extern t_stat op_p (uint32 dev, uint32 ch);
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extern t_stat op_i (uint32 dev, uint32 ch, uint32 sh4);
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extern void lgp_vm_init (void);
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/* CPU data structures
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cpu_dev CPU device descriptor
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cpu_unit CPU unit descriptor
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cpu_reg CPU register list
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cpu_mod CPU modifiers list
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*/
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UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_IN4B+UNIT_TTSS_D, MEMSIZE) };
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REG cpu_reg[] = {
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{ DRDATA (C, PC, 12), REG_VMAD },
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{ HRDATA (A, A, 32), REG_VMIO },
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{ HRDATA (IR, IR, 32), REG_VMIO },
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{ FLDATA (OVF, OVF, 0) },
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{ FLDATA (TSW, t_switch, 0) },
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{ FLDATA (BP32, bp32, 0) },
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{ FLDATA (BP16, bp16, 0) },
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{ FLDATA (BP8, bp8, 0) },
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{ FLDATA (BP4, bp4, 0) },
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{ FLDATA (INPST, inp_strt, 0) },
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{ FLDATA (INPDN, inp_done, 0) },
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{ FLDATA (OUTST, out_strt, 0) },
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{ FLDATA (OUTDN, out_done, 0) },
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{ DRDATA (DELAY, delay, 7) },
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{ BRDATA (CQ, pcq, 16, 12, PCQ_SIZE), REG_RO + REG_CIRC },
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{ HRDATA (CQP, pcq_p, 6), REG_HRO },
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{ HRDATA (WRU, sim_int_char, 8) },
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{ NULL }
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};
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MTAB cpu_mod[] = {
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{ UNIT_LGP21, UNIT_LGP21, "LGP-21", "LGP21", &cpu_set_model, &cpu_show_model },
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{ UNIT_LGP21, 0, "LGP-30", "LGP30", &cpu_set_model, &cpu_show_model },
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{ UNIT_TTSS_D, UNIT_TTSS_D, 0, "TRACK" },
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{ UNIT_TTSS_D, 0, 0, "NORMAL" },
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{ UNIT_LGPH_D, UNIT_LGPH_D, 0, "LGPHEX" },
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{ UNIT_LGPH_D, 0, 0, "STANDARDHEX" },
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{ UNIT_MANI, UNIT_MANI, NULL, "MANUAL" },
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{ UNIT_MANI, 0, NULL, "TAPE" },
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{ UNIT_IN4B, UNIT_IN4B, NULL, "4B", &cpu_set_30opt },
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{ UNIT_IN4B, 0, NULL, "6B", &cpu_set_30opt },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "INPUT", &cpu_set_30opt_i },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "OUTPUT", &cpu_set_30opt_o },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "EXECUTE", &cpu_set_exec },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "FILL", &cpu_set_fill },
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{ 0 }
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};
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DEVICE cpu_dev = {
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"CPU", &cpu_unit, cpu_reg, cpu_mod,
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1, 10, 12, 1, 16, 32,
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&cpu_ex, &cpu_dep, &cpu_reset,
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NULL, NULL, NULL
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};
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/* Timing tables */
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/* Optimization minima and maxima
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Z B Y R I D N M P E U T H C A S */
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static const int32 min_30[16] = {
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
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};
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static const int32 max_30[16] = {
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7, 7, 7, 7, 7, 5, 8, 6, 7, 7, 0, 0, 7, 7, 7, 7
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};
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static const int32 min_21[16] = {
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
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};
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static const int32 max_21[16] = {
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0, 16, 16, 16, 0, 58, 81, 79, 0, 16, 0, 0, 16, 16, 16, 16
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};
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static const uint32 log_to_phys_30[NSC_30] = { /* drum interlace chart */
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0, 57, 50, 43, 36, 29, 22, 15, 8 ,
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1, 58, 51, 44, 37, 30, 23, 16, 9 ,
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2, 59, 52, 45, 38, 31, 24, 17, 10,
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3, 60, 53, 46, 39, 32, 25, 18, 11,
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4, 61, 54, 47, 40, 33, 26, 19, 12,
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5, 62, 55, 48, 41, 32, 27, 20, 13,
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6, 63, 56, 49, 42, 33, 28, 21, 14,
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7
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};
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static const uint32 log_to_phys_21[NSC_21] = { /* disk interlace chart */
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0, 64, 57, 121, 50, 114, 43, 107, 36, 100, 29, 93, 22, 86, 15, 79, 8, 72,
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1, 65, 58, 122, 51, 115, 44, 108, 37, 101, 30, 94, 23, 87, 16, 80, 9, 73,
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2, 66, 59, 123, 52, 116, 45, 109, 38, 102, 31, 95, 24, 88, 17, 81, 10, 74,
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3, 67, 60, 124, 53, 117, 46, 110, 39, 103, 32, 96, 25, 89, 18, 82, 11, 75,
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4, 68, 61, 125, 54, 118, 47, 111, 40, 104, 33, 97, 26, 90, 19, 83, 12, 76,
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5, 69, 62, 126, 55, 119, 48, 112, 41, 105, 34, 98, 27, 91, 20, 84, 12, 77,
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6, 70, 63, 127, 56, 120, 49, 113, 42, 106, 35, 99, 28, 92, 21, 85, 13, 78,
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7, 71
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};
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t_stat sim_instr (void)
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{
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t_stat r = 0;
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uint32 oPC;
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/* Restore register state */
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PC = PC & AMASK; /* mask PC */
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sim_cancel_step (); /* defang SCP step */
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if (lgp21_sov) { /* stop sense pending? */
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lgp21_sov = 0;
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if (!OVF) /* ovf off? skip */
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PC = (PC + 1) & AMASK;
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else OVF = 0; /* on? reset */
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}
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/* Main instruction fetch/decode loop */
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do {
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if (sim_interval <= 0) { /* check clock queue */
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if ((r = sim_process_event ()))
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break;
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}
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if (delay > 0) { /* delay to next instr */
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delay = delay - 1; /* count down delay */
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sim_interval = sim_interval - 1;
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continue; /* skip execution */
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}
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if (sim_brk_summ && /* breakpoint? */
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sim_brk_test (PC, SWMASK ('E'))) {
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r = STOP_IBKPT; /* stop simulation */
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break;
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}
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IR = Read (oPC = PC); /* get instruction */
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PC = (PC + 1) & AMASK; /* increment PC */
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sim_interval = sim_interval - 1;
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if ((r = cpu_one_inst (oPC, IR))) { /* one instr; error? */
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if (r == STOP_STALL) { /* stall? */
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PC = oPC; /* back up PC */
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delay = r = 0; /* no delay */
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}
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else break;
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}
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if (sim_step && (--sim_step <= 0)) /* do step count */
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r = SCPE_STOP;
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} while (r == 0); /* loop until halted */
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pcq_r->qptr = pcq_p; /* update pc q ptr */
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return r;
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}
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/* Execute one instruction */
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t_stat cpu_one_inst (uint32 opc, uint32 ir)
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{
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uint32 ea, op, dat, res, dev, sh4, ch;
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t_bool ovf_this_cycle = FALSE;
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t_stat reason = 0;
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op = I_GETOP (ir); /* opcode */
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ea = I_GETEA (ir); /* address */
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switch (op) { /* case on opcode */
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/* Loads, stores, transfers instructions */
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case OP_B: /* bring */
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A = Read (ea); /* A <- M[ea] */
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delay = I_delay (opc, ea, op);
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break;
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case OP_H: /* hold */
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Write (ea, A); /* M[ea] <- A */
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delay = I_delay (opc, ea, op);
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break;
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case OP_C: /* clear */
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Write (ea, A); /* M[ea] <- A */
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A = 0; /* A <- 0 */
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delay = I_delay (opc, ea, op);
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break;
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case OP_Y: /* store address */
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dat = Read (ea); /* get operand */
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dat = (dat & ~I_EA) | (A & I_EA); /* merge address */
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Write (ea, dat);
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delay = I_delay (opc, ea, op);
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break;
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case OP_R: /* return address */
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dat = Read (ea); /* get operand */
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dat = (dat & ~I_EA) | (((PC + 1) & AMASK) << I_V_EA);
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Write (ea, dat);
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delay = I_delay (opc, ea, op);
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break;
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case OP_U: /* uncond transfer */
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PCQ_ENTRY;
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PC = ea; /* transfer */
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delay = I_delay (opc, ea, op);
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break;
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case OP_T: /* conditional transfer */
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if ((A & SIGN) || /* A < 0 or */
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((ir & SIGN) && t_switch)) { /* -T and Tswitch set? */
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PCQ_ENTRY;
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PC = ea; /* transfer */
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}
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delay = I_delay (opc, ea, op);
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break;
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/* Arithmetic and logical instructions */
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case OP_A: /* add */
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dat = Read (ea); /* get operand */
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res = (A + dat) & DMASK; /* add */
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if ((~A ^ dat) & (dat ^ res) & SIGN) /* calc overflow */
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ovf_this_cycle = TRUE;
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A = res; /* save result */
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delay = I_delay (opc, ea, op);
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break;
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case OP_S: /* sub */
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dat = Read (ea); /* get operand */
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res = (A - dat) & DMASK; /* subtract */
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if ((A ^ dat) & (~dat ^ res) & SIGN) /* calc overflow */
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ovf_this_cycle = TRUE;
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A = res;
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delay = I_delay (opc, ea, op);
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break;
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case OP_M: /* multiply high */
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dat = Read (ea); /* get operand */
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A = (Mul64 (A, dat, NULL) << 1) & DMASK; /* multiply */
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delay = I_delay (opc, ea, op);
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break;
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case OP_N: /* multiply low */
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dat = Read (ea); /* get operand */
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Mul64 (A, dat, &res); /* multiply */
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A = res; /* keep low result */
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delay = I_delay (opc, ea, op); /* total delay */
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break;
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case OP_D: /* divide */
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dat = Read (ea); /* get operand */
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if (Div32 (A, dat, &A)) /* divide; overflow? */
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ovf_this_cycle = TRUE;
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delay = I_delay (opc, ea, op);
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break;
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case OP_E: /* extract */
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dat = Read (ea); /* get operand */
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A = A & dat; /* and */
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delay = I_delay (opc, ea, op);
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break;
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/* IO instructions */
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case OP_P: /* output */
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if (Q_LGP21) { /* LGP-21 */
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ch = A >> 26; /* char, 6b */
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if (ir & SIGN) /* 4b? convert */
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ch = (ch & 0x3C) | 2;
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dev = I_GETTK (ir); /* device select */
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}
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else { /* LGP-30 */
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ch = I_GETTK (ir); /* char, always 6b */
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dev = Q_OUTPT? DEV_PT: DEV_TT; /* device select */
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}
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reason = op_p (dev & DEV_MASK, ch); /* output */
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delay = I_delay (sim_grtime (), ea, op); /* next instruction */
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break;
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|
|
case OP_I: /* input */
|
|
if (Q_LGP21) { /* LGP-21 */
|
|
ch = 0; /* initial shift */
|
|
sh4 = ir & SIGN; /* 4b/6b select */
|
|
dev = I_GETTK (ir); /* device select */
|
|
}
|
|
else { /* LGP-30 */
|
|
ch = I_GETTK (ir); /* initial shift */
|
|
sh4 = Q_IN4B; /* 4b/6b select */
|
|
dev = Q_INPT? DEV_PT: DEV_TT; /* device select */
|
|
}
|
|
if (dev == DEV_SHIFT) /* shift? */
|
|
A = shift_in (A, 0, sh4); /* shift 4/6b */
|
|
else reason = op_i (dev & DEV_MASK, ch, sh4); /* input */
|
|
delay = I_delay (sim_grtime (), ea, op); /* next instruction */
|
|
break;
|
|
|
|
case OP_Z:
|
|
if (Q_LGP21) { /* LGP-21 */
|
|
if (ea & 0xF80) { /* no stop? */
|
|
if (((ea & 0x800) && !bp32) || /* skip if any */
|
|
((ea & 0x400) && !bp16) || /* selected switch */
|
|
((ea & 0x200) && !bp8) || /* is off */
|
|
((ea & 0x100) && !bp4) || /* or if */
|
|
((ir & SIGN) && !OVF)) /* ovf sel and off */
|
|
PC = (PC + 1) & AMASK;
|
|
if (ir & SIGN) /* -Z? clr overflow */
|
|
OVF = 0;
|
|
}
|
|
else { /* stop */
|
|
lgp21_sov = (ir & SIGN)? 1: 0; /* pending sense? */
|
|
reason = STOP_STOP; /* stop */
|
|
}
|
|
}
|
|
else { /* LGP-30 */
|
|
if (out_done) /* P complete? */
|
|
out_done = 0;
|
|
else if (((ea & 0x800) && bp32) || /* bpt switch set? */
|
|
((ea & 0x400) && bp16) ||
|
|
((ea & 0x200) && bp8) ||
|
|
((ea & 0x100) && bp4)) ; /* don't stop or stall */
|
|
else if (out_strt) /* P pending? stall */
|
|
reason = STOP_STALL;
|
|
else reason = STOP_STOP; /* no, stop */
|
|
}
|
|
delay = I_delay (sim_grtime (), ea, op); /* next instruction */
|
|
break; /* end switch */
|
|
}
|
|
|
|
if (ovf_this_cycle) {
|
|
if (Q_LGP21) /* LGP-21? set OVF */
|
|
OVF = 1;
|
|
else reason = STOP_OVF; /* LGP-30? stop */
|
|
}
|
|
return reason;
|
|
}
|
|
|
|
/* Support routines */
|
|
|
|
uint32 Read (uint32 ea)
|
|
{
|
|
return M[ea] & MMASK;
|
|
}
|
|
|
|
void Write (uint32 ea, uint32 dat)
|
|
{
|
|
M[ea] = dat & MMASK;
|
|
return;
|
|
}
|
|
|
|
/* Input shift */
|
|
|
|
uint32 shift_in (uint32 a, uint32 dat, uint32 sh4)
|
|
{
|
|
if (sh4)
|
|
return (((a << 4) | (dat >> 2)) & DMASK);
|
|
return (((a << 6) | dat) & DMASK);
|
|
}
|
|
|
|
/* 32b * 32b multiply, signed */
|
|
|
|
uint32 Mul64 (uint32 a, uint32 b, uint32 *low)
|
|
{
|
|
uint32 sgn = a ^ b;
|
|
uint32 ah, bh, al, bl, rhi, rlo, rmid1, rmid2;
|
|
|
|
if ((a == 0) || (b == 0)) { /* zero argument? */
|
|
if (low)
|
|
*low = 0;
|
|
return 0;
|
|
}
|
|
a = ABS (a);
|
|
b = ABS (b);
|
|
ah = (a >> 16) & M16; /* split operands */
|
|
bh = (b >> 16) & M16; /* into 16b chunks */
|
|
al = a & M16;
|
|
bl = b & M16;
|
|
rhi = ah * bh; /* high result */
|
|
rmid1 = ah * bl;
|
|
rmid2 = al * bh;
|
|
rlo = al * bl;
|
|
rhi = rhi + ((rmid1 >> 16) & M16) + ((rmid2 >> 16) & M16);
|
|
rmid1 = (rlo + (rmid1 << 16)) & M32; /* add mid1 to lo */
|
|
if (rmid1 < rlo) /* carry? incr hi */
|
|
rhi = rhi + 1;
|
|
rmid2 = (rmid1 + (rmid2 << 16)) & M32; /* add mid2 to to */
|
|
if (rmid2 < rmid1) /* carry? incr hi */
|
|
rhi = rhi + 1;
|
|
if (sgn & SIGN) { /* result negative? */
|
|
rmid2 = NEG (rmid2); /* negate */
|
|
rhi = (~rhi + (rmid2 == 0)) & M32;
|
|
}
|
|
if (low) /* low result */
|
|
*low = rmid2;
|
|
return rhi & M32;
|
|
}
|
|
|
|
/* 32b/32b divide (done as 32b'0/32b) */
|
|
|
|
t_bool Div32 (uint32 dvd, uint32 dvr, uint32 *q)
|
|
{
|
|
uint32 sgn = dvd ^ dvr;
|
|
uint32 i, quo;
|
|
|
|
dvd = ABS (dvd);
|
|
dvr = ABS (dvr);
|
|
if (dvd >= dvr)
|
|
return TRUE;
|
|
for (i = quo = 0; i < 31; i++) { /* 31 iterations */
|
|
quo = quo << 1; /* shift quotient */
|
|
dvd = dvd << 1; /* shift dividend */
|
|
if (dvd >= dvr) { /* step work? */
|
|
dvd = (dvd - dvr) & M32; /* subtract dvr */
|
|
quo = quo + 1;
|
|
}
|
|
}
|
|
quo = (quo + 1) & MMASK; /* round low bit */
|
|
if (sgn & SIGN) /* result -? */
|
|
quo = NEG (quo);
|
|
if (q) /* return quo */
|
|
*q = quo;
|
|
return FALSE; /* no overflow */
|
|
}
|
|
|
|
/* Rotational delay */
|
|
|
|
uint32 I_delay (uint32 opc, uint32 ea, uint32 op)
|
|
{
|
|
uint32 tmin = Q_LGP21? min_21[op]: min_30[op];
|
|
uint32 tmax = Q_LGP21? max_21[op]: max_30[op];
|
|
uint32 nsc, curp, newp, oprp, pcdelta, opdelta;
|
|
|
|
if (Q_LGP21) { /* LGP21 */
|
|
nsc = NSC_21; /* full rotation delay */
|
|
curp = log_to_phys_21[opc & SCMASK_21]; /* current phys pos */
|
|
newp = log_to_phys_21[PC & SCMASK_21]; /* new PC phys pos */
|
|
oprp = log_to_phys_21[ea & SCMASK_21]; /* ea phys pos */
|
|
pcdelta = (newp - curp + NSC_21) & SCMASK_21;
|
|
opdelta = (oprp - curp + NSC_21) & SCMASK_21;
|
|
}
|
|
else {
|
|
nsc = NSC_30;
|
|
curp = log_to_phys_30[opc & SCMASK_30];
|
|
newp = log_to_phys_30[PC & SCMASK_30];
|
|
oprp = log_to_phys_30[ea & SCMASK_30];
|
|
pcdelta = (newp - curp + NSC_30) & SCMASK_30;
|
|
opdelta = (oprp - curp + NSC_30) & SCMASK_30;
|
|
}
|
|
if (tmax == 0) { /* skip ea calc? */
|
|
if (pcdelta >= tmin) /* new PC >= min? */
|
|
return pcdelta - 1;
|
|
return pcdelta + nsc - 1;
|
|
}
|
|
if ((opdelta >= tmin) && (opdelta <= tmax))
|
|
return pcdelta - 1;
|
|
return pcdelta + nsc - 1;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat cpu_reset (DEVICE *dptr)
|
|
{
|
|
OVF = 0;
|
|
inp_strt = 0;
|
|
inp_done = 0;
|
|
out_strt = 0;
|
|
out_done = 0;
|
|
lgp21_sov = 0;
|
|
delay = 0;
|
|
lgp_vm_init ();
|
|
pcq_r = find_reg ("CQ", NULL, dptr);
|
|
if (pcq_r)
|
|
pcq_r->qptr = 0;
|
|
else return SCPE_IERR;
|
|
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Validate option, must be LGP30 */
|
|
|
|
t_stat cpu_set_30opt (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
if (Q_LGP21)
|
|
return SCPE_ARG;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Validate input option, must be LGP30 */
|
|
|
|
t_stat cpu_set_30opt_i (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
if (Q_LGP21 || (cptr == NULL))
|
|
return SCPE_ARG;
|
|
if (strcmp (cptr, "TTI") == 0)
|
|
uptr->flags = uptr->flags & ~UNIT_INPT;
|
|
else if (strcmp (cptr, "PTR") == 0)
|
|
uptr->flags = uptr->flags | UNIT_INPT;
|
|
else return SCPE_ARG;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Validate output option, must be LGP30 */
|
|
|
|
t_stat cpu_set_30opt_o (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
if (Q_LGP21 || (cptr == NULL))
|
|
return SCPE_ARG;
|
|
if (strcmp (cptr, "TTO") == 0)
|
|
uptr->flags = uptr->flags & ~UNIT_OUTPT;
|
|
else if (strcmp (cptr, "PTP") == 0)
|
|
uptr->flags = uptr->flags | UNIT_OUTPT;
|
|
else return SCPE_ARG;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Set CPU to LGP21 or LPG30 */
|
|
|
|
t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
if (val)
|
|
uptr->flags = uptr->flags & ~(UNIT_IN4B|UNIT_INPT|UNIT_OUTPT);
|
|
return reset_all (0);
|
|
}
|
|
|
|
/* Show CPU type and all options */
|
|
|
|
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
fputs (Q_LGP21? "LGP-21": "LGP-30", st);
|
|
if (uptr->flags & UNIT_TTSS_D)
|
|
fputs (", track/sector", st);
|
|
if (uptr->flags & UNIT_LGPH_D)
|
|
fputs (", LGP hex", st);
|
|
fputs (Q_MANI? ", manual": ", tape", st);
|
|
if (!Q_LGP21) {
|
|
fputs (Q_IN4B? ", 4b": ", 6b", st);
|
|
fputs (Q_INPT? ", in=PTR": ", in=TTI", st);
|
|
fputs (Q_OUTPT? ", out=PTP": ", out=TTO", st);
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory examine */
|
|
|
|
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
if (addr >= MEMSIZE)
|
|
return SCPE_NXM;
|
|
if (vptr != NULL)
|
|
*vptr = Read (addr);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory deposit */
|
|
|
|
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
if (addr >= MEMSIZE)
|
|
return SCPE_NXM;
|
|
Write (addr, val);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Execute */
|
|
|
|
t_stat cpu_set_exec (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
uint32 inst;
|
|
t_stat r;
|
|
|
|
if (cptr) {
|
|
inst = get_uint (cptr, 16, DMASK, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
}
|
|
else inst = IR;
|
|
while ((r = cpu_one_inst (PC, inst)) == STOP_STALL) {
|
|
sim_interval = 0;
|
|
if ((r = sim_process_event ()))
|
|
return r;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
/* Fill */
|
|
|
|
t_stat cpu_set_fill (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
uint32 inst;
|
|
t_stat r;
|
|
|
|
if (cptr) {
|
|
inst = get_uint (cptr, 16, DMASK, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
IR = inst;
|
|
}
|
|
else IR = A;
|
|
return SCPE_OK;
|
|
}
|