458ab73c4f
- Debug: Output the character received, if printable. - Eliminate type slicing warnings (uint32 -> uint16)
708 lines
17 KiB
C
708 lines
17 KiB
C
/* tt2500_cpu.c: TT2500 CPU simulator
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Copyright (c) 2020, Lars Brinkhoff
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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LARS BRINKHOFF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Lars Brinkhoff shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Lars Brinkhoff.
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*/
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#include "tt2500_defs.h"
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#ifdef USE_DISPLAY
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#include "display/display.h"
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#endif
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/* Debug */
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#define DBG_CPU 0001
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#define DBG_FET 0002
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#define DBG_EXE 0004
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#define DBG_STATE 0010
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#define DBG_INT 0020
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/* CPU state. */
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static uint16 PC;
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static uint16 IR;
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static int ROM = 1;
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int C, V, N, Z;
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static uint16 IM = 0;
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static uint16 STACK[16];
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static uint16 SP = 0;
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static uint16 R[64];
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static uint16 RES, FLAGS, INTS, STARS;
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static uint16 new_XR;
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static int halt;
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typedef struct {
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uint16 PC;
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uint16 IR;
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uint16 MA;
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uint16 MB;
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uint16 AC;
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uint16 L;
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} HISTORY;
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static HISTORY *history = NULL;
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static uint32 history_i, history_m, history_n;
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/* Function declaration. */
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static t_stat cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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static t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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static t_stat cpu_ex (t_value *vptr, t_addr ea, UNIT *uptr, int32 sw);
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static t_stat cpu_dep (t_value val, t_addr ea, UNIT *uptr, int32 sw);
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static t_stat cpu_reset (DEVICE *dptr);
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static void cpu_update (void);
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static UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, 020000) };
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static BITFIELD flags_bits[] = {
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BIT(KB),
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BIT(RSD),
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BITNCF(2),
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ENDBITS
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};
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static BITFIELD ints_bits[] = {
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BIT(2KHZ),
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BIT(RRD),
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BIT(60HZ),
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BITNC,
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ENDBITS
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};
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static BITFIELD stars_bits[] = {
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BIT(WRAP),
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BIT(MINUS1),
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ENDBITS
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};
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REG cpu_reg[] = {
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{ ORDATAD (PC, PC, 13, "Program Counter") },
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{ ORDATAD (ROM, ROM, 1, "Read from ROM") },
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{ ORDATAD (IR, IR, 16, "Instruction") },
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{ ORDATAD (XR, R[REG_XR], 12, "Execute register") },
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{ ORDATAD (A, R[REG_ALATCH], 16, "A latch") },
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{ ORDATAD (IM, IM, 16, "Immediate") },
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{ ORDATAD (RES, RES, 16, "Result") },
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{ HRDATADF (FLAGS, FLAGS, 4, "Flags", flags_bits ) },
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{ HRDATADF (INTS, INTS, 4, "Interrupts", ints_bits ) },
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{ HRDATADF (STARS, STARS, 4, "Stars", stars_bits ) },
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{ BRDATAD (REG, R, 8, 16, 64, "Registers") },
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{ NULL }
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};
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static MTAB cpu_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
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&cpu_set_hist, &cpu_show_hist },
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{ 0 }
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};
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static DEBTAB cpu_deb[] = {
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{ "CPU", DBG_CPU },
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{ "FETCH", DBG_FET },
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{ "EXECUTE", DBG_EXE },
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{ "STATE", DBG_STATE },
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{ "INT", DBG_INT },
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{ NULL, 0 }
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};
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DEVICE cpu_dev = {
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"CPU", &cpu_unit, cpu_reg, cpu_mod,
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0, 8, 16, 1, 8, 16,
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&cpu_ex, &cpu_dep, &cpu_reset,
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NULL, NULL, NULL, NULL, DEV_DEBUG, 0, cpu_deb,
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NULL, NULL, NULL, NULL, NULL, NULL
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};
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static uint16 crm_read (uint16 addr)
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{
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if (ROM && addr < 32)
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return tt2500_rom[addr];
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ROM = 0;
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return CRM[addr];
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}
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static uint16 bus_read (uint16 reg)
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{
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if ((reg & 060) == 020) {
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RES = dev_tab[reg]->read (reg);
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sim_debug (DBG_STATE, &cpu_dev, "%06o <= BUS[%02o]\n", RES, reg);
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} else {
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RES = R[reg];
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}
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return RES;
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}
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static uint16 cpu_rot (uint16 data, uint16 n)
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{
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return (data >> n) + (data << (16 - n));
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}
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static uint16 cpu_ars (uint16 data, uint16 n)
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{
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uint32 sign = 0;
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if (data & 0100000)
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sign = 0177777u << 16;
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return (data >> n) + ((uint16) (sign >> n));
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}
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uint16 cpu_alu (uint16 insn, uint16 op, uint16 adata, uint16 bdata)
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{
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uint32 result;
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V = 0;
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switch (op) {
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case ALU_A: result = adata; break;
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case ALU_ANDN: result = adata & ~bdata; break;
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case ALU_AND: result = adata & bdata; break;
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case ALU_NOR: result = (~(adata | bdata)) & 0177777; break;
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case ALU_IOR: result = adata | bdata; break;
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case ALU_XOR: result = adata ^ bdata; break;
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case ALU_MROT: result = adata & cpu_rot (R[R[REG_ALATCH]], insn & 017); break;
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case ALU_ROT: result = cpu_rot (adata, insn & 017); break;
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case ALU_DEC: result = adata - 1; V = (result == 077777); break;
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case ALU_XADD: bdata += C; /* Fall through. */
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case ALU_ADD:
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result = adata + bdata;
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V = (((~adata ^ bdata) & (bdata ^ result)) >> 15) & 1;
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break;
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case ALU_XSUB: bdata += C; /* Fall through. */
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case ALU_SUB:
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result = adata - bdata;
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V = (((adata ^ bdata) & (~bdata ^ result)) >> 15) & 1;
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break;
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case ALU_INC: result = adata + 1; V = (result == 0100000); break;
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case ALU_ARS: result = cpu_ars (adata, insn & 017); break;
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default: result = 0; break;
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}
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C = !!(result & 0200000);
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result &= 0177777;
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N = !!(result & 0100000);
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Z = (result == 0);
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sim_debug (DBG_STATE, &cpu_dev, "ALU: %06o %06o => %06o (%c%c%c%c)\n",
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adata, bdata, result,
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C ? 'C' : '-',
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V ? 'V' : '-',
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N ? 'N' : '-',
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Z ? 'Z' : '-');
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return result;
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}
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static uint16 mem_read (uint16 address)
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{
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if ((address & 0170000) == 0170000 && (DSR & DSR_TVON) == 0)
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return FONT[address - 0170000];
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else
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return MEM[address];
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}
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static void mem_write (uint16 address, uint16 data)
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{
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if ((address & 0170000) == 0170000 && (DSR & DSR_TVON) == 0)
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FONT[address - 0170000] = (uint8)data;
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else
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MEM[address] = data;
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}
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static void cpu_reg_op (uint16 insn)
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{
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uint16 a = (insn >> 6) & 7;
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uint16 b = insn & 7;
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uint16 alu_op;
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uint16 adata;
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uint16 bdata;
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uint16 result;
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if (IM != 0) {
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adata = IR;
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IM = 0;
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} else if ((insn & 01000) != 0 && (insn & 030000) != 020000) {
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IM = IR;
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return;
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} else
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adata = R[a];
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if (insn & 010)
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bdata = 0;
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else
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bdata = R[b];
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alu_op = insn & 06060;
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if ((insn & 030000) == 020000) {
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if ((insn & 01000) == 0) {
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if (insn & 04000) {
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sim_debug (DBG_STATE, &cpu_dev, "MEM[%06o] <= %06o <= REG[%02o]\n",
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adata, bdata, b);
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mem_write (adata, bdata);
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} else {
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bdata = R[b] = mem_read(adata);
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sim_debug (DBG_STATE, &cpu_dev, "REG[%02o] <= %06o <= MEM[%06o]\n",
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b, bdata, adata);
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}
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}
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if (alu_op != 0)
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alu_op |= 04000;
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}
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result = cpu_alu (insn, alu_op, adata, bdata);
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switch (insn & 030000) {
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case 030000:
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if (C) {
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case 000000:
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sim_debug (DBG_STATE, &cpu_dev, "REG[%02o] <= %06o\n", a, result);
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R[a] = result;
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}
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break;
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case 010000:
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break;
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case 020000:
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sim_debug (DBG_STATE, &cpu_dev, "REG[%02o] <= %06o\n", a, result);
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R[a] = result;
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if (insn & 01000) {
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IM = 0;
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if (insn & 04000) {
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sim_debug (DBG_STATE, &cpu_dev, "CWRITE[%04o]\n", RES);
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CRM[RES] = result;
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} else {
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sim_debug (DBG_STATE, &cpu_dev, "CREAD[%04o]\n", RES);
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R[a] = crm_read (RES);
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V = 0;
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C = 0;
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N = !!(R[a] & 0100000);
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Z = (R[a] == 0);
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sim_debug (DBG_STATE, &cpu_dev, "REG[%02o] <= %06o (%c%c%c%c)\n",
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a, R[a],
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C ? 'C' : '-',
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V ? 'V' : '-',
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N ? 'N' : '-',
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Z ? 'Z' : '-');
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}
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}
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break;
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}
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R[REG_ALATCH] = a;
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sim_debug (DBG_STATE, &cpu_dev, "A <= %o\n", R[REG_ALATCH]);
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RES = result;
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}
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static void cpu_jump (uint16 insn, int push)
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{
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if (push) {
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STACK[SP] = PC;
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sim_debug (DBG_STATE, &cpu_dev, "STACK[%02o] <= %04o\n", SP, PC);
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SP = (SP + 1) & 017;
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}
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PC = insn & 07777;
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}
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static void cpu_dis (uint16 insn)
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{
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uint16 data;
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uint16 mask;
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switch (insn & 01400) {
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case 00000:
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data = ((RES >> 15) & 1) | ((RES >> 13) & 2) |
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((RES >> 11) & 4) | ((RES >> 9) & 8);
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break;
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case 00400:
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data = FLAGS;
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break;
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case 01000:
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data = INTS;
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break;
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case 01400:
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data = STARS;
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break;
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default:
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return;
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}
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mask = (insn >> 4) & 017;
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PC = PC + (data & ~mask);
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}
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static void cpu_popj (void)
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{
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SP = (SP - 1) & 017;
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PC = STACK[SP];
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sim_debug (DBG_STATE, &cpu_dev, "PC <= %04o <= STACK[%02o]\n", PC, SP);
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}
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static void bus_write (uint16 reg, uint16 data)
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{
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switch (reg) {
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case 012: PC = data & 07777; break;
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case 014: dpy_magic (data, &R[2], &R[3], R[4], R[5]); break;
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case 015: dpy_chartv (data); break;
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case 016: cpu_popj (); break;
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case 023: new_XR = data; break;
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case 020: case 021: case 022: case 024: case 025: case 026: case 027:
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case 030: case 031: case 032: case 033: case 034: case 035: case 036: case 037:
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sim_debug (DBG_STATE, &cpu_dev, "BUS[%02o] <= %06o\n", reg, data);
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dev_tab[reg]->write (reg, data);
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break;
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default: /* 40-77 is scratchpad. */
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R[reg] = data;
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sim_debug (DBG_STATE, &cpu_dev, "REG[%02o] <= %06o\n", reg, data);
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break;
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}
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}
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static void cpu_bus (uint16 insn)
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{
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uint16 a = (insn >> 6) & 7;
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uint16 b = insn & 077;
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uint16 bb = insn & 01000;
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if ((insn & 0176000) == 0072000) {
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cpu_dis (insn);
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return;
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}
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if (bb) {
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switch (a) {
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case 2: PC = RES; return;
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case 4: dpy_magic (RES, &R[2], &R[3], R[4], R[5]); return;
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case 5: dpy_chartv (R[b]); return;
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case 6: cpu_popj (); return;
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default:
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sim_debug (DBG_CPU, &cpu_dev, "Unknown instruction: %06o\n", IR);
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break;
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}
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}
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if (insn & 02000) {
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bus_write (b, R[a]);
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} else {
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R[a] = bus_read (b);
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sim_debug (DBG_STATE, &cpu_dev, "REG[%02o] <= %06o\n", a, R[a]);
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}
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}
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static void cpu_branch (uint16 insn)
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{
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uint16 target = insn & 03777;
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int jump = 0;
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switch (insn & 070000) {
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case 000000: jump = !C; break;
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case 010000: jump = !V; break;
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case 020000: jump = N; break;
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case 030000: jump = !Z; break;
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case 040000: jump = N ^ V; break;
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case 050000: jump = INTS; break;
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case 060000: jump = !(R[REG_XR] & 04000); new_XR = R[REG_XR] + 1; break;
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case 070000: jump = FLAGS; break;
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}
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if (insn & 04000)
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jump = !jump;
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if (jump) {
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if (insn & 02000)
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target -= 04000;
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PC = (PC + target) & 07777;
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}
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}
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static void
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cpu_fetch (void)
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{
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/* Fetch cycle. */
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IR = crm_read (PC);
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sim_debug (DBG_FET, &cpu_dev, "%04o: %06o\n", PC, IR);
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sim_interval--;
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if (history) {
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history[history_i].PC = PC;
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history[history_i].IR = IR;
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}
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PC = (PC + 1) & 07777;
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}
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static void cpu_update (void)
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{
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new_XR &= 07777;
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if (R[REG_XR] != new_XR)
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sim_debug (DBG_STATE, &cpu_dev, "XR <= %04o\n", new_XR);
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R[REG_XR] = new_XR;
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R[011] = (new_XR >> 6) & 077;
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R[012] = new_XR & 077;
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R[015] = (new_XR >> 6) & 7;
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R[016] = new_XR & 7;
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}
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static void
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cpu_execute (void)
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{
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if (IM != 0) {
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sim_debug (DBG_EXE, &cpu_dev, "%06o\n", IM);
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cpu_reg_op (IM);
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return;
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}
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if (cpu_dev.dctrl & DBG_EXE) {
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t_value val = IR;
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sim_debug (DBG_EXE, &cpu_dev, "%06o (", IR);
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fprint_sym (sim_deb, PC-1, &val, NULL, SWMASK ('M'));
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sim_debug (DBG_EXE, &cpu_dev, ")\n");
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}
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switch ((IR >> 12) & 017) {
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case 000: case 001: case 002: case 003:
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cpu_reg_op (IR);
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break;
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case 004:
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cpu_jump (IR, 1);
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break;
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case 005:
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cpu_jump (IR, 0);
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break;
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case 007:
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cpu_bus (IR);
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break;
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case 010: case 011: case 012: case 013:
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case 014: case 015: case 016: case 017:
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cpu_branch (IR);
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break;
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default:
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sim_debug (DBG_CPU, &cpu_dev, "Unknown instruction: %06o\n", IR);
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break;
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}
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}
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static void
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cpu_insn (void)
|
|
{
|
|
cpu_update ();
|
|
cpu_execute ();
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|
cpu_fetch ();
|
|
|
|
if (history) {
|
|
history_i = (history_i + 1) % history_m;
|
|
if (history_n < history_m)
|
|
history_n++;
|
|
}
|
|
}
|
|
|
|
t_stat sim_instr (void)
|
|
{
|
|
t_stat reason;
|
|
|
|
if ((reason = build_dev_tab ()) != SCPE_OK)
|
|
return reason;
|
|
|
|
halt = 0;
|
|
|
|
for (;;) {
|
|
AIO_CHECK_EVENT;
|
|
if (sim_interval <= 0) {
|
|
if ((reason = sim_process_event()) != SCPE_OK)
|
|
return reason;
|
|
}
|
|
|
|
if (sim_brk_summ && sim_brk_test(PC, SWMASK('E')))
|
|
return STOP_IBKPT;
|
|
|
|
cpu_insn ();
|
|
|
|
if (sim_step != 0) {
|
|
if (--sim_step == 0)
|
|
return SCPE_STEP;
|
|
}
|
|
|
|
if (halt)
|
|
return STOP_HALT;
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat
|
|
cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
t_stat r;
|
|
uint32 x;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
|
|
x = get_uint (cptr, 10, 1000000, &r);
|
|
if (r != SCPE_OK)
|
|
return r;
|
|
|
|
history = (HISTORY *)calloc (x, sizeof (*history));
|
|
if (history == NULL)
|
|
return SCPE_MEM;
|
|
|
|
history_m = x;
|
|
history_n = 0;
|
|
history_i = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat
|
|
cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
t_value insn;
|
|
uint32 i, j;
|
|
|
|
fprintf (st, "PC____ IR____\n");
|
|
|
|
if (history_i >= history_n)
|
|
j = history_i - history_n;
|
|
else
|
|
j = history_m + history_i - history_n;
|
|
|
|
for (i = 0; i < history_n; i++) {
|
|
fprintf (st, "%06o %06o ",
|
|
history[j].PC,
|
|
history[j].IR);
|
|
insn = history[j].IR;
|
|
fprint_sym (st, history[j].PC, &insn, NULL, SWMASK ('M'));
|
|
fputc ('\n', st);
|
|
j = (j + 1) % history_m;
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat cpu_ex (t_value *vptr, t_addr ea, UNIT *uptr, int32 sw)
|
|
{
|
|
if (vptr == NULL)
|
|
return SCPE_ARG;
|
|
if (sw & SIM_SW_STOP)
|
|
sw |= SWMASK ('C');
|
|
if (sw & SWMASK ('C')) {
|
|
if (ea >= 4096)
|
|
return SCPE_NXM;
|
|
*vptr = crm_read (ea);
|
|
} else {
|
|
if (ea >= 65536)
|
|
return SCPE_NXM;
|
|
*vptr = mem_read (ea);
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat cpu_dep (t_value val, t_addr ea, UNIT *uptr, int32 sw)
|
|
{
|
|
if (sw & SWMASK ('C')) {
|
|
if (ea >= 4096)
|
|
return SCPE_NXM;
|
|
CRM[ea] = val & 0177777;
|
|
} else {
|
|
if (ea >= 65536)
|
|
return SCPE_NXM;
|
|
mem_write (ea, val & 0177777);
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs)
|
|
{
|
|
static t_addr returns[2] = { 0, 0 };
|
|
|
|
if ((CRM[PC] & 0170000) == 040000) {
|
|
returns[0] = PC + 1;
|
|
*ret_addrs = returns;
|
|
return TRUE;
|
|
}
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
static t_stat
|
|
cpu_reset (DEVICE *dptr)
|
|
{
|
|
ROM = 1;
|
|
PC = 0;
|
|
IR = 010000;
|
|
IM = 0;
|
|
SP = 0;
|
|
C = V = N = Z = 0;
|
|
new_XR = 0;
|
|
RES = FLAGS = INTS = STARS = 0;
|
|
|
|
sim_brk_types = SWMASK ('E');
|
|
sim_brk_dflt = SWMASK ('E');
|
|
sim_vm_is_subroutine_call = &cpu_is_pc_a_subroutine_call;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static const char *flag_name (uint16 flag)
|
|
{
|
|
switch (flag) {
|
|
case FLAG_KB: return "KB";
|
|
case FLAG_RSD: return "RSD";
|
|
case INT_2KHZ: return "2KHZ";
|
|
case INT_RRD: return "RRD";
|
|
case INT_60HZ: return "60HZ";
|
|
case STAR_WRAP: return "WRAP";
|
|
case STAR_MINUS1: return "MINUS1";
|
|
default: return "(unknown)";
|
|
}
|
|
}
|
|
|
|
void flag_on (uint16 flag)
|
|
{
|
|
sim_debug (DBG_INT, &cpu_dev, "Flag on %03o (%s)\n", flag, flag_name (flag));
|
|
FLAGS |= flag & 017;
|
|
flag >>= 4;
|
|
INTS |= flag & 017;
|
|
flag >>= 4;
|
|
STARS |= flag & 017;
|
|
}
|
|
|
|
void flag_off (uint16 flag)
|
|
{
|
|
sim_debug (DBG_INT, &cpu_dev, "Flag off %03o (%s)\n",
|
|
flag, flag_name (flag));
|
|
FLAGS &= ~(flag & 017);
|
|
flag >>= 4;
|
|
INTS &= ~(flag & 017);
|
|
flag >>= 4;
|
|
STARS &= ~(flag & 017);
|
|
}
|
|
|
|
#ifdef USE_DISPLAY
|
|
/* Called from display library to get data switches. */
|
|
void
|
|
cpu_get_switches (unsigned long *p1, unsigned long *p2)
|
|
{
|
|
}
|
|
|
|
/* Called from display library to set data switches. */
|
|
void
|
|
cpu_set_switches (unsigned long p1, unsigned long p2)
|
|
{
|
|
}
|
|
#endif
|