479 lines
14 KiB
C
479 lines
14 KiB
C
/* h316_stddev.c: Honeywell 316/516 standard devices
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Copyright (c) 1993-2001, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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ptr 316/516-50 paper tape reader
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ptp 316/516-52 paper tape punch
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tty 316/516-33 teleprinter
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clk/options 316/516-12 real time clocks/internal options
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07-Sep-01 RMS Moved function prototypes
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*/
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#include "h316_defs.h"
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#include <ctype.h>
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#define UNIT_V_UC (UNIT_V_UF + 1) /* UC only */
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#define UNIT_UC (1 << UNIT_V_UC)
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extern uint16 M[];
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extern int32 PC;
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extern int32 stop_inst;
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extern int32 C, dp, ext, extoff_pending, sc;
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extern int32 dev_ready, dev_enable;
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extern UNIT cpu_unit;
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int32 ptr_stopioe = 0, ptp_stopioe = 0; /* stop on error */
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int32 ptp_power = 0, ptp_ptime; /* punch power, time */
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int32 tty_mode = 0, tty_buf = 0; /* tty mode, buf */
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int32 clk_tps = 60; /* ticks per second */
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t_stat ptr_svc (UNIT *uptr);
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t_stat ptr_reset (DEVICE *dptr);
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t_stat ptr_boot (int32 unitno);
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t_stat ptp_svc (UNIT *uptr);
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t_stat ptp_reset (DEVICE *dptr);
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t_stat tti_svc (UNIT *uptr);
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t_stat tto_svc (UNIT *uptr);
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t_stat tty_reset (DEVICE *dptr);
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t_stat clk_svc (UNIT *uptr);
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t_stat clk_reset (DEVICE *dptr);
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/* PTR data structures
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ptr_dev PTR device descriptor
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ptr_unit PTR unit descriptor
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ptr_mod PTR modifiers
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ptr_reg PTR register list
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*/
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UNIT ptr_unit = {
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UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
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REG ptr_reg[] = {
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{ ORDATA (BUF, ptr_unit.buf, 8) },
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{ FLDATA (READY, dev_ready, INT_V_PTR) },
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{ FLDATA (ENABLE, dev_enable, INT_V_PTR) },
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{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
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{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
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{ NULL } };
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DEVICE ptr_dev = {
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"PTR", &ptr_unit, ptr_reg, NULL,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &ptr_reset,
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&ptr_boot, NULL, NULL };
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/* PTP data structures
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ptp_dev PTP device descriptor
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ptp_unit PTP unit descriptor
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ptp_mod PTP modifiers
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ptp_reg PTP register list
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*/
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UNIT ptp_unit = {
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UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
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REG ptp_reg[] = {
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{ ORDATA (BUF, ptp_unit.buf, 8) },
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{ FLDATA (READY, dev_ready, INT_V_PTP) },
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{ FLDATA (ENABLE, dev_enable, INT_V_PTP) },
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{ FLDATA (POWER, ptp_power, 0) },
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{ DRDATA (POS, ptp_unit.pos, 31), PV_LEFT },
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{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
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{ DRDATA (PWRTIME, ptp_ptime, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
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{ NULL } };
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DEVICE ptp_dev = {
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"PTP", &ptp_unit, ptp_reg, NULL,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &ptp_reset,
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NULL, NULL, NULL };
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/* TTY data structures
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tty_dev TTY device descriptor
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tty_unit TTY unit descriptor
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tty_reg TTY register list
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tty_mod TTy modifiers list
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*/
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#define TTI 0
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#define TTO 1
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UNIT tty_unit[] = {
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{ UDATA (&tti_svc, UNIT_UC, 0), KBD_POLL_WAIT },
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{ UDATA (&tto_svc, UNIT_UC, 0), SERIAL_OUT_WAIT } };
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REG tty_reg[] = {
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{ ORDATA (BUF, tty_buf, 8) },
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{ FLDATA (MODE, tty_mode, 0) },
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{ FLDATA (READY, dev_ready, INT_V_TTY) },
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{ FLDATA (ENABLE, dev_enable, INT_V_TTY) },
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{ DRDATA (KPOS, tty_unit[TTI].pos, 31), PV_LEFT },
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{ DRDATA (KTIME, tty_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPOS, tty_unit[TTO].pos, 31), PV_LEFT },
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{ DRDATA (TTIME, tty_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
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{ FLDATA (UC, tty_unit[TTI].flags, UNIT_V_UC), REG_HRO },
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{ NULL } };
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MTAB tty_mod[] = {
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{ UNIT_UC, 0, "lower case", "LC", NULL },
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{ UNIT_UC, UNIT_UC, "upper case", "UC", NULL },
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{ 0 } };
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DEVICE tty_dev = {
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"TTY", tty_unit, tty_reg, tty_mod,
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2, 10, 31, 1, 8, 8,
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NULL, NULL, &tty_reset,
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NULL, NULL, NULL };
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_mod CLK modifiers
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clk_reg CLK register list
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*/
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UNIT clk_unit = {
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UDATA (&clk_svc, 0, 0), 16000 };
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REG clk_reg[] = {
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{ FLDATA (READY, dev_ready, INT_V_CLK) },
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{ FLDATA (ENABLE, dev_enable, INT_V_CLK) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
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{ NULL } };
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL };
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/* Paper tape reader: IO routine */
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int32 ptrio (int32 inst, int32 fnc, int32 dat)
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{
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switch (inst) { /* case on opcode */
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case ioOCP: /* OCP */
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if (fnc & 016) return IOBADFNC (dat); /* only fnc 0,1 */
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if (fnc) sim_cancel (&ptr_unit); /* fnc 1? stop */
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else sim_activate (&ptr_unit, ptr_unit.wait); /* fnc 0? start */
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break;
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case ioSKS: /* SKS */
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if (fnc & 013) return IOBADFNC (dat); /* only fnc 0,4 */
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if (((fnc == 0) && TST_READY (INT_PTR)) || /* fnc 0? skip rdy */
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((fnc == 4) && !TST_INTREQ (INT_PTR))) /* fnc 4? skip !int */
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return IOSKIP (dat);
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break;
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case ioINA: /* INA */
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if (fnc & 007) return IOBADFNC (dat); /* only fnc 0,10 */
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if (TST_READY (INT_PTR)) { /* ready? */
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CLR_READY (INT_PTR); /* clear ready */
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return IOSKIP (ptr_unit.buf | dat); } /* ret buf, skip */
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break; } /* end case op */
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return dat;
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}
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/* Unit service */
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t_stat ptr_svc (UNIT *uptr)
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{
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int32 temp;
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if ((ptr_unit.flags & UNIT_ATT) == 0) /* attached? */
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return IORETURN (ptr_stopioe, SCPE_UNATT);
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if ((temp = getc (ptr_unit.fileref)) == EOF) { /* read byte */
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if (feof (ptr_unit.fileref)) {
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if (ptr_stopioe) printf ("PTR end of file\n");
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else return SCPE_OK; }
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else perror ("PTR I/O error");
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clearerr (ptr_unit.fileref);
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return SCPE_IOERR; }
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SET_READY (INT_PTR); /* set ready flag */
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ptr_unit.buf = temp & 0377; /* get byte */
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ptr_unit.pos = ftell (ptr_unit.fileref); /* update pos */
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sim_activate (&ptr_unit, ptr_unit.wait); /* reactivate */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat ptr_reset (DEVICE *dptr)
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{
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CLR_READY (INT_PTR); /* clear ready, enb */
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CLR_ENABLE (INT_PTR);
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ptr_unit.buf = 0; /* clear buffer */
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sim_cancel (&ptr_unit); /* deactivate unit */
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return SCPE_OK;
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}
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/* Paper tape reader bootstrap routine */
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#define PBOOT_START 1
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#define PBOOT_SIZE (sizeof (pboot) / sizeof (int32))
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static const int32 pboot[] = {
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0010057, /* STA 57 */
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0030001, /* OCP 1 */
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0131001, /* READ, INA 1001 */
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0002003, /* JMP READ */
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0101040, /* SNZ */
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0002003, /* JMP READ */
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0010000, /* STA 0 */
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0131001, /* READ1, INA 1001 */
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0002010, /* JMP READ1 */
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0041470, /* LGL 8 */
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0130001, /* READ2, INA 1 */
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0002013, /* JMP READ2 */
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0110000, /* STA* 0 */
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0024000, /* IRS 0 */
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0100040 /* SZE */
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};
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t_stat ptr_boot (int32 unit)
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{
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int32 i;
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for (i = 0; i < PBOOT_SIZE; i++) /* copy bootstrap */
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M[PBOOT_START + i] = pboot[i];
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PC = PBOOT_START;
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return SCPE_OK;
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}
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/* Paper tape punch: IO routine */
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int32 ptpio (int32 inst, int32 fnc, int32 dat)
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{
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switch (inst) { /* case on opcode */
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case ioOCP: /* OCP */
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if (fnc & 016) return IOBADFNC (dat); /* only fnc 0,1 */
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if (fnc) { /* fnc 1? pwr off */
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CLR_READY (INT_PTP); /* not ready */
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ptp_power = 0; /* turn off power */
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sim_cancel (&ptp_unit); } /* stop punch */
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else if (ptp_power == 0) /* fnc 0? start */
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sim_activate (&ptp_unit, ptp_ptime);
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break;
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case ioSKS: /* SKS */
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if ((fnc & 012) || (fnc == 005)) /* only 0, 1, 4 */
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return IOBADFNC (dat);
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if (((fnc == 00) && TST_READY (INT_PTP)) || /* fnc 0? skip rdy */
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((fnc == 01) /* fnc 1? skip ptp on */
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&& (ptp_power || sim_is_active (&ptp_unit))) ||
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((fnc == 04) && !TST_INTREQ (INT_PTP))) /* fnc 4? skip !int */
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return IOSKIP (dat);
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break;
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case ioOTA: /* OTA */
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if (fnc) return IOBADFNC (dat); /* only fnc 0 */
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if (TST_READY (INT_PTP)) { /* if ptp ready */
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CLR_READY (INT_PTP); /* clear ready */
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ptp_unit.buf = dat & 0377; /* store byte */
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sim_activate (&ptp_unit, ptp_unit.wait);
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return IOSKIP (dat); } /* skip return */
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break; }
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return dat;
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}
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/* Unit service */
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t_stat ptp_svc (UNIT *uptr)
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{
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SET_READY (INT_PTP); /* set flag */
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if (ptp_power == 0) { /* power on? */
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ptp_power = 1; /* ptp is ready */
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return SCPE_OK; }
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if ((ptp_unit.flags & UNIT_ATT) == 0) /* attached? */
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return IORETURN (ptp_stopioe, SCPE_UNATT);
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if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) { /* output byte */
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perror ("PTP I/O error");
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clearerr (ptp_unit.fileref);
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return SCPE_IOERR; }
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ptp_unit.pos = ftell (ptp_unit.fileref); /* update pos */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat ptp_reset (DEVICE *dptr)
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{
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CLR_READY (INT_PTP); /* clear ready, enb */
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CLR_ENABLE (INT_PTP);
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ptp_power = 0; /* power off */
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ptp_unit.buf = 0; /* clear buffer */
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sim_cancel (&ptp_unit); /* deactivate unit */
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return SCPE_OK;
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}
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/* Terminal: IO routine */
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int32 ttyio (int32 inst, int32 fnc, int32 dat)
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{
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switch (inst) { /* case on opcode */
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case ioOCP: /* OCP */
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if (fnc & 016) return IOBADFNC (dat); /* only fnc 0,1 */
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if (fnc && (tty_mode == 0)) { /* input to output? */
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if (!sim_is_active (&tty_unit[TTO])) SET_READY (INT_TTY);
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tty_mode = 1; } /* mode is output */
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else if ((fnc == 0) && tty_mode) { /* output to input? */
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CLR_READY (INT_TTY); /* clear ready */
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tty_mode = 0; } /* mode is input */
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break;
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case ioSKS: /* SKS */
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if (fnc & 012) return IOBADFNC (dat); /* fnc 0,1,4,5 */
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if (((fnc == 0) && TST_READY (INT_TTY)) || /* fnc 0? skip rdy */
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((fnc == 1) && /* fnc 1? skip !busy */
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tty_mode && !sim_is_active (&tty_unit[TTO])) ||
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((fnc == 4) && !TST_INTREQ (INT_TTY)) || /* fnc 4? skip !int */
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((fnc == 5) && /* fnc 5? skip !xoff */
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!tty_mode && ((tty_buf & 0177) == 023)))
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return IOSKIP (dat);
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break;
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case ioINA: /* INA */
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if (fnc & 005) return IOBADFNC (dat); /* only 0,2,10,12 */
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if (TST_READY (INT_TTY)) { /* ready? */
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if (tty_mode == 0) CLR_READY (INT_TTY); /* inp? clear rdy */
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return IOSKIP (dat |
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(tty_buf & ((fnc & 002)? 077: 0377))); }
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break;
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case ioOTA:
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if (fnc & 015) return IOBADFNC (dat); /* only 0,2 */
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if (TST_READY (INT_TTY)) { /* ready? */
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tty_buf = dat & 0377; /* store char */
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if (fnc & 002) { /* binary mode? */
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tty_buf = tty_buf | 0100; /* set ch 7 */
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if (tty_buf & 040) tty_buf = tty_buf & 0277; }
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if (tty_mode) {
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sim_activate (&tty_unit[TTO], tty_unit[TTO].wait);
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CLR_READY (INT_TTY); }
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return IOSKIP (dat); }
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break; } /* end case op */
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return dat;
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}
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/* Unit service routines */
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t_stat tti_svc (UNIT *uptr)
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{
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int32 temp;
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sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* continue poll */
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if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */
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temp = temp & 0177;
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if ((tty_unit[TTI].flags & UNIT_UC) && islower (temp)) /* force upper case? */
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temp = toupper (temp);
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if (tty_mode == 0) { /* input mode? */
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tty_buf = temp | 0200; /* put char in buf */
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tty_unit[TTI].pos = tty_unit[TTI].pos + 1;
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SET_READY (INT_TTY); /* set flag */
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sim_putchar (temp); } /* echo */
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return SCPE_OK;
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}
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t_stat tto_svc (UNIT *uptr)
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{
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int32 temp;
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SET_READY (INT_TTY); /* set done flag */
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if ((temp = sim_putchar (tty_buf & 0177)) != SCPE_OK) return temp;
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tty_unit[TTO].pos = tty_unit[TTO].pos + 1;
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat tty_reset (DEVICE *dptr)
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{
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CLR_READY (INT_TTY); /* clear ready, enb */
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CLR_ENABLE (INT_TTY);
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tty_mode = 0; /* mode = input */
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tty_buf = 0;
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sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* activate poll */
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sim_cancel (&tty_unit[TTO]); /* cancel output */
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return SCPE_OK;
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}
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/* Clock/options: IO routine */
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int32 clkio (int32 inst, int32 fnc, int32 dat)
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{
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switch (inst) { /* case on opcode */
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case ioOCP: /* OCP */
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if (fnc & 015) return IOBADFNC (dat); /* only fnc 0,2 */
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CLR_READY (INT_CLK); /* reset ready */
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if (fnc) sim_cancel (&clk_unit); /* fnc = 2? stop */
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else { if (!sim_is_active (&clk_unit)) /* fnc = 0? start */
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sim_activate (&clk_unit, /* activate */
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sim_rtc_init (clk_unit.wait)); } /* init calibr */
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break;
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case ioSKS: /* SKS */
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if (fnc == 0) { /* clock skip !int */
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if (!TST_INTREQ (INT_CLK)) return IOSKIP (dat); }
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else if ((fnc & 007) == 002) { /* mem parity? */
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if (((fnc == 002) && !TST_READY (INT_MPE)) ||
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((fnc == 012) && TST_READY (INT_MPE)))
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return IOSKIP (dat); }
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else return IOBADFNC (dat); /* invalid fnc */
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break;
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case ioOTA: /* OTA */
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if (fnc == 000) dev_enable = dat; /* SMK */
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else if (fnc == 010) { /* OTK */
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C = (dat >> 15) & 1; /* set C */
|
||
if (cpu_unit.flags & UNIT_HSA) /* HSA included? */
|
||
dp = (dat >> 14) & 1; /* set dp */
|
||
if (cpu_unit.flags & UNIT_EXT) { /* ext opt? */
|
||
if (dat & 020000) { /* ext set? */
|
||
ext = 1; /* yes, set */
|
||
extoff_pending = 0; }
|
||
else extoff_pending = 1; } /* no, clr later */
|
||
sc = dat & 037; } /* set sc */
|
||
else return IOBADFNC (dat);
|
||
break; }
|
||
return dat;
|
||
}
|
||
|
||
/* Unit service */
|
||
|
||
t_stat clk_svc (UNIT *uptr)
|
||
{
|
||
|
||
M[M_CLK] = M[M_CLK + 1] & DMASK; /* increment mem ctr */
|
||
if (M[M_CLK] == 0) SET_READY (INT_CLK); /* = 0? set flag */
|
||
sim_activate (&clk_unit, sim_rtc_calb (clk_tps)); /* reactivate */
|
||
return SCPE_OK;
|
||
}
|
||
|
||
/* Reset routine */
|
||
|
||
t_stat clk_reset (DEVICE *dptr)
|
||
{
|
||
CLR_READY (INT_CLK); /* clear ready, enb */
|
||
CLR_ENABLE (INT_CLK);
|
||
sim_cancel (&clk_unit); /* deactivate unit */
|
||
return SCPE_OK;
|
||
}
|