201 lines
8.6 KiB
C
201 lines
8.6 KiB
C
/*************************************************************************
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* *
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* $Id: s100_selchan.c 1995 2008-07-15 03:59:13Z hharte $ *
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* *
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* Copyright (c) 2007-2008 Howard M. Harte. *
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* http://www.hartetec.com *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
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* NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
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* *
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* Except as contained in this notice, the name of Howard M. Harte shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* Howard M. Harte. *
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* *
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* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
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* *
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* Module Description: *
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* CompuPro Selector Channel module for SIMH. *
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* *
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* Environment: *
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* User mode only *
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* *
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*************************************************************************/
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/*#define DBG_MSG */
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#include "altairz80_defs.h"
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#if defined (_WIN32)
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#include <windows.h>
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#endif
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#ifdef DBG_MSG
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#define DBG_PRINT(args) sim_printf args
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#else
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#define DBG_PRINT(args)
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#endif
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/* Debug flags */
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#define VERBOSE_MSG (1 << 0)
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#define DMA_MSG (1 << 1)
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#define SELCHAN_MAX_DRIVES 1
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typedef struct {
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PNP_INFO pnp; /* Plug and Play */
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uint32 selchan; /* Selector Channel Register */
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uint32 dma_addr; /* DMA Transfer Address */
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uint32 dma_mode; /* DMA Mode register */
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uint8 reg_cnt; /* Counter for selchan register */
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} SELCHAN_INFO;
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static SELCHAN_INFO selchan_info_data = { { 0x0, 0, 0xF0, 1 } };
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static SELCHAN_INFO *selchan_info = &selchan_info_data;
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int32 selchan_dma(uint8 *buf, uint32 len);
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extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
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extern uint32 PCX;
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/* These are needed for DMA. */
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extern void PutByteDMA(const uint32 Addr, const uint32 Value);
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extern uint8 GetByteDMA(const uint32 Addr);
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static t_stat selchan_reset(DEVICE *selchan_dev);
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static int32 selchandev(const int32 port, const int32 io, const int32 data);
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static UNIT selchan_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }
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};
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static REG selchan_reg[] = {
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{ HRDATAD (DMA_MODE, selchan_info_data.dma_mode, 8, "DMA mode register"), },
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{ HRDATAD (DMA_ADDR, selchan_info_data.dma_addr, 24, "DMA transfer address register"), },
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{ NULL }
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};
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static MTAB selchan_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL,
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"Sets disk controller I/O base address" },
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{ 0 }
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};
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/* Debug Flags */
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static DEBTAB selchan_dt[] = {
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{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
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{ "DMA", DMA_MSG, "DMA messages" },
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{ NULL, 0 }
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};
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DEVICE selchan_dev = {
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"SELCHAN", selchan_unit, selchan_reg, selchan_mod,
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SELCHAN_MAX_DRIVES, 10, 31, 1, SELCHAN_MAX_DRIVES, SELCHAN_MAX_DRIVES,
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NULL, NULL, &selchan_reset,
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NULL, NULL, NULL,
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&selchan_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), 0,
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selchan_dt, NULL, "Compupro Selector Channel SELCHAN"
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};
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/* Reset routine */
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static t_stat selchan_reset(DEVICE *dptr)
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{
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PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
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if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
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sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, TRUE);
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} else {
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/* Connect SELCHAN at base address */
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if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, FALSE) != 0) {
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sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
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return SCPE_ARG;
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}
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}
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return SCPE_OK;
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}
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#define SELCHAN_MODE_WRITE 0x80 /* Selector Channel Memory or I/O Write */
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#define SELCHAN_MODE_IO 0x40 /* Set if I/O Access, otherwise memory */
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#define SELCHAN_MODE_CNT_UP 0x20 /* Set = DMA Address Count Up, otherwise down. (Mem only */
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#define SELCHAN_MODE_WAIT 0x10 /* Insert one wait state. */
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#define SELCHAN_MODE_DMA_MASK 0x0F /* Mask for DMA Priority field */
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static int32 selchandev(const int32 port, const int32 io, const int32 data)
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{
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DBG_PRINT(("SELCHAN: IO %s, Port %02x" NLP, io ? "WR" : "RD", port));
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if(io) {
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selchan_info->selchan <<= 8;
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selchan_info->selchan &= 0xFFFFFF00;
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selchan_info->selchan |= data;
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selchan_info->dma_addr = (selchan_info->selchan & 0xFFFFF00) >> 8;
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selchan_info->dma_mode = (selchan_info->selchan & 0xFF);
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selchan_info->reg_cnt ++;
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if(selchan_info->reg_cnt == 4) {
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sim_debug(VERBOSE_MSG, &selchan_dev, "SELCHAN: " ADDRESS_FORMAT " DMA=0x%06x, Mode=0x%02x (%s, %s, %s)\n", PCX, selchan_info->dma_addr, selchan_info->dma_mode, selchan_info->dma_mode & SELCHAN_MODE_WRITE ? "WR" : "RD", selchan_info->dma_mode & SELCHAN_MODE_IO ? "I/O" : "MEM", selchan_info->dma_mode & SELCHAN_MODE_IO ? "FIX" : selchan_info->dma_mode & SELCHAN_MODE_CNT_UP ? "INC" : "DEC");
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}
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return 0;
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} else {
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sim_debug(VERBOSE_MSG, &selchan_dev, "SELCHAN: " ADDRESS_FORMAT " Reset\n", PCX);
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selchan_info->reg_cnt = 0;
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return(0xFF);
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}
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}
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int32 selchan_dma(uint8 *buf, uint32 len)
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{
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uint32 i;
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if(selchan_info->reg_cnt != 4) {
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sim_printf("SELCHAN: " ADDRESS_FORMAT " Programming error: selector channel disabled." NLP,
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PCX);
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return (-1);
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}
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if(selchan_info->dma_mode & SELCHAN_MODE_IO)
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{
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sim_printf("SELCHAN: " ADDRESS_FORMAT " I/O Not supported" NLP, PCX);
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return (-1);
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} else {
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sim_debug(DMA_MSG, &selchan_dev, "SELCHAN: " ADDRESS_FORMAT " DMA %s Transfer, len=%d\n", PCX, (selchan_info->dma_mode & SELCHAN_MODE_WRITE) ? "WR" : "RD", len);
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for(i=0;i<len;i++) {
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if(selchan_info->dma_mode & SELCHAN_MODE_WRITE) {
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PutByteDMA(selchan_info->dma_addr + i, buf[i]);
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} else {
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buf[i] = GetByteDMA(selchan_info->dma_addr + i);
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}
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}
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if(selchan_info->dma_mode & SELCHAN_MODE_CNT_UP) {
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selchan_info->dma_addr += i;
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} else {
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selchan_info->dma_addr -= i;
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}
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}
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return(0);
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}
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