671 lines
23 KiB
C
671 lines
23 KiB
C
/* vax730_uba.c: VAX 11/730 Unibus adapter
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Copyright (c) 2010-2011, Matt Burke
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This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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uba DW730 Unibus adapter
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29-Mar-2011 MB First Version
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*/
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#include "vax_defs.h"
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/* Unibus adapter */
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#define UBA_NMAPR 496 /* number of map reg */
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/* Unibus configuration register */
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#define UBACNF_OF 0x00
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#define UBACNF_CODE 0x00000028 /* adapter code */
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/* Data path registers */
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#define UBADPR_OF 0x01
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/* Control & Status register */
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#define UBACSR_OF 0x04
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#define UBACSR_WNV 0x00004000 /* write not valid */
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#define UBACSR_TBPAR 0x00008000 /* TB parity err */
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#define UBACSR_NXM 0x00010000 /* UB NXM */
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#define UBACSR_RDS 0x80000000 /* UB read data subs */
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/* Vector registers - read only */
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#define UBA_UVEC 0x80000000
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/* RB730 registers */
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#define RB730_OF 0x80
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#define RB730_LN 8
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/* Map registers */
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#define UBAMAP_OF 0x200
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#define UBAMAP_VLD 0x80000000 /* valid */
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#define UBAMAP_LWAE 0x04000000 /* LW access enb - ni */
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#define UBAMAP_ODD 0x02000000 /* odd byte */
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#define UBAMAP_V_DP 21 /* data path */
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#define UBAMAP_M_DP 0xF
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#define UBAMAP_DP (UBAMAP_M_DP << UBAMAP_V_DP)
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#define UBAMAP_GETDP(x) (((x) >> UBAMAP_V_DP) & UBAMAP_M_DP)
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#define UBAMAP_PAG 0x001FFFFF
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#define UBAMAP_RD (0x86000000 | UBAMAP_DP | UBAMAP_PAG)
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#define UBAMAP_WR (UBAMAP_RD)
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/* Debug switches */
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#define UBA_DEB_RRD 0x01 /* reg reads */
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#define UBA_DEB_RWR 0x02 /* reg writes */
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#define UBA_DEB_MRD 0x04 /* map reads */
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#define UBA_DEB_MWR 0x08 /* map writes */
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#define UBA_DEB_XFR 0x10 /* transfers */
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#define UBA_DEB_ERR 0x20 /* errors */
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int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */
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uint32 uba_csr = 0; /* control & status reg */
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uint32 uba_fmer = 0; /* failing map reg */
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uint32 uba_map[UBA_NMAPR] = { 0 }; /* map registers */
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int32 autcon_enb = 1; /* autoconfig enable */
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extern int32 trpirq;
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extern int32 autcon_enb;
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extern jmp_buf save_env;
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extern UNIT cpu_unit;
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extern int32 p1;
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t_stat uba_reset (DEVICE *dptr);
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const char *uba_description (DEVICE *dptr);
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t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
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t_stat uba_wrreg (int32 val, int32 pa, int32 lnt);
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int32 uba_get_ubvector (int32 lvl);
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t_bool uba_eval_int (int32 lvl);
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void uba_ubpdn (int32 time);
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t_bool uba_map_addr (uint32 ua, uint32 *ma);
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t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat uba_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc);
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extern int32 eval_int (void);
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extern t_stat build_dib_tab (void);
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extern t_stat rb_rd32 (int32 *data, int32 PA, int32 access);
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extern t_stat rb_wr32 (int32 data, int32 PA, int32 access);
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/* Unibus IO page dispatches */
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t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
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t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
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/* Unibus interrupt request to interrupt action map */
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int32 (*int_ack[IPL_HLVL][32])(void); /* int ack routines */
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/* Unibus interrupt request to vector map */
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int32 int_vec[IPL_HLVL][32]; /* int req to vector */
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/* Unibus adapter data structures
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uba_dev UBA device descriptor
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uba_unit UBA units
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uba_reg UBA register list
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*/
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DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };
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UNIT uba_unit = { UDATA (0, 0, 0) };
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REG uba_reg[] = {
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{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
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{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
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{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
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{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
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{ HRDATAD (CSR, uba_csr, 32, "control/status register") },
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{ BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
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{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
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{ NULL }
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};
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MTAB uba_mod[] = {
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{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
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NULL, &show_nexus, NULL, "Display nexus" },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
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NULL, &show_iospace, NULL, "Display I/O space address map" },
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{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
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&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
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{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
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&set_autocon, NULL, NULL, "Disable autoconfiguration" },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
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NULL, &uba_show_virt, NULL, "Display translation for Unibus address arg" },
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{ 0 }
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};
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DEBTAB uba_deb[] = {
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{ "REGREAD", UBA_DEB_RRD },
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{ "REGWRITE", UBA_DEB_RWR },
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{ "MAPREAD", UBA_DEB_MRD },
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{ "MAPWRITE", UBA_DEB_MWR },
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{ "XFER", UBA_DEB_XFR },
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{ "ERROR", UBA_DEB_ERR },
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{ NULL, 0 }
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};
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DEVICE uba_dev = {
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"UBA", &uba_unit, uba_reg, uba_mod,
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1, 16, UBADDRWIDTH, 2, 16, 16,
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&uba_ex, &uba_dep, &uba_reset,
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NULL, NULL, NULL,
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&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
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uba_deb, NULL, NULL, NULL, NULL, NULL,
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&uba_description
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};
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/* Read Unibus adapter register - aligned lw only */
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t_stat uba_rdreg (int32 *val, int32 pa, int32 lnt)
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{
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int32 idx, ofs;
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if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */
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sim_printf (">>UBA: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt);
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// **FIXME** - Set error bit?
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return SCPE_OK;
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}
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ofs = NEXUS_GETOFS (pa); /* get offset */
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if (ofs >= UBAMAP_OF) { /* map? */
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idx = ofs - UBAMAP_OF;
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if (idx >= UBA_NMAPR) return SCPE_NXM; /* valid? */
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*val = uba_map[idx] & UBAMAP_RD;
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if (DEBUG_PRI (uba_dev, UBA_DEB_MRD))
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fprintf (sim_deb, ">>UBA: map %d read, value = %X\n", idx, *val);
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return SCPE_OK;
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}
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if (ofs >= RB730_OF) { /* RB730? */
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idx = ofs - RB730_OF;
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if (idx >= RB730_LN) return SCPE_NXM; /* valid? */
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return rb_rd32 (val, pa, lnt);
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}
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switch (ofs) { /* case on offset */
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case UBACNF_OF: /* Config Reg */
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*val = UBACNF_CODE;
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break;
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case UBADPR_OF + 0: /* DP Regs */
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case UBADPR_OF + 1:
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case UBADPR_OF + 2:
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*val = 0x0; /* Not used on 11/730 */
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break;
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case UBACSR_OF: /* CSR */
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*val = uba_csr;
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break;
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default:
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return SCPE_NXM;
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}
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if (DEBUG_PRI (uba_dev, UBA_DEB_RRD))
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fprintf (sim_deb, ">>UBA: reg %d read, value = %X\n", ofs, *val);
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return SCPE_OK;
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}
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/* Write Unibus adapter register */
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t_stat uba_wrreg (int32 val, int32 pa, int32 lnt)
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{
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int32 idx, ofs;
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if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */
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sim_printf (">>UBA: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt);
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// **FIXME** - Set error bit?
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return SCPE_OK;
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}
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ofs = NEXUS_GETOFS (pa); /* get offset */
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if (ofs >= UBAMAP_OF) { /* map? */
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idx = ofs - UBAMAP_OF;
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if (idx >= UBA_NMAPR) return SCPE_NXM; /* valid? */
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uba_map[idx] = val & UBAMAP_WR;
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if (DEBUG_PRI (uba_dev, UBA_DEB_MWR))
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fprintf (sim_deb, ">>UBA: map %d write, value = %X\n", idx, val);
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return SCPE_OK;
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}
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if (ofs >= RB730_OF) { /* RB730? */
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idx = ofs - RB730_OF;
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if (idx >= RB730_LN) return SCPE_NXM; /* valid? */
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return rb_wr32 (val, pa, lnt);
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}
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switch (ofs) { /* case on offset */
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case UBACNF_OF: /* Config Reg */
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case UBADPR_OF + 0: /* DP Regs */
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case UBADPR_OF + 1:
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case UBADPR_OF + 2:
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break; /* ignore writes */
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case UBACSR_OF: /* CSR */
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if(val & 0x10000) uba_csr = 0;
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break;
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default:
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return SCPE_NXM;
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}
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if (DEBUG_PRI (uba_dev, UBA_DEB_RWR))
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fprintf (sim_deb, ">>UBA: reg %d write, value = %X\n", ofs, val);
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return SCPE_OK;
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}
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/* Read and write Unibus I/O space */
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int32 ReadUb (uint32 pa)
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{
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int32 idx, val;
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if (ADDR_IS_IOP (pa)) { /* iopage */
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idx = (pa & IOPAGEMASK) >> 1;
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if (iodispR[idx]) {
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iodispR[idx] (&val, pa, READ);
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return val;
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}
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}
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MACH_CHECK(MCHK_IIA);
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return 0;
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}
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void WriteUb (uint32 pa, int32 val, int32 mode)
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{
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int32 idx;
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if (ADDR_IS_IOP (pa)) { /* iopage */
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idx = (pa & IOPAGEMASK) >> 1;
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if (iodispW[idx]) {
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iodispW[idx] (val, pa, mode);
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return;
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}
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}
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MACH_CHECK(MCHK_IIA);
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return;
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}
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/* ReadIO - read from IO - UBA only responds to byte, aligned word
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Inputs:
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pa = physical address
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lnt = length (BWLQ)
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Output:
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longword of data
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*/
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int32 ReadIO (uint32 pa, int32 lnt)
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{
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uint32 iod;
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if ((lnt == L_BYTE) || /* byte? */
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((lnt == L_WORD) && ((pa & 1) == 0))) { /* aligned word? */
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iod = ReadUb (pa); /* DATI from Unibus */
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if (pa & 2) /* position */
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iod = iod << 16;
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}
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else {
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sim_printf (">>UBA: invalid read mask, pa = %x, lnt = %d\n", pa, lnt);
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// **FIXME** - Set error bit?
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iod = 0;
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}
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SET_IRQL;
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return iod;
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}
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/* WriteIO - write to IO - UBA only responds to byte, aligned word
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Inputs:
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pa = physical address
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val = data to write, right justified in 32b longword
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lnt = length (BWL)
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Outputs:
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none
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*/
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void WriteIO (uint32 pa, int32 val, int32 lnt)
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{
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if (lnt == L_BYTE) /* byte? DATOB */
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WriteUb (pa, val, WRITEB);
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else if ((lnt == L_WORD) && ((pa & 1) == 0)) /* aligned word? */
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WriteUb (pa, val, WRITE); /* DATO */
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else {
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sim_printf (">>UBA: invalid write mask, pa = %x, lnt = %d\n", pa, lnt);
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// **FIXME** - Set error bit?
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}
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SET_IRQL; /* update ints */
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return;
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}
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/* Update UBA nexus interrupts */
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t_bool uba_eval_int (int32 lvl)
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{
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return (int_req[lvl] != 0);
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}
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/* Return vector for Unibus interrupt at relative IPL level [0-3] */
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int32 uba_get_ubvector (int32 lvl)
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{
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int32 i, vec;
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vec = 0;
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for (i = 0; int_req[lvl] && (i < 32); i++) {
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if ((int_req[lvl] >> i) & 1) {
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int_req[lvl] = int_req[lvl] & ~(1u << i);
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if (int_ack[lvl][i])
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return (vec | int_ack[lvl][i]());
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return (vec | int_vec[lvl][i]);
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}
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}
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return vec;
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}
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/* Unibus I/O buffer routines
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Map_ReadB - fetch byte buffer from memory
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Map_ReadW - fetch word buffer from memory
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Map_WriteB - store byte buffer into memory
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Map_WriteW - store word buffer into memory
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*/
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf)
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{
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int32 i, j, pbc;
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uint32 ma, dat;
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ba = ba & UBADDRMASK; /* mask UB addr */
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for (i = 0; i < bc; i = i + pbc) { /* loop by pages */
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if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */
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return (bc - i);
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pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */
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if (pbc > (bc - i)) /* limit to rem xfr */
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pbc = bc - i;
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if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
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fprintf (sim_deb, ">>UBA: 8b read, ma = %X, bc = %X\n", ma, pbc);
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if ((ma | pbc) & 3) { /* aligned LW? */
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for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */
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*buf++ = ReadB (ma);
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}
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}
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else { /* yes, do by LW */
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for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
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dat = ReadL (ma); /* get lw */
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*buf++ = dat & BMASK; /* low 8b */
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*buf++ = (dat >> 8) & BMASK; /* next 8b */
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*buf++ = (dat >> 16) & BMASK; /* next 8b */
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*buf++ = (dat >> 24) & BMASK;
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}
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}
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}
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return 0;
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}
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf)
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{
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int32 i, j, pbc;
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uint32 ma, dat;
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ba = ba & UBADDRMASK; /* mask UB addr */
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bc = bc & ~01;
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for (i = 0; i < bc; i = i + pbc) { /* loop by pages */
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if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */
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return (bc - i);
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pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */
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if (pbc > (bc - i)) /* limit to rem xfr */
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pbc = bc - i;
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if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
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fprintf (sim_deb, ">>UBA: 16b read, ma = %X, bc = %X\n", ma, pbc);
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if ((ma | pbc) & 1) { /* aligned word? */
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for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */
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if ((i + j) & 1) { /* odd byte? */
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*buf = (*buf & BMASK) | (ReadB (ma) << 8);
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buf++;
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}
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else *buf = (*buf & ~BMASK) | ReadB (ma);
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}
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}
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else if ((ma | pbc) & 3) { /* aligned LW? */
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for (j = 0; j < pbc; ma = ma + 2, j = j + 2) { /* no, words */
|
|
*buf++ = ReadW (ma); /* get word */
|
|
}
|
|
}
|
|
else { /* yes, do by LW */
|
|
for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
|
|
dat = ReadL (ma); /* get lw */
|
|
*buf++ = dat & WMASK; /* low 16b */
|
|
*buf++ = (dat >> 16) & WMASK; /* high 16b */
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf)
|
|
{
|
|
int32 i, j, pbc;
|
|
uint32 ma, dat;
|
|
|
|
ba = ba & UBADDRMASK; /* mask UB addr */
|
|
for (i = 0; i < bc; i = i + pbc) { /* loop by pages */
|
|
if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */
|
|
return (bc - i);
|
|
pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */
|
|
if (pbc > (bc - i)) /* limit to rem xfr */
|
|
pbc = bc - i;
|
|
if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
|
|
fprintf (sim_deb, ">>UBA: 8b write, ma = %X, bc = %X\n", ma, pbc);
|
|
if ((ma | pbc) & 3) { /* aligned LW? */
|
|
for (j = 0; j < pbc; ma++, j++) { /* no, do by bytes */
|
|
WriteB (ma, *buf);
|
|
buf++;
|
|
}
|
|
}
|
|
else { /* yes, do by LW */
|
|
for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
|
|
dat = (uint32) *buf++; /* get low 8b */
|
|
dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */
|
|
dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */
|
|
dat = dat | (((uint32) *buf++) << 24); /* merge hi 8b */
|
|
WriteL (ma, dat); /* store lw */
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf)
|
|
{
|
|
int32 i, j, pbc;
|
|
uint32 ma, dat;
|
|
|
|
ba = ba & UBADDRMASK; /* mask UB addr */
|
|
bc = bc & ~01;
|
|
for (i = 0; i < bc; i = i + pbc) { /* loop by pages */
|
|
if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */
|
|
return (bc - i);
|
|
pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */
|
|
if (pbc > (bc - i)) /* limit to rem xfr */
|
|
pbc = bc - i;
|
|
if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
|
|
fprintf (sim_deb, ">>UBA: 16b write, ma = %X, bc = %X\n", ma, pbc);
|
|
if ((ma | pbc) & 1) { /* aligned word? */
|
|
for (j = 0; j < pbc; ma++, j++) { /* no, bytes */
|
|
if ((i + j) & 1) {
|
|
WriteB (ma, (*buf >> 8) & BMASK);
|
|
buf++;
|
|
}
|
|
else WriteB (ma, *buf & BMASK);
|
|
}
|
|
}
|
|
else if ((ma | pbc) & 3) { /* aligned LW? */
|
|
for (j = 0; j < pbc; ma = ma + 2, j = j + 2) { /* no, words */
|
|
WriteW (ma, *buf); /* write word */
|
|
buf++;
|
|
}
|
|
}
|
|
else { /* yes, do by LW */
|
|
for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
|
|
dat = (uint32) *buf++; /* get low 16b */
|
|
dat = dat | (((uint32) *buf++) << 16); /* merge hi 16b */
|
|
WriteL (ma, dat); /* store LW */
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Map an address via the translation map */
|
|
|
|
t_bool uba_map_addr (uint32 ua, uint32 *ma)
|
|
{
|
|
uint32 ublk, umap;
|
|
|
|
ublk = ua >> VA_V_VPN; /* Unibus blk */
|
|
if (ublk >= UBA_NMAPR) /* unimplemented? */
|
|
return FALSE;
|
|
umap = uba_map[ublk]; /* get map */
|
|
if (umap & UBAMAP_VLD) { /* valid? */
|
|
*ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua);
|
|
if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD)) /* buffered dp? */
|
|
*ma = *ma + 1; /* byte offset? */
|
|
return (ADDR_IS_MEM (*ma)); /* legit addr */
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
/* Map an address via the translation map - console version (no status changes) */
|
|
|
|
t_bool uba_map_addr_c (uint32 ua, uint32 *ma)
|
|
{
|
|
uint32 ublk, umap;
|
|
|
|
ublk = ua >> VA_V_VPN; /* Unibus blk */
|
|
if (ublk >= UBA_NMAPR) /* unimplemented? */
|
|
return FALSE;
|
|
umap = uba_map[ublk]; /* get map */
|
|
if (umap & UBAMAP_VLD) { /* valid? */
|
|
*ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua);
|
|
if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD)) /* buffered dp? */
|
|
*ma = *ma + 1; /* byte offset? */
|
|
return TRUE; /* legit addr */
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
/* Unibus power fail routines */
|
|
|
|
void uba_ubpdn (int32 time)
|
|
{
|
|
int32 i;
|
|
DEVICE *dptr;
|
|
|
|
for (i = 0; sim_devices[i] != NULL; i++) { /* reset Unibus */
|
|
dptr = sim_devices[i];
|
|
if (dptr->reset && (dptr->flags & DEV_UBUS))
|
|
dptr->reset (dptr);
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Reset Unibus adapter */
|
|
|
|
t_stat uba_reset (DEVICE *dptr)
|
|
{
|
|
int32 i;
|
|
|
|
for (i = 0; i < IPL_HLVL; i++) {
|
|
int_req[i] = 0;
|
|
}
|
|
for (i = 0; i < UBA_NMAPR; i++)
|
|
uba_map[i] = 0;
|
|
uba_csr = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory examine via map (word only) */
|
|
|
|
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
|
{
|
|
uint32 ua = (uint32) exta, pa;
|
|
|
|
if ((vptr == NULL) || (ua >= UBADDRSIZE))
|
|
return SCPE_ARG;
|
|
if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) {
|
|
*vptr = (uint32) ReadW (pa);
|
|
return SCPE_OK;
|
|
}
|
|
return SCPE_NXM;
|
|
}
|
|
|
|
/* Memory deposit via map (word only) */
|
|
|
|
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
|
|
{
|
|
uint32 ua = (uint32) exta, pa;
|
|
|
|
if (ua >= UBADDRSIZE)
|
|
return SCPE_ARG;
|
|
if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) {
|
|
WriteW (pa, (int32) val);
|
|
return SCPE_OK;
|
|
}
|
|
return SCPE_NXM;
|
|
}
|
|
|
|
/* Show UBA virtual address */
|
|
|
|
t_stat uba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
t_stat r;
|
|
char *cptr = (char *) desc;
|
|
uint32 ua, pa;
|
|
|
|
if (cptr) {
|
|
ua = (uint32) get_uint (cptr, 16, UBADDRSIZE - 1, &r);
|
|
if (r == SCPE_OK) {
|
|
if (uba_map_addr_c (ua, &pa))
|
|
fprintf (of, "Unibus %-X = physical %-X\n", ua, pa);
|
|
else fprintf (of, "Unibus %-X: invalid mapping\n", ua);
|
|
return SCPE_OK;
|
|
}
|
|
}
|
|
fprintf (of, "Invalid argument\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *uba_description (DEVICE *dptr)
|
|
{
|
|
return "Unibus adapter";
|
|
}
|