701f0fe028
1. New Features
1.1 Directory and documentation
- Only common files (SCP and libraries) are in the top level
directory. Individual simulator files are in their individual
directories.
- simh_doc.txt has been split up. simh_doc.txt now documents
only SCP. The individual simulators are documented in separate
text files in their own directories.
- mingw_build.bat is a batch file for the MINGW/gcc environment
that will build all the simulators, assuming the root directory
structure is at c:\sim.
- Makefile is a UNIX make file for the gcc environment that will
build all the simulators, assuming the root directory is at
c:\sim.
1.2 SCP
- DO <file name> executes the SCP commands in the specified file.
- Replicated registers in unit structures can now be declared as
arrays for examine, modify, save, and restore. Most replicated
unit registers (for example, mag tape position registers) have
been changed to arrays.
- The ADD/REMOVE commands have been replaced by SET unit ONLINE
and SET unit OFFLINE, respectively.
- Register names that are unique within an entire simulator do
not have to be prefaced with the device name.
- The ATTACH command can attach files read only, either under
user option (-r), or because the attached file is ready only.
- The SET/SHOW capabilities have been extended. New forms include:
SET <dev> param{=value}{ param ...}
SET <unit> param{=value}{ param ...}
SHOW <dev> {param param ...}
SHOW <unit> {param param ...}
- Multiple breakpoints have been implemented. Breakpoints are
set/cleared/displayed by:
BREAK addr_list{[count]}
NOBREAK addr_list
SHOW BREAK addr_list
1.3 PDP-11 simulator
- Unibus map implemented, with 22b RP controller (URH70) or 18b
RP controller (URH11) (in debug).
- All DMA peripherals rewritten to use map.
- Many peripherals modified for source sharing with VAX.
- RQDX3 implemented.
- Bugs fixed in RK11 and RL11 write check.
1.4 PDP-10 simulator
- ITS 1-proceed implemented.
- Bugs fixed in ITS PC sampling and LPMR
1.5 18b PDP simulator
- Interrupts split out to multiple levels to allow easier
expansion.
1.5 IBM System 3 Simulator
- Written by Charles (Dutch) Owen.
1.6 VAX Simulator (in debug)
- Simulates MicroVAX 3800 (KA655) with 16MB-64MB memory, RQDX3,
RLV12, TSV11, DZV11, LPV11, PCV11.
- CDROM capability has been added to the RQDX3, to allow testing
with VMS hobbyist images.
1.7 SDS 940 Simulator (not tested)
- Simulates SDS 940, 16K-64K memory, fixed and moving head
disk, magtape, line printer, console.
1.8 Altair Z80
- Revised from Charles (Dutch) Owen's original by Peter Schorn.
- MITS 8080 with full Z80 simulation.
- 4K and 8K BASIC packages, Prolog package.
1.9 Interdata
The I4 simulator has been withdrawn for major rework. Look for
a complete 16b/32b Interdata simulator sometime next year.
2. Release Notes
2.1 SCP
SCP now allows replicated registers in unit structures to be
modelled as arrays. All replicated register declarations have
been replaced by register array declarations. As a result,
save files from prior revisions will generate errors after
restoring main memory.
2.2 PDP-11
The Unibus map code is in debug. The map was implemented primarily
to allow source sharing with the VAX, which requires a DMA map.
DMA devices work correctly with the Unibus map disabled.
The RQDX3 simulator has run a complete RSTS/E SYSGEN, with multiple
drives, and booted the completed system from scratch.
2.3 VAX
The VAX simulator will run the boot code up to the >>> prompt. It
can successfully process a SHOW DEVICE command. It runs the HCORE
instruction diagnostic. It can boot the hobbyist CD through SYSBOOT
and through the date/time dialog and restore the hobbyist CD, using
standalone backup. On the boot of the restored disk, it gets to the
date/time dialog, and then crashes.
2.4 SDS 940
The SDS 940 is untested, awaiting real code.
2.5 GCC Optimization
At -O2 and above, GCC does not correctly compile the simulators which
use setjmp-longjmp (PDP-11, PDP-10, VAX). A working hypothesis is
that optimized state maintained in registers is being used in the
setjmp processing routine. On the PDP-11 and PDP-10, all of this
state has been either made global, or volatile, to encourage GCC to
keep the state up to date in memory. The VAX is still vulnerable.
3. Work list
3.1 SCP
- Better ENABLE/DISABLE.
3.2 PDP-11 RQDX3
Software mapped mode, RCT read simulation, VMS debug.
530 lines
18 KiB
C
530 lines
18 KiB
C
/* hp2100_sys.c: HP 2100 simulator interface
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Copyright (c) 1993-2001, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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17-Sep-01 RMS Removed multiconsole support
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27-May-01 RMS Added multiconsole support
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14-Mar-01 RMS Revised load/dump interface (again)
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30-Oct-00 RMS Added examine to file support
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15-Oct-00 RMS Added dynamic device number support
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27-Oct-98 RMS V2.4 load interface
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*/
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#include "hp2100_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern UNIT cpu_unit;
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extern DEVICE dma0_dev, dma1_dev;
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extern DEVICE ptr_dev, ptp_dev;
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extern DEVICE tty_dev, clk_dev, lpt_dev;
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extern DEVICE mtd_dev, mtc_dev;
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extern DEVICE dpd_dev, dpc_dev;
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extern REG cpu_reg[];
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extern uint16 M[];
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax maximum number of words for examine/deposit
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "HP 2100";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 3;
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DEVICE *sim_devices[] = { &cpu_dev,
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&dma0_dev, &dma1_dev,
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&ptr_dev, &ptp_dev,
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&tty_dev,
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&clk_dev, &lpt_dev,
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&mtd_dev, &mtc_dev,
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&dpd_dev, &dpc_dev,
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NULL };
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Unimplemented instruction",
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"Non-existent I/O device",
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"HALT instruction",
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"Breakpoint",
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"Indirect address loop" };
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/* Binary loader
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The binary loader consists of blocks preceded and trailed by zero frames.
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A block consists of 16b words (punched big endian), as follows:
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count'xxx
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origin
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word 0
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:
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word count-1
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checksum
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The checksum includes the origin but not the count.
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*/
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int32 fgetw (FILE *fileref)
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{
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int c1, c2;
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if ((c1 = fgetc (fileref)) == EOF) return -1;
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if ((c2 = fgetc (fileref)) == EOF) return -1;
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return ((c1 & 0377) << 8) | (c2 & 0377);
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}
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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int32 origin, csum, zerocnt, count, word, i;
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if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
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for (zerocnt = 1;; zerocnt = -10) { /* block loop */
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for (;; zerocnt++) { /* skip 0's */
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if ((count = fgetc (fileref)) == EOF) return SCPE_OK;
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else if (count) break;
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else if (zerocnt == 0) return SCPE_OK; }
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if (fgetc (fileref) == EOF) return SCPE_FMT;
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if ((origin = fgetw (fileref)) < 0) return SCPE_FMT;
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csum = origin; /* seed checksum */
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for (i = 0; i < count; i++) { /* get data words */
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if ((word = fgetw (fileref)) < 0) return SCPE_FMT;
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if (MEM_ADDR_OK (origin)) M[origin] = word;
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origin = origin + 1;
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csum = csum + word; }
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if ((word = fgetw (fileref)) < 0) return SCPE_FMT;
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if ((word ^ csum) & DMASK) return SCPE_CSUM; }
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return SCPE_OK;
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}
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/* Symbol tables */
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#define I_V_FL 16 /* flag start */
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#define I_M_FL 017 /* flag mask */
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#define I_V_NPN 0 /* no operand */
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#define I_V_NPNC 1 /* no operand + C */
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#define I_V_MRF 2 /* mem ref */
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#define I_V_ASH 3 /* alter/skip, shift */
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#define I_V_ESHF 4 /* extended shift */
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#define I_V_EMRF 5 /* extended mem ref */
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#define I_V_IOT1 6 /* I/O + HC */
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#define I_V_IOT2 7 /* I/O only */
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#define I_V_EG1Z 010 /* ext grp, 1 op + 0 */
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#define I_V_EG2 011 /* ext grp, 2 op */
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#define I_NPN (I_V_NPN << I_V_FL)
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#define I_NPNC (I_V_NPNC << I_V_FL)
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#define I_MRF (I_V_MRF << I_V_FL)
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#define I_ASH (I_V_ASH << I_V_FL)
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#define I_ESHF (I_V_ESHF << I_V_FL)
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#define I_EMRF (I_V_EMRF << I_V_FL)
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#define I_IOT1 (I_V_IOT1 << I_V_FL)
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#define I_IOT2 (I_V_IOT2 << I_V_FL)
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#define I_EG1Z (I_V_EG1Z << I_V_FL)
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#define I_EG2 (I_V_EG2 << I_V_FL)
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static const int32 masks[] = {
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0177777, 0176777, 0074000, 0170000,
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0177760, 0177777, 0176700, 0177700,
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0177777, 0177777 };
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static const char *opcode[] = {
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"NOP", "NOP", "AND", "JSB",
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"XOR", "JMP", "IOR", "ISZ",
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"ADA", "ADB" ,"CPA", "CPB",
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"LDA", "LDB", "STA", "STB",
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"ASL", "LSL", "RRL",
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"ASR", "LSR", "RRR",
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"MPY", "DIV", "DLD", "DST",
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"FAD", "FSB", "FMP", "FDV",
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"FIX", "FLT",
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"STO", "CLO", "SOC", "SOS",
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"HLT", "STF", "CLF",
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"SFC", "SFS", "MIA", "MIB",
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"LIA", "LIB", "OTA", "OTB",
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"STC", "CLC",
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"SAX", "SBX", "CAX", "CBX",
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"LAX", "LBX", "STX",
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"CXA", "CXB", "LDX",
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"ADX", "XAX", "XBX",
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"SAY", "SBY", "CAY", "CBY",
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"LAY", "LBY", "STY",
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"CYA", "CYB", "LDY",
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"ADY", "XAY", "XBY",
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"ISX", "DSX", "JLY", "LBT",
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"SBT", "MBT", "CBT", "SBT",
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"ISY", "DSY", "JPY", "SBS",
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"CBS", "TBS", "CMW", "MVW",
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NULL, /* decode only */
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NULL };
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static const int32 opc_val[] = {
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0000000+I_NPN, 0002000+I_NPN, 0010000+I_MRF, 0014000+I_MRF,
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0020000+I_MRF, 0024000+I_MRF, 0030000+I_MRF, 0034000+I_MRF,
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0040000+I_MRF, 0044000+I_MRF, 0050000+I_MRF, 0054000+I_MRF,
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0060000+I_MRF, 0064000+I_MRF, 0070000+I_MRF, 0074000+I_MRF,
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0100020+I_ESHF, 0100040+I_ESHF, 0100100+I_ESHF,
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0101020+I_ESHF, 0101040+I_ESHF, 0101100+I_ESHF,
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0100200+I_EMRF, 0100400+I_EMRF, 0104200+I_EMRF, 0104400+I_EMRF,
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0105000+I_EMRF, 0105020+I_EMRF, 0105040+I_EMRF, 0105060+I_EMRF,
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0105100+I_NPN, 0105120+I_NPN,
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0102101+I_NPN, 0103101+I_NPN, 0102201+I_NPNC, 0102301+I_NPNC,
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0102000+I_IOT1, 0102100+I_IOT2, 0103100+I_IOT2,
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0102200+I_IOT2, 0102300+I_IOT2, 0102400+I_IOT1, 0106400+I_IOT1,
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0102500+I_IOT1, 0106500+I_IOT1, 0102600+I_IOT1, 0106600+I_IOT1,
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0102700+I_IOT1, 0106700+I_IOT1,
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0101740+I_EMRF, 0105740+I_EMRF, 0101741+I_NPN, 0105741+I_NPN,
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0101742+I_EMRF, 0105742+I_EMRF, 0105743+I_EMRF,
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0101744+I_NPN, 0105744+I_NPN, 0105745+I_EMRF,
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0105746+I_EMRF, 0101747+I_NPN, 0105747+I_NPN,
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0101750+I_EMRF, 0105750+I_EMRF, 0101751+I_NPN, 0105751+I_NPN,
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0101752+I_EMRF, 0105752+I_EMRF, 0105753+I_EMRF,
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0101754+I_NPN, 0105754+I_NPN, 0105755+I_EMRF,
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0105756+I_EMRF, 0101757+I_NPN, 0105757+I_NPN,
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0105760+I_NPN, 0105761+I_NPN, 0105762+I_EMRF, 0105763+I_NPN,
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0105764+I_NPN, 0105765+I_EG1Z, 0105766+I_EG1Z, 0105767+I_NPN,
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0105770+I_NPN, 0105771+I_NPN, 0105772+I_EMRF, 0105773+I_EG2,
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0105774+I_EG2, 0105775+I_EG2, 0105776+I_EG1Z, 0105777+I_EG1Z,
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0000000+I_ASH, /* decode only */
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-1 };
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/* Decode tables for shift and alter/skip groups */
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static const char *stab[] = {
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"ALS", "ARS", "RAL", "RAR", "ALR", "ERA", "ELA", "ALF",
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"BLS", "BRS", "RBL", "RBR", "BLR", "ERB", "ELB", "BLF",
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"CLA", "CMA", "CCA", "CLB", "CMB", "CCB",
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"SEZ", "CLE", "CLE", "CME", "CCE",
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"SSA", "SSB", "SLA", "SLB",
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"ALS", "ARS", "RAL", "RAR", "ALR", "ERA", "ELA", "ALF",
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"BLS", "BRS", "RBL", "RBR", "BLR", "ERB", "ELB", "BLF",
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"INA", "INB", "SZA", "SZB", "RSS",
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NULL };
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static const int32 mtab[] = {
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0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700,
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0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700,
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0007400, 0007400, 0007400, 0007400, 0007400, 0007400,
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0002040, 0002040, 0002300, 0002300, 0002300,
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0006020, 0006020, 0004010, 0004010,
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0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027,
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0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027,
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0006004, 0006004, 0006002, 0006002, 0002001,
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0 };
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static const int32 vtab[] = {
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0001000, 0001100, 0001200, 0001300, 0001400, 0001500, 0001600, 0001700,
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0005000, 0005100, 0005200, 0005300, 0005400, 0005500, 0005600, 0005700,
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0002400, 0003000, 0003400, 0006400, 0007000, 0007400,
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0002040, 0000040, 0002100, 0002200, 0002300,
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0002020, 0006020, 0000010, 0004010,
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0000020, 0000021, 0000022, 0000023, 0000024, 0000025, 0000026, 0000027,
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0004020, 0004021, 0004022, 0004023, 0004024, 0004025, 0004026, 0004027,
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0002004, 0006004, 0002002, 0006002, 0002001,
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-1 };
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/* Symbolic decode
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Inputs:
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*of = output stream
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addr = current PC
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*val = pointer to data
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*uptr = pointer to unit
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sw = switches
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Outputs:
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return = status code
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*/
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#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw)
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{
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int32 cflag, cm, i, j, inst, disp;
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cflag = (uptr == NULL) || (uptr == &cpu_unit);
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inst = val[0];
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if (sw & SWMASK ('A')) { /* ASCII? */
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if (inst > 0377) return SCPE_ARG;
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK; }
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if (sw & SWMASK ('C')) { /* characters? */
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fprintf (of, FMTASC ((inst >> 8) & 0177));
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK; }
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if (!(sw & SWMASK ('M'))) return SCPE_ARG;
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/* Instruction decode */
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for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
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j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
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if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
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switch (j) { /* case on class */
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case I_V_NPN: /* no operands */
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fprintf (of, "%s", opcode[i]); /* opcode */
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break;
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case I_V_NPNC: /* no operands + C */
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fprintf (of, "%s", opcode[i]);
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if (inst & HC) fprintf (of, " C");
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break;
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case I_V_MRF: /* mem ref */
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disp = inst & DISP; /* displacement */
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fprintf (of, "%s ", opcode[i]); /* opcode */
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if (inst & CP) { /* current page? */
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if (cflag) fprintf (of, "%-o", (addr & PAGENO) | disp);
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else fprintf (of, "C %-o", disp); }
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else fprintf (of, "%-o", disp); /* page zero */
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if (inst & IA) fprintf (of, ",I");
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break;
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case I_V_ASH: /* shift, alter-skip */
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cm = FALSE;
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for (i = 0; mtab[i] != 0; i++) {
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if ((inst & mtab[i]) == vtab[i]) {
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if (cm) fprintf (of, ",");
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cm = TRUE;
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fprintf (of, "%s", stab[i]); } }
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if (!cm) return SCPE_ARG; /* nothing decoded? */
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break;
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case I_V_ESHF: /* extended shift */
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disp = inst & 017; /* shift count */
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if (disp == 0) disp = 16;
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fprintf (of, "%s %d", opcode[i], disp);
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break;
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case I_V_EMRF: /* extended mem ref */
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fprintf (of, "%s %-o", opcode[i], val[1] & AMASK);
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if (val[1] & IA) fprintf (of, ",I");
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return -1; /* extra word */
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case I_V_IOT1: /* IOT with H/C */
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fprintf (of, "%s %-o", opcode[i], inst & DEVMASK);
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if (inst & HC) fprintf (of, ",C");
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break;
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case I_V_IOT2: /* IOT */
|
||
fprintf (of, "%s %-o", opcode[i], inst & DEVMASK);
|
||
break;
|
||
case I_V_EG1Z: /* ext grp 1 op + 0 */
|
||
fprintf (of, "%s %-o", opcode[i], val[1] & AMASK);
|
||
if (val[1] & IA) fprintf (of, ",I");
|
||
return -2; /* extra words */
|
||
case I_V_EG2: /* ext grp 2 op */
|
||
fprintf (of, "%s %-o", opcode[i], val[1] & AMASK);
|
||
if (val[1] & IA) fprintf (of, ",I");
|
||
fprintf (of, " %-o", val[2] & AMASK);
|
||
if (val[2] & IA) fprintf (of, ",I");
|
||
return -2; } /* extra words */
|
||
return SCPE_OK; } /* end if */
|
||
} /* end for */
|
||
return SCPE_ARG;
|
||
}
|
||
|
||
/* Get address with indirection
|
||
|
||
Inputs:
|
||
*cptr = pointer to input string
|
||
Outputs:
|
||
val = address
|
||
-1 if error
|
||
*/
|
||
|
||
int32 get_addr (char *cptr)
|
||
{
|
||
int32 d;
|
||
t_stat r;
|
||
char gbuf[CBUFSIZE];
|
||
|
||
cptr = get_glyph (cptr, gbuf, ','); /* get next field */
|
||
d = get_uint (gbuf, 8, AMASK, &r); /* construe as addr */
|
||
if (r != SCPE_OK) return -1;
|
||
if (*cptr != 0) { /* more? */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* look for indirect */
|
||
if (strcmp (gbuf, "I")) return -1;
|
||
d = d | IA; }
|
||
return d;
|
||
}
|
||
|
||
/* Symbolic input
|
||
|
||
Inputs:
|
||
*iptr = pointer to input string
|
||
addr = current PC
|
||
*uptr = pointer to unit
|
||
*val = pointer to output values
|
||
sw = switches
|
||
Outputs:
|
||
status = error status
|
||
*/
|
||
|
||
t_stat parse_sym (char *iptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||
{
|
||
int32 cflag, d, i, j, k, clef, tbits;
|
||
t_stat r, ret;
|
||
char *cptr, gbuf[CBUFSIZE];
|
||
|
||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||
while (isspace (*iptr)) iptr++; /* absorb spaces */
|
||
if ((sw & SWMASK ('A')) || ((*iptr == '\'') && iptr++)) { /* ASCII char? */
|
||
if (iptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (t_value) iptr[0] & 0177;
|
||
return SCPE_OK; }
|
||
if ((sw & SWMASK ('C')) || ((*iptr == '"') && iptr++)) { /* char string? */
|
||
if (iptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (((t_value) iptr[0] & 0177) << 8) |
|
||
((t_value) iptr[1] & 0177);
|
||
return SCPE_OK; }
|
||
|
||
/* Instruction parse */
|
||
|
||
ret = SCPE_OK;
|
||
cptr = get_glyph (iptr, gbuf, 0); /* get opcode */
|
||
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||
if (opcode[i]) { /* found opcode? */
|
||
val[0] = opc_val[i] & DMASK; /* get value */
|
||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||
|
||
switch (j) { /* case on class */
|
||
case I_V_NPN: /* no operand */
|
||
break;
|
||
case I_V_NPNC: /* no operand + C */
|
||
if (*cptr != 0) {
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
if (strcmp (gbuf, "C")) return SCPE_ARG;
|
||
val[0] = val[0] | HC; }
|
||
break;
|
||
case I_V_MRF: /* mem ref */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if (k = (strcmp (gbuf, "C") == 0)) { /* C specified? */
|
||
val[0] = val[0] | CP;
|
||
cptr = get_glyph (cptr, gbuf, 0); }
|
||
else if (k = (strcmp (gbuf, "Z") == 0)) { /* Z specified? */
|
||
cptr = get_glyph (cptr, gbuf, ','); }
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
if ((d & AMASK) <= DISP) val[0] = val[0] | d;
|
||
else if (cflag && !k && (((addr ^ d) & PAGENO) == 0))
|
||
val[0] = val[0] | (d & (IA | DISP)) | CP;
|
||
else return SCPE_ARG;
|
||
break;
|
||
case I_V_ESHF: /* extended shift */
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
d = get_uint (gbuf, 10, 16, &r);
|
||
if ((r != SCPE_OK) || (d == 0)) return SCPE_ARG;
|
||
val[0] = val[0] | (d & 017);
|
||
break;
|
||
case I_V_EMRF: /* extended mem ref */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
val[1] = d;
|
||
ret = -1;
|
||
break;
|
||
case I_V_IOT1: /* IOT + optional C */
|
||
cptr = get_glyph (cptr, gbuf, ','); /* get device */
|
||
d = get_uint (gbuf, 8, DEVMASK, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
val[0] = val[0] | d;
|
||
if (*cptr != 0) {
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
if (strcmp (gbuf, "C")) return SCPE_ARG;
|
||
val[0] = val[0] | HC; }
|
||
break;
|
||
case I_V_IOT2: /* IOT */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get device */
|
||
d = get_uint (gbuf, 8, DEVMASK, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
val[0] = val[0] | d;
|
||
break;
|
||
case I_V_EG1Z: /* ext grp 1 op + 0 */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
val[1] = d;
|
||
val[2] = 0;
|
||
ret = -2;
|
||
break;
|
||
case I_V_EG2: /* ext grp 2 op */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((k = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
val[1] = d;
|
||
val[2] = k;
|
||
ret = -2;
|
||
break; } /* end case */
|
||
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
|
||
return ret;
|
||
} /* end if opcode */
|
||
|
||
/* Shift or alter-skip
|
||
|
||
Each opcode is matched by a mask, specifiying the bits affected, and
|
||
the value, specifying the value. As opcodes are processed, the mask
|
||
values are used to specify which fields have already been filled in.
|
||
|
||
The mask has two subfields, the type bits (A/B and A/S), and the field
|
||
bits. The type bits, once specified by any instruction, must be
|
||
consistent in all other instructions. The mask bits assure that no
|
||
field is filled in twice.
|
||
|
||
Two special cases:
|
||
|
||
1. The dual shift field in shift requires checking how much of the
|
||
target word has been filled in before assigning the shift value.
|
||
To implement this, shifts are listed twice is the decode table.
|
||
If the current subopcode is a shift in the first part of the table
|
||
(entries 0..15), and CLE has been seen or the first shift field is
|
||
filled in, the code forces a mismatch. The glyph will match in
|
||
the second part of the table.
|
||
|
||
2. CLE processing must be deferred until the instruction can be
|
||
classified as shift or alter-skip, since it has two different
|
||
bit values in the two classes. To implement this, CLE seen is
|
||
recorded as a flag and processed after all other subopcodes.
|
||
*/
|
||
|
||
clef = FALSE;
|
||
tbits = 0;
|
||
val[0] = 0;
|
||
for (cptr = get_glyph (iptr, gbuf, ','); gbuf[0] != 0;
|
||
cptr = get_glyph (cptr, gbuf, ',')) { /* loop thru glyphs */
|
||
if (strcmp (gbuf, "CLE") == 0) { /* CLE? */
|
||
if (clef) return SCPE_ARG; /* already seen? */
|
||
clef = TRUE; /* set flag */
|
||
continue; }
|
||
for (i = 0; stab[i] != NULL; i++) { /* find subopcode */
|
||
if ((strcmp (gbuf, stab[i]) == 0) &&
|
||
((i >= 16) || (!clef && ((val[0] & 001710) == 0)))) break; }
|
||
if (stab[i] == NULL) return SCPE_ARG;
|
||
if (tbits & mtab[i] & (AB | ASKP) & (vtab[i] ^ val[0])) return SCPE_ARG;
|
||
if (tbits & mtab[i] & ~(AB | ASKP)) return SCPE_ARG;
|
||
tbits = tbits | mtab[i]; /* fill type+mask */
|
||
val[0] = val[0] | vtab[i]; } /* fill value */
|
||
if (clef) { /* CLE seen? */
|
||
if (val[0] & ASKP) { /* alter-skip? */
|
||
if (val[0] & 0300) return SCPE_ARG; /* already filled in? */
|
||
else val[0] = val[0] | 0100; }
|
||
else val[0] = val[0] | 040; } /* fill in shift */
|
||
return ret;
|
||
}
|