da6dcef801
When the 3B2 simulator was set to allow idling, there was significant clock drift related to the primary timer unit. It turns out that the simulator was using `AIO_SET_INTERRUPT_LATENCY` and `sim_rtcn_tick_ack` incorrectly. They are not needed with the structure of system timers in the 3B2 architecture.
814 lines
22 KiB
C
814 lines
22 KiB
C
/* 3b2_stddev.c: Miscellaneous System Board Devices
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Copyright (c) 2017-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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/*
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This file contains system-specific registers and devices for the
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following 3B2 devices:
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- nvram Non-Volatile RAM
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- tod MM58174A and MM58274C Real-Time-Clock
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- flt Fault Register (Rev 3 only)
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*/
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#include "3b2_stddev.h"
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#include "3b2_cpu.h"
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#include "3b2_csr.h"
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#include "3b2_timer.h"
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DEBTAB sys_deb_tab[] = {
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{ "INIT", INIT_MSG, "Init" },
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{ "READ", READ_MSG, "Read activity" },
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{ "WRITE", WRITE_MSG, "Write activity" },
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{ "EXECUTE", EXECUTE_MSG, "Execute activity" },
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{ "IRQ", IRQ_MSG, "Interrupt activity"},
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{ "TRACE", TRACE_DBG, "Detailed activity" },
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{ NULL, 0 }
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};
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uint32 *NVRAM = NULL;
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/* NVRAM */
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UNIT nvram_unit = {
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UDATA(NULL, UNIT_FIX+UNIT_BINK, NVRSIZE)
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};
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REG nvram_reg[] = {
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{ NULL }
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};
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DEVICE nvram_dev = {
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"NVRAM", &nvram_unit, nvram_reg, NULL,
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1, 16, 8, 4, 16, 32,
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&nvram_ex, &nvram_dep, &nvram_reset,
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NULL, &nvram_attach, &nvram_detach,
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NULL, DEV_DEBUG, 0, sys_deb_tab, NULL, NULL,
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&nvram_help, NULL, NULL,
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&nvram_description
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};
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t_stat nvram_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if ((vptr == NULL) || (addr & 03)) {
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return SCPE_ARG;
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}
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if (addr >= NVRSIZE) {
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return SCPE_NXM;
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}
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*vptr = NVRAM[addr >> 2];
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return SCPE_OK;
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}
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t_stat nvram_dep(t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if (addr & 03) {
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return SCPE_ARG;
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}
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if (addr >= NVRSIZE) {
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return SCPE_NXM;
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}
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NVRAM[addr >> 2] = (uint32) val;
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return SCPE_OK;
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}
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t_stat nvram_reset(DEVICE *dptr)
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{
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if (NVRAM == NULL) {
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NVRAM = (uint32 *)calloc(NVRSIZE >> 2, sizeof(uint32));
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memset(NVRAM, 0, sizeof(uint32) * NVRSIZE >> 2);
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nvram_unit.filebuf = NVRAM;
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}
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if (NVRAM == NULL) {
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return SCPE_MEM;
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}
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return SCPE_OK;
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}
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const char *nvram_description(DEVICE *dptr)
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{
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return "Non-Volatile RAM.\n";
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}
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t_stat nvram_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf(st, "Non-Volatile RAM\n\n");
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fprintf(st, "The %s device is a small battery-backed, non-volatile RAM\n", dptr->name);
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fprintf(st, "used by the 3B2 to hold system configuration and diagnostic data.\n\n");
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fprintf(st, "In order for the simulator to keep track of this data while not\n");
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fprintf(st, "running, the %s device may be attached to a file, e.g.\n\n", dptr->name);
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fprintf(st, " sim> ATTACH NVRAM <filename>\n");
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fprint_show_help(st, dptr);
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fprint_reg_help(st, dptr);
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return SCPE_OK;
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}
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t_stat nvram_attach(UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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/* If we've been asked to attach, make sure the ATTABLE
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and BUFABLE flags are set on the unit */
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uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE);
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r = attach_unit(uptr, cptr);
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if (r != SCPE_OK) {
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/* Unset the ATTABLE and BUFABLE flags if we failed. */
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uptr->flags = uptr->flags & (uint32) ~(UNIT_ATTABLE | UNIT_BUFABLE);
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} else {
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uptr->hwmark = (uint32) uptr->capac;
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}
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return r;
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}
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t_stat nvram_detach(UNIT *uptr)
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{
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t_stat r;
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r = detach_unit(uptr);
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if ((uptr->flags & UNIT_ATT) == 0) {
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uptr->flags = uptr->flags & (uint32) ~(UNIT_ATTABLE | UNIT_BUFABLE);
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}
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return r;
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}
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uint32 nvram_read(uint32 pa, size_t size)
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{
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uint32 offset = pa - NVRBASE;
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uint32 data = 0;
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uint32 sc = (~(offset & 3) << 3) & 0x1f;
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switch(size) {
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case 8:
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data = (NVRAM[offset >> 2] >> sc) & BYTE_MASK;
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break;
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case 16:
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if (offset & 2) {
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data = NVRAM[offset >> 2] & HALF_MASK;
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} else {
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data = (NVRAM[offset >> 2] >> 16) & HALF_MASK;
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}
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break;
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case 32:
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data = NVRAM[offset >> 2];
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break;
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}
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return data;
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}
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void nvram_write(uint32 pa, uint32 val, size_t size)
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{
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uint32 offset = pa - NVRBASE;
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uint32 index = offset >> 2;
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uint32 sc, mask;
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switch(size) {
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case 8:
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sc = (~(pa & 3) << 3) & 0x1f;
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mask = (uint32) (0xff << sc);
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NVRAM[index] = (NVRAM[index] & ~mask) | (val << sc);
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break;
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case 16:
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if (offset & 2) {
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NVRAM[index] = (NVRAM[index] & ~HALF_MASK) | val;
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} else {
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NVRAM[index] = (NVRAM[index] & HALF_MASK) | (val << 16);
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}
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break;
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case 32:
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NVRAM[index] = val;
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break;
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}
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}
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/*
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* MM58174A and MM58274C Time Of Day Clock.
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*
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* In addition to keeping track of time of day in tenths of seconds,
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* this device is also used as the simulator's primary calibrated
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* real-time clock. It operates at the speed of 100Hz, with every
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* tenth step incrementing the time-of-day counter.
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*/
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#define TOD_12H(TD) (((TD)->clkset & 1) == 0)
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#define TOD_BCDH(V) (((V) / 10) & 0xf)
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#define TOD_BCDL(V) (((V) % 10) & 0xf)
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#define TOD_LYEAR(TD) ((TD)->lyear == 0)
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#define TOD_LYEAR_INC(TD) \
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do { \
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(TD)->lyear = (((TD)->lyear + 1) & 0x3); \
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(TD)->clkset &= 3; \
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(TD)->clkset |= (TD)->lyear << 2; \
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} while(0)
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#define CTRL_DISABLE 0x4
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#define CLKSET_PM 0x2
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#define FLAG_DATA_CHANGED 0x4
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#define FLAG_INTERRUPT 0x1
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#define MIN_DIFF 5l
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#define MAX_DIFF 157680000l
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#define CLK_DELAY 10000 /* 10 milliseconds per tick */
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#define CLK_TPS 100l /* 100 ticks per second */
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static void tod_resync(UNIT *uptr);
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static void tod_tick(UNIT *uptr);
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static t_stat tod_svc(UNIT *uptr);
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static t_bool tod_enabled;
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int32 tmr_poll = CLK_DELAY;
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int32 tmxr_poll = CLK_DELAY;
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UNIT tod_unit = {
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UDATA(&tod_svc, UNIT_FIX|UNIT_BINK|UNIT_IDLE, sizeof(TOD_DATA)), CLK_DELAY
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};
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REG tod_reg[] = {
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{ DRDATAD(POLL, tmr_poll, 24, "Calibrated poll interval") },
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{ 0 }
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};
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DEVICE tod_dev = {
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"TOD", &tod_unit, tod_reg, NULL,
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1, 16, 8, 4, 16, 32,
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NULL, NULL, &tod_reset,
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NULL, &tod_attach, &tod_detach,
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NULL, DEV_DEBUG, 0, sys_deb_tab, NULL, NULL,
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&tod_help, NULL, NULL,
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&tod_description
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};
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/*
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* Attempt to re-sync the TOD by catching up (if lagging) and updating
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* the current time stored in the TOD state.
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*
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* Because this process may be expensive when catching up following a
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* very long time without the simulator running, the process will
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* short-circuit if the delta is longer than 5 years, or if no
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* previous time was recorded.
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*/
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static void tod_resync(UNIT *uptr)
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{
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TOD_DATA *td;
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time_t delta;
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uint32 catchup_ticks;
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if (!(uptr->flags & UNIT_ATT) || uptr->filebuf == NULL) {
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return;
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}
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td = (TOD_DATA *)uptr->filebuf;
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if (td->time > 0) {
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delta = time(NULL) - td->time;
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if (delta > MIN_DIFF && delta < MAX_DIFF) {
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catchup_ticks = (uint32) delta * CLK_TPS;
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sim_debug(EXECUTE_MSG, &tod_dev,
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"Catching up with a delta of %ld seconds (%d ticks).\n",
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delta, catchup_ticks);
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while (catchup_ticks-- > 0) {
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tod_tick(&tod_unit);
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}
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}
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}
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td->time = time(NULL);
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}
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t_stat tod_reset(DEVICE *dptr)
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{
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int32 t;
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if (tod_unit.filebuf == NULL) {
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tod_unit.filebuf = calloc(sizeof(TOD_DATA), 1);
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if (tod_unit.filebuf == NULL) {
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return SCPE_MEM;
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}
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}
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/* We start in a running state */
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tod_enabled = TRUE;
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t = sim_rtcn_init_unit(&tod_unit, tod_unit.wait, TMR_CLK);
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sim_activate_after(&tod_unit, 1000000/CLK_TPS);
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tmr_poll = t;
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tmxr_poll = t;
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return SCPE_OK;
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}
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t_stat tod_attach(UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE);
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r = attach_unit(uptr, cptr);
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if (r != SCPE_OK) {
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uptr->flags = uptr->flags & (uint32) ~(UNIT_ATTABLE | UNIT_BUFABLE);
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} else {
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uptr->hwmark = (uint32) uptr->capac;
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}
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return r;
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}
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t_stat tod_detach(UNIT *uptr)
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{
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t_stat r;
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r = detach_unit(uptr);
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if ((uptr->flags & UNIT_ATT) == 0) {
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uptr->flags = uptr->flags & (uint32) ~(UNIT_ATTABLE | UNIT_BUFABLE);
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}
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return r;
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}
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static t_stat tod_svc(UNIT *uptr)
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{
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TOD_DATA *td = (TOD_DATA *)uptr->filebuf;
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int32 t;
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/* Re-sync the recorded system time once every second */
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if (tod_enabled) {
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tod_tick(uptr);
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if (td->tsec == 0) {
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tod_resync(uptr);
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}
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}
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t = sim_rtcn_calb(CLK_TPS, TMR_CLK);
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sim_activate_after(uptr, 1000000/CLK_TPS);
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tmr_poll = t;
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tmxr_poll = t;
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return SCPE_OK;
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}
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/*
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* The MM58174 and MM58274 consist of a set of failry "dumb" roll-over
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* counters. In an ideal world, we'd just look at the real system time
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* and translate that into whatever read the host needs.
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* Unfortunately, since the Day-of-Week and Leap Year registers are
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* totally independent of whatever the "real" date and time should be,
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* this doesn't map very well, and DGMON hardware diagnostics fail.
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*
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* Instead, we model the behavior of the chip accurately here. Each
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* rollover is cascaded to the next highest register, using the same
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* logic the chip uses.
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*/
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static void tod_tick(UNIT *uptr)
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{
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TOD_DATA *td = (TOD_DATA *)uptr->filebuf;
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if (++td->tsec > 99) {
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td->tsec = 0;
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td->flags |= FLAG_DATA_CHANGED;
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if (++td->sec > 59) {
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td->sec = 0;
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if (++td->min > 59) {
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td->min = 0;
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td->hour++;
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/* 12-hour clock cycles from 1-12, 24-hour clock cycles from 00-23 */
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if (TOD_12H(td)) {
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if (td->hour == 12) {
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td->clkset ^= CLKSET_PM;
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}
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if (td->hour > 12) {
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td->hour = 1;
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}
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} else if (td->hour > 23) {
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td->hour = 0;
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}
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if ((TOD_12H(td) && td->hour == 12) || (!TOD_12H(td) && td->hour == 0)) {
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/* Manage day-of-week */
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td->wday++;
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if (td->wday > 7) {
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td->wday = 1;
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}
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td->day++;
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switch(td->mon) {
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case 2: /* FEB */
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if (TOD_LYEAR(td)) {
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if (td->day > 29) {
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td->day = 1;
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}
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} else {
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if (td->day > 28) {
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td->day = 1;
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}
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}
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break;
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case 4: /* APR */
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case 6: /* JUN */
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case 9: /* SEP */
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case 11: /* NOV */
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if (td->day > 30) {
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td->day = 1;
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}
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break;
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case 1: /* JAN */
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case 3: /* MAR */
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case 5: /* MAY */
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case 7: /* JUL */
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case 8: /* AUG */
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case 10: /* OCT */
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case 12: /* DEC */
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if (td->day > 31) {
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td->day = 1;
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}
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break;
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}
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if (td->day == 1) {
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if (++td->mon > 12) {
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td->mon = 1;
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TOD_LYEAR_INC(td);
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if (++td->year > 99) {
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td->year = 0;
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}
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}
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}
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}
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}
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}
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}
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}
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uint32 tod_read(uint32 pa, size_t size)
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{
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uint8 reg, val;
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TOD_DATA *td = (TOD_DATA *)(tod_unit.filebuf);
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reg = pa & 0xfc;
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switch(reg) {
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#if defined(REV3)
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case TOD_CTRL:
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val = td->flags;
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td->flags &= ~(FLAG_DATA_CHANGED);
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break;
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#endif
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case TOD_TSEC:
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val = TOD_BCDH(td->tsec);
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break;
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case TOD_1SEC:
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val = TOD_BCDL(td->sec);
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break;
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case TOD_10SEC:
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val = TOD_BCDH(td->sec);
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break;
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case TOD_1MIN:
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val = TOD_BCDL(td->min);
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break;
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case TOD_10MIN:
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val = TOD_BCDH(td->min);
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break;
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case TOD_1HOUR:
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val = TOD_BCDL(td->hour);
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break;
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case TOD_10HOUR:
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val = TOD_BCDH(td->hour);
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break;
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case TOD_1DAY:
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val = TOD_BCDL(td->day);
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break;
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case TOD_10DAY:
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val = TOD_BCDH(td->day);
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break;
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case TOD_1MON:
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val = TOD_BCDL(td->mon);
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break;
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case TOD_10MON:
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val = TOD_BCDH(td->mon);
|
|
break;
|
|
case TOD_WDAY:
|
|
val = td->wday;
|
|
break;
|
|
case TOD_1YEAR:
|
|
#if defined(REV3)
|
|
val = TOD_BCDL(td->year);
|
|
#else
|
|
val = td->lyear;
|
|
#endif
|
|
break;
|
|
#if defined(REV3)
|
|
case TOD_10YEAR:
|
|
val = TOD_BCDH(td->year);
|
|
break;
|
|
case TOD_SET_INT:
|
|
val = td->clkset;
|
|
break;
|
|
#endif
|
|
default:
|
|
val = 0;
|
|
break;
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
void tod_write(uint32 pa, uint32 val, size_t size)
|
|
{
|
|
uint32 reg;
|
|
TOD_DATA *td = (TOD_DATA *)(tod_unit.filebuf);
|
|
|
|
/* reg = pa - TODBASE; */
|
|
reg = pa & 0xfc;
|
|
|
|
switch(reg) {
|
|
#if defined(REV3)
|
|
case TOD_CTRL:
|
|
td->ctrl = (uint8) val;
|
|
if (val & CTRL_DISABLE) {
|
|
tod_enabled = FALSE;
|
|
td->tsec = 0;
|
|
} else {
|
|
tod_enabled = TRUE;
|
|
}
|
|
#else
|
|
case TOD_TEST:
|
|
/* test mode */
|
|
#endif
|
|
break;
|
|
case TOD_TSEC:
|
|
td->tsec = (uint8) val * 10;
|
|
break;
|
|
case TOD_1SEC:
|
|
td->sec = ((td->sec / 10) * 10) + (uint8) val;
|
|
break;
|
|
case TOD_10SEC:
|
|
td->sec = ((uint8) val * 10) + (td->sec % 10);
|
|
break;
|
|
case TOD_1MIN:
|
|
td->min = ((td->min / 10) * 10) + (uint8) val;
|
|
break;
|
|
case TOD_10MIN:
|
|
td->min = ((uint8) val * 10) + (td->min % 10);
|
|
break;
|
|
case TOD_1HOUR:
|
|
td->hour = ((td->hour / 10) * 10) + (uint8) val;
|
|
break;
|
|
case TOD_10HOUR:
|
|
td->hour = ((uint8) val * 10) + (td->hour % 10);
|
|
break;
|
|
case TOD_1DAY:
|
|
td->day = ((td->day / 10) * 10) + (uint8) val;
|
|
break;
|
|
case TOD_10DAY:
|
|
td->day = ((uint8) val * 10) + (td->day % 10);
|
|
break;
|
|
case TOD_1MON:
|
|
td->mon = ((td->mon / 10) * 10) + (uint8) val;
|
|
break;
|
|
case TOD_10MON:
|
|
td->mon = ((uint8) val * 10) + (td->mon % 10);
|
|
break;
|
|
case TOD_1YEAR:
|
|
#if defined(REV3)
|
|
td->year = ((td->year / 10) * 10) + (uint8) val;
|
|
#else
|
|
td->lyear = (uint8) val;
|
|
#endif
|
|
break;
|
|
#if defined(REV3)
|
|
case TOD_10YEAR:
|
|
td->year = ((uint8) val * 10) + (td->year % 10);
|
|
break;
|
|
case TOD_SET_INT:
|
|
td->clkset = (uint8) val;
|
|
if (!TOD_12H(td)) {
|
|
/* The AM/PM indicator is always 0 if not in 12H mode */
|
|
td->clkset &= ~(CLKSET_PM);
|
|
}
|
|
td->lyear = (val >> 2) & 3;
|
|
break;
|
|
#else
|
|
case TOD_STARTSTOP:
|
|
tod_enabled = val & 1;
|
|
break;
|
|
#endif
|
|
case TOD_WDAY:
|
|
td->wday = (uint8)val & 0x7;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
const char *tod_description(DEVICE *dptr)
|
|
{
|
|
#if defined(REV3)
|
|
return("MM58274C real time clock");
|
|
#else
|
|
return("MM58174A real time clock");
|
|
#endif
|
|
}
|
|
|
|
t_stat tod_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
char dname[10];
|
|
|
|
#if defined(REV3)
|
|
snprintf(dname, 10, "MM58274C");
|
|
#else
|
|
snprintf(dname, 10, "MM58174A");
|
|
#endif
|
|
|
|
fprintf(st, "%s Time-Of-Day Clock (%s)\n\n", dname, dptr->name);
|
|
fprintf(st, "The %s controller simulates a National Semiconductor %s\n", dptr->name, dname);
|
|
fprintf(st, "real time clock. This clock keeps track of the current system time\n");
|
|
fprintf(st, "and date.\n\n");
|
|
fprintf(st, "In order to preserve simulated calendar time between simulator runs,\n");
|
|
fprintf(st, "the %s clock may be attached to a file which stores its state while\n", dptr->name);
|
|
fprintf(st, "the simulator is not running, e.g.:\n\n");
|
|
fprintf(st, " sim> ATTACH TOD <filename>\n");
|
|
fprint_show_help(st, dptr);
|
|
fprint_reg_help(st, dptr);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
#if defined(REV3)
|
|
|
|
/*
|
|
* Fault Register
|
|
*
|
|
* The Fault Register is composed of two 32-bit registers at addresses
|
|
* 0x4C000 and 0x4D000. These latch state of the last address to cause
|
|
* a CPU fault.
|
|
*
|
|
* Bits 00-25: Physical memory address bits
|
|
*
|
|
* Fault Register 2 does double duty. It actually consists of four
|
|
* words, each of which maps to a memory slot on the system board. If
|
|
* occupied, it records the size of memory equipped in the slot, as
|
|
* well as information about any memory faults.
|
|
*
|
|
*
|
|
* Bits Active Purpose
|
|
* ----------------------------------------------------
|
|
* 31-26 H Upper Halfword ECC Syndrome Bits
|
|
* 25-20 H Lower Halfword ECC Syndeome Bits
|
|
* 19 L I/O Bus or BUB master on Fault
|
|
* 18 H Invert low addr bit 2 (DWORD1)
|
|
* 17 H Decrement low addr by 4
|
|
* 16 L I/O Bus Master on Fault
|
|
* 15 L CPU accessing I/O Peripheral
|
|
* 14 L BUB Slot 0 master on fault
|
|
* 13 L CPU Accessing BUB Peripheral
|
|
* 12-11 H BUB peripheral accessed by CPU
|
|
* 10 L BUB Slot 1 master on fault
|
|
* 9 L BUB Slot 2 master on fault
|
|
* 8 L BUB Slot 3 master on fault
|
|
* 7-3 N/A Not Used
|
|
* 2 L Memory Equipped
|
|
* 1-0 H Equipped Memory Size
|
|
*
|
|
*/
|
|
|
|
uint32 flt[2] = {0, 0};
|
|
|
|
UNIT flt_unit = {
|
|
UDATA(NULL, UNIT_FIX+UNIT_BINK, 64)
|
|
};
|
|
|
|
REG flt_reg[] = {
|
|
{ HRDATAD(FLT1, flt[0], 32, "Fault Register 1") },
|
|
{ HRDATAD(FLT2, flt[1], 32, "Fault Register 2") },
|
|
{ NULL }
|
|
};
|
|
|
|
DEVICE flt_dev = {
|
|
"FLT", &flt_unit, flt_reg, NULL,
|
|
1, 16, 32, 1, 16, 32,
|
|
NULL, NULL, NULL,
|
|
NULL, NULL, NULL,
|
|
NULL, DEV_DEBUG, 0, sys_deb_tab, NULL, NULL,
|
|
&flt_help, NULL, NULL,
|
|
&flt_description
|
|
};
|
|
|
|
/*
|
|
* Return the configured memory size for a given backplane location.
|
|
*/
|
|
static uint32 mem_size(uint8 slot) {
|
|
switch(MEM_SIZE) {
|
|
case MSIZ_8M:
|
|
if (slot <= 1) {
|
|
return MEM_EQP|MEM_4M;
|
|
} else {
|
|
return 0;
|
|
}
|
|
case MSIZ_16M:
|
|
return MEM_EQP|MEM_4M;
|
|
case MSIZ_32M:
|
|
if (slot <= 1) {
|
|
return MEM_EQP|MEM_16M;
|
|
} else {
|
|
return 0;
|
|
}
|
|
case MSIZ_64M:
|
|
return MEM_EQP|MEM_16M;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
uint32 flt_read(uint32 pa, size_t size)
|
|
{
|
|
sim_debug(EXECUTE_MSG, &flt_dev,
|
|
"Read from FLT Register at %x\n",
|
|
pa);
|
|
|
|
switch(pa) {
|
|
case FLTLBASE:
|
|
return flt[0];
|
|
case FLTHBASE:
|
|
return (flt[1] & FLT_MSK) | mem_size(0);
|
|
case FLTHBASE + 4:
|
|
return (flt[1] & FLT_MSK) | mem_size(1);
|
|
case FLTHBASE + 8:
|
|
return (flt[1] & FLT_MSK) | mem_size(2);
|
|
case FLTHBASE + 12:
|
|
return (flt[1] & FLT_MSK) | mem_size(3);
|
|
default:
|
|
sim_debug(EXECUTE_MSG, &flt_dev,
|
|
"Read from FLT Register at %x: FAILURE, NO DATA!!!!\n",
|
|
pa);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void flt_write(uint32 pa, uint32 val, size_t size)
|
|
{
|
|
sim_debug(EXECUTE_MSG, &flt_dev,
|
|
"Write to FLT Register at %x (val=%x)\n",
|
|
pa, val);
|
|
|
|
return;
|
|
}
|
|
|
|
t_stat flt_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf(st, "Fault Register\n\n");
|
|
fprintf(st, "The %s device is a pair of 32-bit registers that hold information about\n", dptr->name);
|
|
fprintf(st, "system memory faults.\n");
|
|
fprint_show_help(st, dptr);
|
|
fprint_reg_help(st, dptr);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *flt_description(DEVICE *dptr)
|
|
{
|
|
return "Fault Register";
|
|
}
|
|
|
|
#endif
|