704 lines
24 KiB
C
704 lines
24 KiB
C
/* isbc206.c: Intel iSBC 206 disk adapter
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Copyright (c) 2017, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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31 Oct 17 - Original file.
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NOTES:
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This controller will mount 1 Hard Disk removable and three Hard Disk fixed disk
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images on drives :F0: thru :F3: addressed at ports 068H to 06FH.
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Registers:
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068H - Read - Subsystem status
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bit 0 - ready status of drive 0
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bit 1 - ready status of drive 1
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bit 2 - state of channel's interrupt FF
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bit 3 - controller presence indicator
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bit 4 - DD controller presence indicator
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bit 5 - ready status of drive 2
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bit 6 - ready status of drive 3
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bit 7 - zero
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069H - Read - Read result type (bits 2-7 are zero)
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00 - I/O complete with error
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01 - Reserved
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10 - Result byte contains diskette ready status
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11 - Reserved
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069H - Write - IOPB address low byte.
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06AH - Write - IOPB address high byte and start operation.
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06BH - Read - Read result byte
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If result type is 00H
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0x01 - ID field miscompare
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0x02 - Data field CRC error
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0x04 - Seek error
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0x08 - Bad sector address error
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0x0A - ID field CRC error
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0x0B - Protocol violations
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0x0C - Bad track address error
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0x0E - No ID address mark or sector found
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0x0F - D=Bad data field address mark
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0x10 - Format error
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0x20 - write protect
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0x40 - write error
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0x80 - not ready
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06FH - Write - Reset diskette system.
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Operations:
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NOP - 0x00
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Seek - 0x01
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Format Track - 0x02
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Recalibrate - 0x03
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Read Data - 0x04
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Verify CRC - 0x05
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Write Data - 0x06
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Write Deleted Data - 0x07
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IOPB - I/O Parameter Block
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Byte 0 - Channel Word
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bit 3 - data word length (=8-bit, 1=16-bit)
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bit 4-5 - interrupt control
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00 - I/O complete interrupt to be issued
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01 - I/O complete interrupts are disabled
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10 - illegal code
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11 - illegal code
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bit 6- randon format sequence
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Byte 1 - Diskette Instruction
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bit 0-2 - operation code
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000 - no operation
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001 - seek
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010 - format track
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011 - recalibrate
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100 - read data
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101 - verify CRC
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110 - write data
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111 - write deleted data
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bit 3 - data word length ( same as byte-0, bit-3)
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bit 4-5 - unit select
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00 - drive 0
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01 - drive 1
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10 - drive 2
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11 - drive 3
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bit 6-7 - reserved (zero)
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Byte 2 - Number of Records
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Byte 4 - Track Address
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Byte 5 - Sector Address
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Byte 6 - Buffer Low Address
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Byte 7 - Buffer High Address
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u3 -
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u4 -
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u5 -
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u6 - hdd number.
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*/
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#include "system_defs.h" /* system header in system dir */
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#if defined (SBC206_NUM) && (SBC206_NUM > 0)
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#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
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#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
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#define HDD_NUM 2 //one fixed and one removable
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//disk controller operations
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#define DNOP 0x00 //HDC no operation
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#define DSEEK 0x01 //HDC seek
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#define DFMT 0x02 //HDC format
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#define DHOME 0x03 //HDC home
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#define DREAD 0x04 //HDC read
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#define DVCRC 0x05 //HDC verify CRC
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#define DWRITE 0x06 //HDC write
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//status
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#define RDY0 0x01 //HDD 0 ready
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#define RDY1 0x02 //HDD 1 ready
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#define HDCINT 0x04 //HDC interrupt flag
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#define HDCPRE 0x08 //HDC board present
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//result type
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#define ROK 0x00 //HDC returned error
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//#define RCHG 0x02 //HDC returned ok
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#define RCHG 0x01 //HDC returned ok
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// If result type is RERR then rbyte is
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#define RB0DR 0x01 //deleted record
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#define RB0CRC 0x02 //CRC error
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#define RB0SEK 0x04 //seek error
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#define RB0ADR 0x08 //address error
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#define RB0OU 0x10 //data overrun/underrun
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#define RB0WP 0x20 //write protect
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#define RB0WE 0x40 //write error
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#define RB0NR 0x80 //not ready
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// If result type is ROK then rbyte is
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#define RB1RD0 0x40 //drive 0 ready
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#define RB1RD1 0x80 //drive 1 ready
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//disk geometry values
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#define MDSHD 3796992 //hard disk HD size
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#define MAXSECHD 144 //hard disk last sector (2 heads/2 tracks)
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#define MAXTRKHD 206 //hard disk last track
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#define isbc206_NAME "Intel iSBC 206 Hard Disk Controller Board"
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/* external globals */
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extern uint16 PCX;
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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extern uint8 unreg_dev(uint8);
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extern uint8 get_mbyte(uint16 addr);
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extern void put_mbyte(uint16 addr, uint8 val);
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/* function prototypes */
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t_stat isbc206_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc206_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc206_set_verb(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc206_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat isbc206_reset(DEVICE *dptr);
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void isbc206_reset_dev(void);
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t_stat isbc206_attach (UNIT *uptr, CONST char *cptr);
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t_stat isbc206_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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uint8 isbc206r0(t_bool io, uint8 data, uint8 devnum); /* isbc206 port 0 */
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uint8 isbc206r1(t_bool io, uint8 data, uint8 devnum); /* isbc206 port 1 */
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uint8 isbc206r2(t_bool io, uint8 data, uint8 devnum); /* isbc206 port 2 */
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uint8 isbc206r3(t_bool io, uint8 data, uint8 devnum); /* isbc206 port 3 */
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uint8 isbc206r7(t_bool io, uint8 data, uint8 devnum); /* isbc206 port 7 */
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void isbc206_diskio(void); //do actual disk i/o
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/* globals */
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int isbc206_onetime = 1;
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static const char* isbc206_desc(DEVICE *dptr) {
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return isbc206_NAME;
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}
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typedef struct { //HDD definition
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int t0;
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int rdy;
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uint8 sec;
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uint8 cyl;
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} HDDDEF;
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typedef struct { //HDC definition
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uint8 baseport; //HDC base port
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uint8 intnum; //interrupt number
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uint8 verb; //verbose flag
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uint16 iopb; //HDC IOPB
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uint8 stat; //HDC status
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uint8 rdychg; //HDC ready change
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uint8 rtype; //HDC result type
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uint8 rbyte0; //HDC result byte for type 00
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uint8 rbyte1; //HDC result byte for type 10
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uint8 intff; //HDC interrupt FF
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HDDDEF hd[HDD_NUM]; //indexed by the HDD number
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} HDCDEF;
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HDCDEF hdc206; //indexed by the isbc-206 instance number
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UNIT isbc206_unit[] = { // 2 HDDs
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF|UNIT_FIX, MDSHD) },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF|UNIT_FIX, MDSHD) },
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{ NULL }
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};
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REG isbc206_reg[] = {
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{ HRDATA (STAT0, hdc206.stat, 8) }, /* isbc206 0 status */
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{ HRDATA (RTYP0, hdc206.rtype, 8) }, /* isbc206 0 result type */
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{ HRDATA (RBYT0A, hdc206.rbyte0, 8) }, /* isbc206 0 result byte 0 */
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{ HRDATA (RBYT0B, hdc206.rbyte1, 8) }, /* isbc206 0 result byte 1 */
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{ HRDATA (INTFF0, hdc206.intff, 8) }, /* isbc206 0 interrupt f/f */
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{ NULL }
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};
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MTAB isbc206_mod[] = {
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{ UNIT_WPMODE, 0, "RW", "RW", &isbc206_set_mode },
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{ UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &isbc206_set_mode },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "VERB", &isbc206_set_verb,
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NULL, NULL, "Sets the verbose mode for iSBC206"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "PORT", &isbc206_set_port,
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NULL, NULL, "Sets the base port for iSBC206"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc206_set_int,
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NULL, NULL, "Sets the interrupt number for iSBC206"},
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc206_show_param, NULL,
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"show configured parametes for iSBC206" },
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{ 0 }
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};
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DEBTAB isbc206_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE isbc206_dev = {
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"SBC206", //name
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isbc206_unit, //units
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isbc206_reg, //registers
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isbc206_mod, //modifiers
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HDD_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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isbc206_reset, //reset
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NULL, //boot
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&isbc206_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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isbc206_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* isbc206 set mode = Write protect */
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t_stat isbc206_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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if (uptr->flags & UNIT_ATT)
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return sim_messagef (SCPE_ALATT, "%s is already attached to %s\n", sim_uname(uptr), uptr->filename);
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if (val & UNIT_WPMODE) { /* write protect */
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uptr->flags |= val;
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if (hdc206.verb)
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sim_printf(" sbc206: WP\n");
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} else { /* read write */
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uptr->flags &= ~val;
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if (hdc206.verb)
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sim_printf(" sbc206: RW\n");
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}
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return SCPE_OK;
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}
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// set base address parameter
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t_stat isbc206_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result;
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if (uptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%02x", &size);
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hdc206.baseport = size;
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if (hdc206.verb)
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sim_printf("SBC206: Base port=%04X\n", hdc206.baseport);
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return SCPE_OK;
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}
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// set interrupt parameter
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t_stat isbc206_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result;
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if (uptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%02x", &size);
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hdc206.intnum = size;
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if (hdc206.verb)
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sim_printf("SBC206: Interrupt number=%04X\n", hdc206.intnum);
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return SCPE_OK;
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}
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t_stat isbc206_set_verb(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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if (cptr == NULL)
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return SCPE_ARG;
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if (strncasecmp(cptr, "OFF", 4) == 0) {
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hdc206.verb = 0;
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return SCPE_OK;
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}
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if (strncasecmp(cptr, "ON", 3) == 0) {
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hdc206.verb = 1;
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sim_printf(" SBC206: hdc206.verb=%d\n", hdc206.verb);
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return SCPE_OK;
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}
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return SCPE_ARG;
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}
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// show configuration parameters
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t_stat isbc206_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "%s Base port at %04X Interrupt # is %i %s",
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((isbc206_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
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hdc206.baseport, hdc206.intnum,
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hdc206.verb ? "Verbose" : "Quiet"
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);
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return SCPE_OK;
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}
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/* Hardware reset routine */
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t_stat isbc206_reset(DEVICE *dptr)
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{
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int i;
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UNIT *uptr;
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if (dptr == NULL)
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return SCPE_ARG;
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if (isbc206_onetime) {
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hdc206.baseport = SBC206_BASE; //set default base
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hdc206.intnum = SBC206_INT; //set default interrupt
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hdc206.verb = 0; //set verb = 0
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isbc206_onetime = 0;
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// one-time initialization for all FDDs for this FDC instance
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for (i = 0; i < HDD_NUM; i++) {
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uptr = isbc206_dev.units + i;
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uptr->u6 = i; //fdd unit number
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}
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}
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if ((dptr->flags & DEV_DIS) == 0) { // enabled
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reg_dev(isbc206r0, hdc206.baseport, 0); //read status
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reg_dev(isbc206r1, hdc206.baseport + 1, 0); //read rslt type/write IOPB addr-l
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reg_dev(isbc206r2, hdc206.baseport + 2, 0); //write IOPB addr-h and start
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reg_dev(isbc206r3, hdc206.baseport + 3, 0); //read rstl byte
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reg_dev(isbc206r7, hdc206.baseport + 7, 0); //write reset fdc201
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isbc206_reset_dev(); //software reset
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if (hdc206.verb)
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sim_printf(" sbc206: Enabled base port at 0%02XH Interrupt #=%02X %s\n",
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hdc206.baseport, hdc206.intnum, hdc206.verb ? "Verbose" : "Quiet" );
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} else {
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unreg_dev(hdc206.baseport); //read status
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unreg_dev(hdc206.baseport + 1); //read rslt type/write IOPB addr-l
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unreg_dev(hdc206.baseport + 2); //write IOPB addr-h and start
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unreg_dev(hdc206.baseport + 3); //read rstl byte
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unreg_dev(hdc206.baseport + 7); //write reset fdc201
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if (hdc206.verb)
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sim_printf(" sbc206: Disabled\n");
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}
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return SCPE_OK;
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}
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/* Software reset routine */
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void isbc206_reset_dev(void)
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{
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int32 i;
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UNIT *uptr;
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hdc206.stat = 0; //clear status
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for (i = 0; i < HDD_NUM; i++) { /* handle all units */
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uptr = isbc206_dev.units + i;
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hdc206.stat |= (HDCPRE + 0x80); //set the HDC status
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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if (uptr->flags & UNIT_ATT) { /* if attached */
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switch(i){
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case 0:
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hdc206.stat |= RDY0; //set HDD 0 ready
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hdc206.rbyte1 |= RB1RD0;
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break;
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case 1:
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hdc206.stat |= RDY1; //set HDD 1 ready
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hdc206.rbyte1 |= RB1RD1;
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break;
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}
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hdc206.rdychg = 0;
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}
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}
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}
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/* isbc206 attach - attach an .IMG file to a HDD */
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t_stat isbc206_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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uint8 hddnum;
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" isbc206_attach: Attach error %d\n", r);
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return r;
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}
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hddnum = uptr->u6;
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switch(hddnum){
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case 0:
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hdc206.stat |= RDY0; //set HDD 0 ready
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hdc206.rbyte1 |= RB1RD0;
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break;
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case 1:
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hdc206.stat |= RDY1; //set HDD 1 ready
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hdc206.rbyte1 |= RB1RD1;
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break;
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}
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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return SCPE_OK;
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}
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/* iSBC206 control port functions */
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uint8 isbc206r0(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status*/
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return hdc206.stat;
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}
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return 0;
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}
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uint8 isbc206r1(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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hdc206.intff = 0; //clear interrupt FF
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hdc206.stat &= ~(HDCINT + 0x80);
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hdc206.rtype = ROK;
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return hdc206.rtype;
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} else { /* write data port */
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hdc206.iopb = data;
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}
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return 0;
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}
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uint8 isbc206r2(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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;
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} else { /* write data port */
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hdc206.iopb |= (data << 8);
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isbc206_diskio();
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if (hdc206.intff)
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hdc206.stat |= HDCINT;
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}
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return 0;
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}
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uint8 isbc206r3(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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if (hdc206.rtype == ROK) {
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return hdc206.rbyte0;
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} else {
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if (hdc206.rdychg) {
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return hdc206.rbyte1;
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} else {
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return hdc206.rbyte0;
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}
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}
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} else { /* write data port */
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; //stop diskette operation
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}
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return 0;
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}
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uint8 isbc206r7(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read data port */
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;
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} else { /* write data port */
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isbc206_reset_dev();
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}
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return 0;
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}
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// perform the actual disk I/O operation
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void isbc206_diskio(void)
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{
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uint8 cw, di, nr, ta, sa, data, nrptr;
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uint16 ba;
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uint32 dskoff;
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uint8 hddnum, fmtb;
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uint32 i;
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UNIT *uptr;
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uint8 *fbuf;
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//parse the IOPB
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cw = get_mbyte(hdc206.iopb);
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di = get_mbyte(hdc206.iopb + 1);
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nr = get_mbyte(hdc206.iopb + 2);
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ta = get_mbyte(hdc206.iopb + 3);
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sa = get_mbyte(hdc206.iopb + 4);
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ba = get_mbyte(hdc206.iopb + 5);
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hddnum = (di & 0x30) >> 4;
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uptr = isbc206_dev.units + hddnum;
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fbuf = (uint8 *) (isbc206_dev.units + hddnum)->filebuf;
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//check for not ready
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switch(hddnum) {
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case 0:
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if ((hdc206.stat & RDY0) == 0) {
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hdc206.rtype = ROK;
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hdc206.rbyte0 = RB0NR;
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hdc206.intff = 1; //set interrupt FF
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sim_printf("\n SBC206: HDD %d - Ready error", hddnum);
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return;
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}
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break;
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case 1:
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if ((hdc206.stat & RDY1) == 0) {
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hdc206.rtype = ROK;
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hdc206.rbyte0 = RB0NR;
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hdc206.intff = 1; //set interrupt FF
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sim_printf("\n SBC206: HDD %d - Ready error", hddnum);
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return;
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}
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break;
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}
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//check for address error
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if (
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((di & 0x07) != DHOME) && (
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(sa > MAXSECHD) ||
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((sa + nr) > (MAXSECHD + 1)) ||
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(sa == 0) ||
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(ta > MAXTRKHD)
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)) {
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hdc206.rtype = ROK;
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hdc206.rbyte0 = RB0ADR;
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hdc206.intff = 1; //set interrupt FF
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sim_printf("\n SBC206: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
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hddnum, sa, nr, ta, PCX);
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return;
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}
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switch (di & 0x07) {
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case DNOP:
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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case DSEEK:
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hdc206.hd[hddnum].sec = sa;
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hdc206.hd[hddnum].cyl = ta;
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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case DHOME:
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hdc206.hd[hddnum].sec = sa;
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hdc206.hd[hddnum].cyl = 0;
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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case DVCRC:
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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case DFMT:
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//check for WP
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if(uptr->flags & UNIT_WPMODE) {
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hdc206.rtype = ROK;
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hdc206.rbyte0 = RB0WP;
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hdc206.intff = 1; //set interrupt FF
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sim_printf("\n SBC206: HDD %d - Write protect error DFMT", hddnum);
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return;
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}
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fmtb = get_mbyte(ba); //get the format byte
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//calculate offset into disk image
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dskoff = ((ta * MAXSECHD) + (sa - 1)) * 128;
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for(i=0; i<=((uint32)(MAXSECHD) * 128); i++) {
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*(fbuf + (dskoff + i)) = fmtb;
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}
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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case DREAD:
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nrptr = 0;
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while(nrptr < nr) {
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//calculate offset into disk image
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dskoff = ((ta * MAXSECHD) + (sa - 1)) * 128;
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//copy sector from image to RAM
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for (i=0; i<128; i++) {
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data = *(fbuf + (dskoff + i));
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put_mbyte(ba + i, data);
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}
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sa++;
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ba+=0x80;
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nrptr++;
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}
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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case DWRITE:
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//check for WP
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if(uptr->flags & UNIT_WPMODE) {
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hdc206.rtype = ROK;
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hdc206.rbyte0 = RB0WP;
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hdc206.intff = 1; //set interrupt FF
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sim_printf("\n SBC206: HDD %d - Write protect error DWRITE", hddnum);
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return;
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}
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nrptr = 0;
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while(nrptr < nr) {
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//calculate offset into disk image
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dskoff = ((ta * MAXSECHD) + (sa - 1)) * 128;
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//copy sector from image to RAM
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for (i=0; i<128; i++) {
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data = get_mbyte(ba + i);
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*(fbuf + (dskoff + i)) = data;
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}
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sa++;
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ba+=0x80;
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nrptr++;
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}
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hdc206.rtype = ROK;
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hdc206.rbyte0 = 0; //set no error
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hdc206.intff = 1; //set interrupt FF
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break;
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default:
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sim_printf("\n SBC206: HDD %d - isbc206_diskio bad di=%02X", hddnum, di & 0x07);
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break;
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}
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}
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#endif /* SBC206_NUM > 0 */
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/* end of isbc206.c */
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