339 lines
15 KiB
C
339 lines
15 KiB
C
/* vax610_defs.h: MicroVAX I model-specific definitions file
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Copyright (c) 2011-2012, Matt Burke
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This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name(s) of the author(s) shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author(s).
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15-Feb-2012 MB First Version
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This file covers the MicroVAX I
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System memory map
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0000 0000 - 003F FFFF main memory
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0040 0000 - 1FFF FFFF reserved
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2000 0000 - 2000 1FFF qbus address space
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2000 2000 - 3FFF FFFF reserved
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*/
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#ifdef FULL_VAX /* subset VAX */
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#undef FULL_VAX
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#endif
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#ifndef _VAX_610_DEFS_H_
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#define _VAX_610_DEFS_H_ 1
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/* Microcode constructs */
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#define VAX610_SID (7 << 24) /* system ID */
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#define VAX610_FLOAT (1 << 16) /* floating point type */
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#define VAX610_MREV (5 << 8) /* microcode revision */
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#define VAX610_HWREV 1 /* hardware revision */
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_PWRUP 0x0300 /* powerup code */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define CON_BADPSL 0x4000 /* invalid PSL flag */
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#define CON_MAPON 0x8000 /* mapping on flag */
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#define MCHK_TBM_P0 0x05 /* PPTE in P0 */
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#define MCHK_TBM_P1 0x06 /* PPTE in P1 */
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#define MCHK_M0_P0 0x07 /* PPTE in P0 */
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#define MCHK_M0_P1 0x08 /* PPTE in P1 */
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#define MCHK_INTIPL 0x09 /* invalid ireq */
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#define MCHK_READ 0x02 /* read check */
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#define MCHK_WRITE 0x02 /* write check */
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/* Machine specific IPRs */
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#define MT_TBDR 36 /* Translation Buffer Disable */
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#define MT_CADR 37 /* Cache Disable Register */
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#define MT_MCESR 38 /* Machine Check Error Summary */
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#define MT_CAER 39 /* Cache Error Register */
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#define MT_CONISP 41 /* Console Saved ISP */
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#define MT_CONPC 42 /* Console Saved PC */
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#define MT_CONPSL 43 /* Console Saved PSL */
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#define MT_SBIFS 48 /* SBI fault status */
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#define MT_SBIS 49 /* SBI silo */
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#define MT_SBISC 50 /* SBI silo comparator */
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#define MT_SBIMT 51 /* SBI maint */
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#define MT_SBIER 52 /* SBI error */
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#define MT_SBITA 53 /* SBI timeout addr */
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#define MT_SBIQC 54 /* SBI timeout clear */
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#define MT_IORESET 55 /* I/O Bus Reset */
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#define MT_TBDATA 59 /* Translation Buffer Data */
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#define MT_MBRK 60 /* microbreak */
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#define MT_MAX 63 /* last valid IPR */
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/* Memory */
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#define MAXMEMWIDTH 22 /* max mem, KA610 */
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#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */
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#define MAXMEMWIDTH_X 22 /* max mem, KA610 */
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#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
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#define INITMEMSIZE (1 << 22) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#undef PAMASK
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#define PAMASK 0x203FFFFF /* KA610 needs a special mask */
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 19), NULL, "512k", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
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{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }
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#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \
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NULL, &cpu_show_leds }, \
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{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
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NULL, &cpu_show_model },
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/* Qbus I/O page */
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#define IOPAGEAWIDTH 13 /* IO addr width */
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#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */
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#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */
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#define IOPAGEBASE 0x20000000 /* IO page base */
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#define ADDR_IS_IO(x) ((((uint32) (x)) >= IOPAGEBASE) && \
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(((uint32) (x)) < (IOPAGEBASE + IOPAGESIZE)))
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/* Other address spaces */
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#define ADDR_IS_CDG(x) (0)
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#define ADDR_IS_ROM(x) (0)
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#define ADDR_IS_NVR(x) (0)
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/* Machine specific reserved operand tests (all NOPs) */
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_SBR_TEST(r)
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#define ML_PXBR_TEST(r)
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#define LP_AST_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define WRITE (L_WORD)
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#define WRITEB (L_BYTE)
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/* Common CSI flags */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Timers */
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#define TMR_CLK 0 /* 100Hz clock */
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/* I/O system definitions */
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#define DZ_MUXES 4 /* max # of DZV muxes */
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#define DZ_LINES 4 /* lines per DZV mux */
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#define VH_MUXES 4 /* max # of DHQ muxes */
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#define DLX_LINES 16 /* max # of KL11/DL11's */
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#define DCX_LINES 16 /* max # of DC11's */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define AUTO_LNT 34 /* autoconfig ranks */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */
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#define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */
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#define DEV_UBUS (1u << DEV_V_UBUS)
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#define DEV_QBUS (1u << DEV_V_QBUS)
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#define DEV_Q18 (1u << DEV_V_Q18)
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#define UNIBUS FALSE /* 22b only */
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#define DEV_RDX 16 /* default device radix */
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/* Device information block */
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#define VEC_DEVMAX 4 /* max device vec */
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typedef struct {
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uint32 ba; /* base addr */
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uint32 lnt; /* length */
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t_stat (*rd)(int32 *dat, int32 ad, int32 md);
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t_stat (*wr)(int32 dat, int32 ad, int32 md);
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int32 vnum; /* vectors: number */
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int32 vloc; /* locator */
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int32 vec; /* value */
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int32 (*ack[VEC_DEVMAX])(void); /* ack routine */
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} DIB;
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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/* The KA610 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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however, DEC Qbus controllers all interrupt on IPL 14
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Within each IPL, priority is right to left
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*/
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/* IPL 17 */
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/* IPL 16 */
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#define INT_V_CLK 0 /* clock */
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/* IPL 15 */
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/* IPL 14 - devices through RY are IPL 15 on Unibus systems */
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#define INT_V_RQ 0 /* RQDX3 */
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#define INT_V_RL 1 /* RLV12/RL02 */
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#define INT_V_DZRX 2 /* DZ11 */
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#define INT_V_DZTX 3
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#define INT_V_TS 4 /* TS11/TSV05 */
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#define INT_V_TQ 5 /* TMSCP */
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#define INT_V_XQ 6 /* DEQNA/DELQA */
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#define INT_V_RY 7 /* RXV21 */
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#define INT_V_TTI 8 /* console */
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#define INT_V_TTO 9
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#define INT_V_PTR 10 /* PC11 */
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#define INT_V_PTP 11
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#define INT_V_LPT 12 /* LP11 */
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#define INT_V_CSI 13 /* SSC cons UART */
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#define INT_V_CSO 14
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#define INT_V_TMR0 15 /* SSC timers */
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#define INT_V_TMR1 16
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#define INT_V_VHRX 17 /* DHQ11 */
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#define INT_V_VHTX 18
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#define INT_V_QDSS 19 /* QDSS */
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#define INT_V_CR 20
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#define INT_V_QVSS 21 /* QVSS */
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_RL (1u << INT_V_RL)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_TS (1u << INT_V_TS)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_XQ (1u << INT_V_XQ)
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#define INT_RY (1u << INT_V_RY)
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#define INT_TTI (1u << INT_V_TTI)
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#define INT_TTO (1u << INT_V_TTO)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_CSI (1u << INT_V_CSI)
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#define INT_CSO (1u << INT_V_CSO)
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#define INT_TMR0 (1u << INT_V_TMR0)
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#define INT_TMR1 (1u << INT_V_TMR1)
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#define INT_VHRX (1u << INT_V_VHRX)
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#define INT_VHTX (1u << INT_V_VHTX)
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#define INT_QDSS (1u << INT_V_QDSS)
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#define INT_CR (1u << INT_V_CR)
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#define INT_QVSS (1u << INT_V_QVSS)
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#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
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#define IPL_RQ (0x14 - IPL_HMIN)
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#define IPL_RL (0x14 - IPL_HMIN)
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#define IPL_DZRX (0x14 - IPL_HMIN)
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#define IPL_DZTX (0x14 - IPL_HMIN)
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#define IPL_TS (0x14 - IPL_HMIN)
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#define IPL_TQ (0x14 - IPL_HMIN)
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#define IPL_XQ (0x14 - IPL_HMIN)
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#define IPL_RY (0x14 - IPL_HMIN)
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#define IPL_TTI (0x14 - IPL_HMIN)
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#define IPL_TTO (0x14 - IPL_HMIN)
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#define IPL_PTR (0x14 - IPL_HMIN)
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#define IPL_PTP (0x14 - IPL_HMIN)
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#define IPL_LPT (0x14 - IPL_HMIN)
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#define IPL_CSI (0x14 - IPL_HMIN)
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#define IPL_CSO (0x14 - IPL_HMIN)
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#define IPL_TMR0 (0x14 - IPL_HMIN)
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#define IPL_TMR1 (0x14 - IPL_HMIN)
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#define IPL_VHRX (0x14 - IPL_HMIN)
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#define IPL_VHTX (0x14 - IPL_HMIN)
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#define IPL_QDSS (0x14 - IPL_HMIN)
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#define IPL_CR (0x14 - IPL_HMIN)
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#define IPL_QVSS (0x14 - IPL_HMIN)
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#define IPL_HMAX 0x17 /* highest hwre level */
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#define IPL_HMIN 0x14 /* lowest hwre level */
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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/* Device vectors */
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#define VEC_AUTO (0) /* Assigned by Auto Configure */
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#define VEC_FLOAT (0) /* Assigned by Auto Configure */
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#define VEC_QBUS 1 /* Qbus system */
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#define VEC_Q 0x200 /* Qbus vector offset */
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/* Interrupt macros */
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#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
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#define IREQ(dv) int_req[IPL_##dv]
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#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
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#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* Logging */
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#define LOG_CPU_I 0x1 /* intexc */
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#define LOG_CPU_R 0x2 /* REI */
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#define LOG_CPU_P 0x4 /* context */
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/* Function prototypes for virtual memory interface */
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int32 Read (uint32 va, int32 lnt, int32 acc);
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void Write (uint32 va, int32 val, int32 lnt, int32 acc);
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/* Function prototypes for physical memory interface (inlined) */
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SIM_INLINE int32 ReadB (uint32 pa);
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SIM_INLINE int32 ReadW (uint32 pa);
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SIM_INLINE int32 ReadL (uint32 pa);
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SIM_INLINE int32 ReadLP (uint32 pa);
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SIM_INLINE void WriteB (uint32 pa, int32 val);
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SIM_INLINE void WriteW (uint32 pa, int32 val);
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SIM_INLINE void WriteL (uint32 pa, int32 val);
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void WriteLP (uint32 pa, int32 val);
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/* Function prototypes for I/O */
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
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int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
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int32 clk_cosched (int32 wait);
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t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat cpu_show_leds (FILE *st, UNIT *uptr, int32 val, void *desc);
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#include "pdp11_io_lib.h"
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#endif
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