831 lines
35 KiB
C
831 lines
35 KiB
C
/* hp2100_dr.c: HP 2100 12606B/12610B fixed head disk/drum simulator
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Copyright (c) 1993-2016, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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DR 12606B 2770/2771 fixed head disk
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12610B 2773/2774/2775 drum
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10-Nov-16 JDB Modified the drc_boot routine to use the BBDL
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05-Aug-16 JDB Renamed the P register from "PC" to "PR"
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13-May-16 JDB Modified for revised SCP API function parameter types
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30-Dec-14 JDB Added S-register parameters to ibl_copy
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24-Dec-14 JDB Added casts for explicit downward conversions
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10-Feb-12 JDB Deprecated DEVNO in favor of SC
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28-Mar-11 JDB Tidied up signal handling
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26-Oct-10 JDB Changed I/O signal handler for revised signal model
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09-Jul-08 JDB Revised drc_boot to use ibl_copy
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26-Jun-08 JDB Rewrote device I/O to model backplane signals
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28-Dec-06 JDB Added ioCRS state to I/O decoders
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07-Oct-04 JDB Fixed enable/disable from either device
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Fixed sector return in status word
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Provided protected tracks and "Writing Enabled" status bit
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Fixed DMA last word write, incomplete sector fill value
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Added "parity error" status return on writes for 12606
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Added track origin test for 12606
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Added SCP test for 12606
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Fixed 12610 SFC operation
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Added "Sector Flag" status bit
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Added "Read Inhibit" status bit for 12606
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Fixed current-sector determination
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Added PROTECTED, UNPROTECTED, TRACKPROT modifiers
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26-Aug-04 RMS Fixed CLC to stop operation (from Dave Bryan)
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26-Apr-04 RMS Fixed SFS x,C and SFC x,C
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Revised boot rom to use IBL algorithm
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Implemented DMA SRQ (follows FLG)
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27-Jul-03 RMS Fixed drum sizes
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Fixed variable capacity interaction with SAVE/RESTORE
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10-Nov-02 RMS Added BOOT command
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References:
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- 12606B Disc Memory Interface Kit Operating and Service Manual
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(12606-90012, Mar-1970)
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- 12610B Drum Memory Interface Kit Operating and Service Manual
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(12610-9001, Feb-1970)
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These head-per-track devices are buffered in memory, to minimize overhead.
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The drum data channel does not have a command flip-flop. Its control
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flip-flop is not wired into the interrupt chain; accordingly, the
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simulator uses command rather than control for the data channel. Its
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flag does not respond to SFS, SFC, or STF.
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The drum control channel does not have any of the traditional flip-flops.
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The 12606 interface implements two diagnostic tests. An SFS CC instruction
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will skip if the disk has passed the track origin (sector 0) since the last
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CLF CC instruction, and an SFC CC instruction will skip if the Sector Clock
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Phase (SCP) flip-flop is clear, indicating that the current sector is
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accessible. The 12610 interface does not support these tests; the SKF signal
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is not driven, so neither SFC CC nor SFS CC will skip.
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The interface implements a track protect mechanism via a switch and a set of
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on-card diodes. The switch sets the protected/unprotected status, and the
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particular diodes installed indicate the range of tracks (a power of 2) that
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are read-only in the protected mode.
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Somewhat unusually, writing to a protected track completes normally, but the
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data isn't actually written, as the write current is inhibited. There is no
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"failure" status indication. Instead, a program must note the lack of
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"Writing Enabled" status before the write is attempted.
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Specifications (2770/2771):
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- 90 sectors per logical track
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- 45 sectors per revolution
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- 64 words per sector
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- 2880 words per revolution
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- 3450 RPM = 17.4 ms/revolution
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- data timing = 6.0 us/word, 375 us/sector
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- inst timing = 4 inst/word, 11520 inst/revolution
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Specifications 2773/2774/2775:
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- 32 sectors per logical track
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- 32 sectors per revolution
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- 64 words per sector
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- 2048 words per revolution
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- 3450 RPM = 17.4 ms/revolution
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- data timing = 8.5 us/word, 550 us/sector
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- inst timing = 6 inst/word, 12288 inst/revolution
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*/
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#include "hp2100_defs.h"
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#include "hp2100_cpu.h"
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#include <math.h>
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/* Constants */
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#define DR_NUMWD 64 /* words/sector */
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#define DR_FNUMSC 90 /* fhd sec/track */
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#define DR_DNUMSC 32 /* drum sec/track */
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#define DR_NUMSC ((drc_unit.flags & UNIT_DRUM)? DR_DNUMSC: DR_FNUMSC)
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#define DR_SIZE (512 * DR_DNUMSC * DR_NUMWD) /* initial size */
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#define DR_FTIME 4 /* fhd per-word time */
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#define DR_DTIME 6 /* drum per-word time */
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#define DR_OVRHEAD 5 /* overhead words at track start */
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#define UNIT_V_PROT (UNIT_V_UF + 0) /* track protect */
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#define UNIT_V_SZ (UNIT_V_UF + 1) /* disk vs drum */
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#define UNIT_M_SZ 017 /* size */
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#define UNIT_PROT (1 << UNIT_V_PROT)
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#define UNIT_SZ (UNIT_M_SZ << UNIT_V_SZ)
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#define UNIT_DRUM (1 << UNIT_V_SZ) /* low order bit */
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#define SZ_180K 000 /* disks */
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#define SZ_360K 002
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#define SZ_720K 004
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#define SZ_1024K 001 /* drums: default size */
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#define SZ_1536K 003
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#define SZ_384K 005
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#define SZ_512K 007
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#define SZ_640K 011
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#define SZ_768K 013
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#define SZ_896K 015
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#define DR_GETSZ(x) (((x) >> UNIT_V_SZ) & UNIT_M_SZ)
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/* Command word */
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#define CW_WR 0100000 /* write vs read */
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#define CW_V_FTRK 7 /* fhd track */
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#define CW_M_FTRK 0177
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#define CW_V_DTRK 5 /* drum track */
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#define CW_M_DTRK 01777
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#define MAX_TRK (((drc_unit.flags & UNIT_DRUM)? CW_M_DTRK: CW_M_FTRK) + 1)
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#define CW_GETTRK(x) ((drc_unit.flags & UNIT_DRUM)? \
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(((x) >> CW_V_DTRK) & CW_M_DTRK): \
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(((x) >> CW_V_FTRK) & CW_M_FTRK))
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#define CW_PUTTRK(x) ((drc_unit.flags & UNIT_DRUM)? \
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(((x) & CW_M_DTRK) << CW_V_DTRK): \
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(((x) & CW_M_FTRK) << CW_V_FTRK))
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#define CW_V_FSEC 0 /* fhd sector */
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#define CW_M_FSEC 0177
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#define CW_V_DSEC 0 /* drum sector */
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#define CW_M_DSEC 037
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#define CW_GETSEC(x) ((drc_unit.flags & UNIT_DRUM)? \
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(((x) >> CW_V_DSEC) & CW_M_DSEC): \
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(((x) >> CW_V_FSEC) & CW_M_FSEC))
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#define CW_PUTSEC(x) ((drc_unit.flags & UNIT_DRUM)? \
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(((x) & CW_M_DSEC) << CW_V_DSEC): \
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(((x) & CW_M_FSEC) << CW_V_FSEC))
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/* Status register, ^ = dynamic */
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#define DRS_V_NS 8 /* ^next sector */
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#define DRS_M_NS 0177
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#define DRS_SEC 0100000 /* ^sector flag */
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#define DRS_RDY 0000200 /* ^ready */
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#define DRS_RIF 0000100 /* ^read inhibit */
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#define DRS_SAC 0000040 /* sector coincidence */
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#define DRS_ABO 0000010 /* abort */
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#define DRS_WEN 0000004 /* ^write enabled */
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#define DRS_PER 0000002 /* parity error */
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#define DRS_BSY 0000001 /* ^busy */
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#define CALC_SCP(x) (((int32) fmod ((x) / (double) dr_time, \
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(double) (DR_NUMWD))) >= (DR_NUMWD - 3))
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int32 drc_cw = 0; /* fnc, addr */
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int32 drc_sta = 0; /* status */
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int32 drc_run = 0; /* run flip-flop */
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struct {
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FLIP_FLOP control; /* control flip-flop */
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FLIP_FLOP flag; /* flag flip-flop */
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} drd = { CLEAR, CLEAR };
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int32 drd_ibuf = 0; /* input buffer */
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int32 drd_obuf = 0; /* output buffer */
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int32 drd_ptr = 0; /* sector pointer */
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int32 drc_pcount = 1; /* number of prot tracks */
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int32 dr_stopioe = 1; /* stop on error */
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int32 dr_time = DR_DTIME; /* time per word */
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static int32 sz_tab[16] = {
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184320, 1048576, 368640, 1572864, 737280, 393216, 0, 524288,
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0, 655360, 0, 786432, 0, 917504, 0, 0 };
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IOHANDLER drdio;
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IOHANDLER drcio;
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t_stat drc_svc (UNIT *uptr);
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t_stat drc_reset (DEVICE *dptr);
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t_stat drc_attach (UNIT *uptr, CONST char *cptr);
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t_stat drc_boot (int32 unitno, DEVICE *dptr);
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int32 dr_incda (int32 trk, int32 sec, int32 ptr);
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int32 dr_seccntr (double simtime);
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t_stat dr_set_prot (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat dr_show_prot (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat dr_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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DEVICE drd_dev, drc_dev;
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/* DRD data structures
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drd_dev device descriptor
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drd_unit unit descriptor
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drd_reg register list
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*/
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DIB dr_dib[] = {
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{ &drdio, DRD },
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{ &drcio, DRC }
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};
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#define drd_dib dr_dib[0]
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#define drc_dib dr_dib[1]
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UNIT drd_unit[] = {
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{ UDATA (NULL, 0, 0) },
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{ UDATA (NULL, UNIT_DIS, 0) }
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};
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#define TMR_ORG 0 /* origin timer */
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#define TMR_INH 1 /* inhibit timer */
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REG drd_reg[] = {
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{ ORDATA (IBUF, drd_ibuf, 16) },
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{ ORDATA (OBUF, drd_obuf, 16) },
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{ FLDATA (CTL, drd.control, 0) },
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{ FLDATA (FLG, drd.flag, 0) },
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{ ORDATA (BPTR, drd_ptr, 6) },
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{ ORDATA (SC, drd_dib.select_code, 6), REG_HRO },
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{ ORDATA (DEVNO, drd_dib.select_code, 6), REG_HRO },
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{ NULL }
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};
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MTAB drd_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 1, "SC", "SC", &hp_setsc, &hp_showsc, &drd_dev },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "DEVNO", "DEVNO", &hp_setdev, &hp_showdev, &drd_dev },
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{ 0 }
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};
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DEVICE drd_dev = {
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"DRD", drd_unit, drd_reg, drd_mod,
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2, 0, 0, 0, 0, 0,
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NULL, NULL, &drc_reset,
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NULL, NULL, NULL,
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&drd_dib, DEV_DISABLE
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};
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/* DRC data structures
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drc_dev device descriptor
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drc_unit unit descriptor
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drc_mod unit modifiers
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drc_reg register list
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*/
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UNIT drc_unit = {
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UDATA (&drc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+
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UNIT_MUSTBUF+UNIT_DRUM+UNIT_BINK, DR_SIZE)
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};
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REG drc_reg[] = {
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{ DRDATA (PCNT, drc_pcount, 10), REG_HIDDEN | PV_LEFT },
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{ ORDATA (CW, drc_cw, 16) },
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{ ORDATA (STA, drc_sta, 16) },
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{ FLDATA (RUN, drc_run, 0) },
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{ DRDATA (TIME, dr_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, dr_stopioe, 0) },
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{ ORDATA (SC, drc_dib.select_code, 6), REG_HRO },
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{ ORDATA (DEVNO, drc_dib.select_code, 6), REG_HRO },
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{ DRDATA (CAPAC, drc_unit.capac, 24), REG_HRO },
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{ NULL }
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};
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MTAB drc_mod[] = {
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{ UNIT_DRUM, 0, "disk", NULL, NULL },
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{ UNIT_DRUM, UNIT_DRUM, "drum", NULL, NULL },
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{ UNIT_SZ, (SZ_180K << UNIT_V_SZ), NULL, "180K", &dr_set_size },
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{ UNIT_SZ, (SZ_360K << UNIT_V_SZ), NULL, "360K", &dr_set_size },
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{ UNIT_SZ, (SZ_720K << UNIT_V_SZ), NULL, "720K", &dr_set_size },
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{ UNIT_SZ, (SZ_384K << UNIT_V_SZ), NULL, "384K", &dr_set_size },
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{ UNIT_SZ, (SZ_512K << UNIT_V_SZ), NULL, "512K", &dr_set_size },
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{ UNIT_SZ, (SZ_640K << UNIT_V_SZ), NULL, "640K", &dr_set_size },
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{ UNIT_SZ, (SZ_768K << UNIT_V_SZ), NULL, "768K", &dr_set_size },
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{ UNIT_SZ, (SZ_896K << UNIT_V_SZ), NULL, "896K", &dr_set_size },
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{ UNIT_SZ, (SZ_1024K << UNIT_V_SZ), NULL, "1024K", &dr_set_size },
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{ UNIT_SZ, (SZ_1536K << UNIT_V_SZ), NULL, "1536K", &dr_set_size },
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{ UNIT_PROT, UNIT_PROT, "protected", "PROTECTED", NULL },
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{ UNIT_PROT, 0, "unprotected", "UNPROTECTED", NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "TRACKPROT", "TRACKPROT",
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&dr_set_prot, &dr_show_prot, NULL },
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{ MTAB_XTD | MTAB_VDV, 1, "SC", "SC", &hp_setsc, &hp_showsc, &drd_dev },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "DEVNO", "DEVNO", &hp_setdev, &hp_showdev, &drd_dev },
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{ 0 }
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};
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DEVICE drc_dev = {
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"DRC", &drc_unit, drc_reg, drc_mod,
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1, 8, 21, 1, 8, 16,
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NULL, NULL, &drc_reset,
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&drc_boot, &drc_attach, NULL,
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&drc_dib, DEV_DISABLE
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};
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/* Data channel I/O signal handler.
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The data channel card does not follow the usual interface I/O configuration.
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PRL is always asserted, the card does not drive IRQ, FLG, or SKF and does not
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respond to IAK. SRQ is driven by the output of the flag flip-flop, which
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obeys CLF only. There is no flag buffer. The control flip-flop obeys STC
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and CLC. Clearing control clears the flag flip-flop, and setting control
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sets the flag flip-flop if the interface is configured for writing. On the
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12606B, POPIO and CRS clear the track address register.
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Implementation notes:
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1. In response to CRS, the 12606B data channel clears only the track address
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register; the command channel clears the sector address register and the
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direction flip-flop. Under simulation, all three form the control word,
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and as CRS is sent to all devices, we simply clear the control word here.
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*/
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uint32 drdio (DIB *dibptr, IOCYCLE signal_set, uint32 stat_data)
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{
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int32 t;
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IOSIGNAL signal;
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IOCYCLE working_set = IOADDSIR (signal_set); /* add ioSIR if needed */
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while (working_set) {
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signal = IONEXT (working_set); /* isolate next signal */
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switch (signal) { /* dispatch I/O signal */
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case ioCLF: /* clear flag flip-flop */
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drd.flag = CLEAR;
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break;
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case ioENF: /* enable flag */
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drd.flag = SET;
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break;
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case ioIOI: /* I/O data input */
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stat_data = IORETURN (SCPE_OK, drd_ibuf); /* merge in return status */
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break;
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case ioIOO: /* I/O data output */
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drd_obuf = IODATA (stat_data); /* clear supplied status */
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break;
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case ioCRS: /* control reset */
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if (!(drc_unit.flags & UNIT_DRUM)) /* 12606B? */
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drc_cw = 0; /* clear control word */
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/* fall into CLC handler */
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case ioCLC: /* clear control flip-flop */
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drd.flag = drd.control = CLEAR; /* clear control and flag */
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if (!drc_run) /* cancel curr op */
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sim_cancel (&drc_unit);
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drc_sta = drc_sta & ~DRS_SAC; /* clear SAC flag */
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break;
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case ioSTC: /* set control flip-flop */
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drd.control = SET; /* set ctl */
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if (drc_cw & CW_WR) /* writing? */
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drd.flag = SET; /* prime DMA */
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drc_sta = 0; /* clr status */
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drd_ptr = 0; /* clear sec ptr */
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sim_cancel (&drc_unit); /* cancel curr op */
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t = CW_GETSEC (drc_cw) - dr_seccntr (sim_gtime());
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if (t <= 0) t = t + DR_NUMSC;
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sim_activate (&drc_unit, t * DR_NUMWD * dr_time);
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break;
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case ioSIR: /* set interrupt request */
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setstdSRQ (drd); /* set SRQ signal */
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break;
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default: /* all other signals */
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break; /* are ignored */
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}
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working_set = working_set & ~signal; /* remove current signal from set */
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}
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return stat_data;
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}
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/* Command channel I/O signal dispatcher.
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The command channel card does not follow the usual interface I/O
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configuration. PRL is always asserted, the card does not drive IRQ, FLG, or
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SRQ and does not respond to IAK. There are no control, flag, or flag buffer
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flip-flops. CLF clears the track origin flip-flop; STF is ignored. The
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12606B drives SKF, whereas the 12610B does not. On the 12610B, SFS tests the
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Track Origin flip-flop, and SFC tests the Sector Clock Phase (SCP) flip-flop.
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Implementation notes:
|
|
|
|
1. CRS clears the Run Flip-Flop, stopping the current operation. Under
|
|
simulation, we allow the data channel signal handler to do this, as the
|
|
same operation is invoked by CLC DC, and as CRS is sent to all devices.
|
|
|
|
2. The command channel cannot interrupt, so there is no SIR handler.
|
|
*/
|
|
|
|
uint32 drcio (DIB *dibptr, IOCYCLE signal_set, uint32 stat_data)
|
|
{
|
|
|
|
uint16 data;
|
|
int32 sec;
|
|
IOSIGNAL signal;
|
|
IOCYCLE working_set = IOADDSIR (signal_set); /* add ioSIR if needed */
|
|
|
|
while (working_set) {
|
|
signal = IONEXT (working_set); /* isolate next signal */
|
|
|
|
switch (signal) { /* dispatch I/O signal */
|
|
|
|
case ioCLF: /* clear flag flip-flop */
|
|
if (!(drc_unit.flags & UNIT_DRUM)) { /* disk? */
|
|
sec = dr_seccntr (sim_gtime ()); /* current sector */
|
|
sim_cancel (&drd_unit[TMR_ORG]); /* sched origin tmr */
|
|
sim_activate (&drd_unit[TMR_ORG],
|
|
(DR_FNUMSC - sec) * DR_NUMWD * dr_time);
|
|
}
|
|
break;
|
|
|
|
|
|
case ioSFC: /* skip if flag is clear */
|
|
if (!(drc_unit.flags & UNIT_DRUM)) /* 12606? */
|
|
setSKF (!(CALC_SCP (sim_gtime()))); /* skip if nearing end of sector */
|
|
break;
|
|
|
|
|
|
case ioSFS: /* skip if flag is set */
|
|
if (!(drc_unit.flags & UNIT_DRUM)) /* 12606? */
|
|
setSKF (!sim_is_active (&drd_unit[TMR_ORG])); /* skip if origin seen */
|
|
break;
|
|
|
|
|
|
case ioIOI: /* I/O data input */
|
|
data = (uint16) drc_sta; /* static bits */
|
|
|
|
if (!(drc_unit.flags & UNIT_PROT) || /* not protected? */
|
|
(CW_GETTRK(drc_cw) >= drc_pcount)) /* or not in range? */
|
|
data = data | DRS_WEN; /* set wrt enb status */
|
|
|
|
if (drc_unit.flags & UNIT_ATT) { /* attached? */
|
|
data = data | (uint16) (dr_seccntr (sim_gtime()) << DRS_V_NS) | DRS_RDY;
|
|
if (sim_is_active (&drc_unit)) /* op in progress? */
|
|
data = data | DRS_BSY;
|
|
if (CALC_SCP (sim_gtime())) /* SCP ff set? */
|
|
data = data | DRS_SEC; /* set sector flag */
|
|
if (sim_is_active (&drd_unit[TMR_INH]) && /* inhibit timer on? */
|
|
!(drc_cw & CW_WR))
|
|
data = data | DRS_RIF; /* set read inh flag */
|
|
}
|
|
|
|
stat_data = IORETURN (SCPE_OK, data); /* merge in return status */
|
|
break;
|
|
|
|
|
|
case ioIOO: /* I/O data output */
|
|
if (!(drc_unit.flags & UNIT_DRUM)) { /* disk? */
|
|
sim_cancel (&drd_unit[TMR_INH]); /* schedule inhibit timer */
|
|
sim_activate (&drd_unit[TMR_INH], DR_FTIME * DR_NUMWD);
|
|
}
|
|
drc_cw = IODATA (stat_data); /* get control word */
|
|
break;
|
|
|
|
|
|
default: /* all other signals */
|
|
break; /* are ignored */
|
|
}
|
|
|
|
working_set = working_set & ~signal; /* remove current signal from set */
|
|
}
|
|
|
|
return stat_data;
|
|
}
|
|
|
|
|
|
/* Unit service */
|
|
|
|
t_stat drc_svc (UNIT *uptr)
|
|
{
|
|
int32 trk, sec;
|
|
uint32 da;
|
|
uint16 *bptr = (uint16 *) uptr->filebuf;
|
|
|
|
if ((uptr->flags & UNIT_ATT) == 0) {
|
|
drc_sta = DRS_ABO;
|
|
return IOERROR (dr_stopioe, SCPE_UNATT);
|
|
}
|
|
|
|
trk = CW_GETTRK (drc_cw);
|
|
sec = CW_GETSEC (drc_cw);
|
|
da = ((trk * DR_NUMSC) + sec) * DR_NUMWD;
|
|
drc_sta = drc_sta | DRS_SAC;
|
|
drc_run = 1; /* set run ff */
|
|
|
|
if (drc_cw & CW_WR) { /* write? */
|
|
if ((da < uptr->capac) && (sec < DR_NUMSC)) {
|
|
bptr[da + drd_ptr] = (uint16) drd_obuf;
|
|
if (((uint32) (da + drd_ptr)) >= uptr->hwmark)
|
|
uptr->hwmark = da + drd_ptr + 1;
|
|
}
|
|
drd_ptr = dr_incda (trk, sec, drd_ptr); /* inc disk addr */
|
|
if (drd.control) { /* dch active? */
|
|
drdio (&drd_dib, ioENF, 0); /* set SRQ */
|
|
sim_activate (uptr, dr_time); /* sched next word */
|
|
}
|
|
else { /* done */
|
|
if (drd_ptr) /* need to fill? */
|
|
for ( ; drd_ptr < DR_NUMWD; drd_ptr++)
|
|
bptr[da + drd_ptr] = (uint16) drd_obuf; /* fill with last word */
|
|
if (!(drc_unit.flags & UNIT_DRUM)) /* disk? */
|
|
drc_sta = drc_sta | DRS_PER; /* parity bit sets on write */
|
|
drc_run = 0; /* clear run ff */
|
|
}
|
|
} /* end write */
|
|
else { /* read */
|
|
if (drd.control) { /* dch active? */
|
|
if ((da >= uptr->capac) || (sec >= DR_NUMSC)) drd_ibuf = 0;
|
|
else drd_ibuf = bptr[da + drd_ptr];
|
|
drd_ptr = dr_incda (trk, sec, drd_ptr);
|
|
drdio (&drd_dib, ioENF, 0); /* set SRQ */
|
|
sim_activate (uptr, dr_time); /* sched next word */
|
|
}
|
|
else drc_run = 0; /* clear run ff */
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Increment current disk address */
|
|
|
|
int32 dr_incda (int32 trk, int32 sec, int32 ptr)
|
|
{
|
|
ptr = ptr + 1; /* inc pointer */
|
|
if (ptr >= DR_NUMWD) { /* end sector? */
|
|
ptr = 0; /* new sector */
|
|
sec = sec + 1; /* adv sector */
|
|
if (sec >= DR_NUMSC) { /* end track? */
|
|
sec = 0; /* new track */
|
|
trk = trk + 1; /* adv track */
|
|
if (trk >= MAX_TRK) trk = 0; /* wraps at max */
|
|
}
|
|
drc_cw = (drc_cw & CW_WR) | CW_PUTTRK (trk) | CW_PUTSEC (sec);
|
|
}
|
|
return ptr;
|
|
}
|
|
|
|
/* Read the sector counter
|
|
|
|
The hardware sector counter contains the number of the next sector that will
|
|
pass under the heads (so it is one ahead of the current sector). For the
|
|
duration of the last sector of the track, the sector counter contains 90 for
|
|
the 12606 and 0 for the 12610. The sector counter resets to 0 at track
|
|
origin and increments at the start of the first sector. Therefore, the
|
|
counter value ranges from 0-90 for the 12606 and 0-31 for the 12610. The 0
|
|
state is quite short in the 12606 and long in the 12610, relative to the
|
|
other sector counter states.
|
|
|
|
The simulated sector counter is calculated from the simulation time, based on
|
|
the time per word and the number of words per track.
|
|
*/
|
|
|
|
int32 dr_seccntr (double simtime)
|
|
{
|
|
int32 curword;
|
|
|
|
curword = (int32) fmod (simtime / (double) dr_time,
|
|
(double) (DR_NUMWD * DR_NUMSC + DR_OVRHEAD));
|
|
if (curword <= DR_OVRHEAD) return 0;
|
|
else return ((curword - DR_OVRHEAD) / DR_NUMWD +
|
|
((drc_unit.flags & UNIT_DRUM)? 0: 1));
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat drc_reset (DEVICE *dptr)
|
|
{
|
|
DIB *dibptr = (DIB *) dptr->ctxt; /* DIB pointer */
|
|
|
|
hp_enbdis_pair (dptr, /* make pair cons */
|
|
(dptr == &drd_dev)? &drc_dev: &drd_dev);
|
|
|
|
if (sim_switches & SWMASK ('P')) { /* power-on reset? */
|
|
drd_ptr = 0; /* clear sector pointer */
|
|
drc_sta = drc_cw = 0; /* clear controller state variables */
|
|
}
|
|
|
|
IOPRESET (dibptr); /* PRESET device (does not use PON) */
|
|
|
|
sim_cancel (&drc_unit);
|
|
sim_cancel (&drd_unit[TMR_ORG]);
|
|
sim_cancel (&drd_unit[TMR_INH]);
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Attach routine */
|
|
|
|
t_stat drc_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
int32 sz = sz_tab[DR_GETSZ (uptr->flags)];
|
|
|
|
if (sz == 0) return SCPE_IERR;
|
|
uptr->capac = sz;
|
|
return attach_unit (uptr, cptr);
|
|
}
|
|
|
|
/* Set protected track count */
|
|
|
|
t_stat dr_set_prot (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
int32 count;
|
|
t_stat status;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
count = (int32) get_uint (cptr, 10, 768, &status);
|
|
if (status != SCPE_OK)
|
|
return status;
|
|
else switch (count) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
case 16:
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
drc_pcount = count;
|
|
break;
|
|
case 256:
|
|
case 512:
|
|
case 768:
|
|
if (drc_unit.flags & UNIT_DRUM)
|
|
drc_pcount = count;
|
|
else return SCPE_ARG;
|
|
break;
|
|
default:
|
|
return SCPE_ARG;
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show protected track count */
|
|
|
|
t_stat dr_show_prot (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
fprintf (st, "protected tracks=%d", drc_pcount);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Set size routine */
|
|
|
|
t_stat dr_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
int32 sz;
|
|
int32 szindex;
|
|
|
|
if (val < 0) return SCPE_IERR;
|
|
if ((sz = sz_tab[szindex = DR_GETSZ (val)]) == 0) return SCPE_IERR;
|
|
if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
|
|
uptr->capac = sz;
|
|
if (szindex & UNIT_DRUM) dr_time = DR_DTIME; /* drum */
|
|
else {
|
|
dr_time = DR_FTIME; /* disk */
|
|
if (drc_pcount > 128) drc_pcount = 128; /* max prot track count */
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
|
|
/* Basic Binary Disc Loader.
|
|
|
|
The Basic Binary Disc Loader (BBDL) contains two programs. The program
|
|
starting at address x7700 loads absolute paper tapes into memory. The
|
|
program starting at address x7760 loads a disc-resident bootstrap from the
|
|
277x fixed-head disc/drum. Entering a BOOT DRC command loads the BBDL into
|
|
memory and executes the disc portion starting at x7760. The bootstrap issues
|
|
a CLC 0,C to clear the disc track and sector address registers and then sets
|
|
up a 64-word read from track 0 sector 0 to memory locations 0-77 octal. It
|
|
then stores a JMP * instruction in location 77, starts the read, and jumps to
|
|
location 77. The JMP * causes the CPU to loop until the last word read from
|
|
the disc overlays location 77 which, typically, would be a JMP instruction to
|
|
the start of the disc-resident bootstrap.
|
|
|
|
In hardware, the BBDL was hand-configured for the disc and paper tape reader
|
|
select codes when it was installed on a given system. Under simulation, we
|
|
treat it as a standard HP 1000 loader, even though it is not structured that
|
|
way, and so the ibl_copy mechanism used to load and configure it must be
|
|
augmented to account for the differences.
|
|
|
|
|
|
Implementaion notes:
|
|
|
|
1. The full BBDL is loaded into memory, even though only the disc portion
|
|
will be used.
|
|
|
|
2. For compatibility with the ibl_copy routine, the loader has been changed
|
|
from the standard HP version. The device I/O instructions are modified
|
|
to address locations 10 and 11.
|
|
*/
|
|
|
|
static const BOOT_ROM dr_rom = {
|
|
0107700, /* ST2 CLC 0,C START OF PAPER TAPE LOADER */
|
|
0002401, /* CLA,RSS */
|
|
0063726, /* CONT2 LDA CM21 */
|
|
0006700, /* CLB,CCE */
|
|
0017742, /* JSB READ2 */
|
|
0007306, /* LEDR2 CMB,CCE,INB,SZB */
|
|
0027713, /* JMP RECL2 */
|
|
0002006, /* EOTC2 INA,SZA */
|
|
0027703, /* JMP CONT2+1 */
|
|
0102077, /* HLT 77B */
|
|
0027700, /* JMP ST2 */
|
|
0077754, /* RECL2 STB CNT2 */
|
|
0017742, /* JSB READ2 */
|
|
0017742, /* JSB READ2 */
|
|
0074000, /* STB A */
|
|
0077757, /* STB ADR11 */
|
|
0067757, /* SUCID LDB ADR11 */
|
|
0047755, /* ADB MAXAD */
|
|
0002040, /* SEZ */
|
|
0027740, /* JMP RESCU */
|
|
0017742, /* LOAD2 JSB READ2 */
|
|
0040001, /* ADA B */
|
|
0177757, /* CM21 STB ADR11,I */
|
|
0037757, /* ISZ ADR11 */
|
|
0000040, /* CLE */
|
|
0037754, /* ISZ CNT2 */
|
|
0027720, /* JMP SUCID */
|
|
0017742, /* JSB READ2 */
|
|
0054000, /* CPB A */
|
|
0027702, /* JMP CONT2 */
|
|
0102011, /* HLT 11B */
|
|
0027700, /* JMP ST2 */
|
|
0102055, /* RESCU HLT 55B */
|
|
0027700, /* JMP ST2 */
|
|
0000000, /* READ2 NOP */
|
|
0006600, /* CLB,CME */
|
|
0103710, /* RED2 STC PR,C */
|
|
0102310, /* SFS PR */
|
|
0027745, /* JMP *-1 */
|
|
0107410, /* MIB PR,C */
|
|
0002041, /* SEZ,RSS */
|
|
0127742, /* JMP READ2,I */
|
|
0005767, /* BLF,CLE,BLF */
|
|
0027744, /* JMP RED2 */
|
|
0000000, /* CNT2 NOP */
|
|
0000000, /* MAXAD NOP */
|
|
0020000, /* CWORD ABS 20000B+DC */
|
|
0000000, /* ADR11 NOP */
|
|
|
|
0107700, /* DLDR CLC 0,C START OF FIXED DISC LOADER */
|
|
0063756, /* LDA CWORD */
|
|
0102606, /* OTA 6 */
|
|
0002700, /* CLA,CCE */
|
|
0102611, /* OTA CC */
|
|
0001500, /* ERA */
|
|
0102602, /* OTA 2 */
|
|
0063777, /* LDA WRDCT */
|
|
0102702, /* STC 2 */
|
|
0102602, /* OTA 2 */
|
|
0103706, /* STC 6,C */
|
|
0102710, /* STC DC */
|
|
0067776, /* LDB JMP77 */
|
|
0074077, /* STB 77B */
|
|
0024077, /* JMP77 JMP 77B */
|
|
0177700 /* WRDCT OCT -100 */
|
|
};
|
|
|
|
#define BBDL_MAX_ADDR 0000055 /* ROM index of the maximum address word */
|
|
#define BBDL_DMA_CNTL 0000056 /* ROM index of the DMA control word */
|
|
#define BBDL_DISC_START 0000060 /* ROM index of the disc loader */
|
|
|
|
t_stat drc_boot (int32 unitno, DEVICE *dptr)
|
|
{
|
|
const int32 dev = drd_dib.select_code; /* data chan select code */
|
|
|
|
if (unitno != 0) /* boot supported on drive unit 0 only */
|
|
return SCPE_NOFNC; /* report "Command not allowed" if attempted */
|
|
|
|
if (ibl_copy (dr_rom, dev, IBL_S_NOCLR, IBL_S_NOSET)) /* copy the boot ROM to memory and configure */
|
|
return SCPE_IERR; /* return an internal error if the copy failed */
|
|
|
|
WritePW (PR + BBDL_MAX_ADDR, ReadPW (PR + IBL_END)); /* move the maximum address word */
|
|
WritePW (PR + BBDL_DMA_CNTL, dr_rom [BBDL_DMA_CNTL] + dev); /* set up the DMA control word */
|
|
|
|
WritePW (PR + IBL_DPC, dr_rom [IBL_DPC]); /* restore the overwritten word */
|
|
WritePW (PR + IBL_END, dr_rom [IBL_END]); /* restore the overwritten word */
|
|
|
|
PR = PR + BBDL_DISC_START; /* select the starting address */
|
|
|
|
return SCPE_OK;
|
|
}
|