190 lines
6.2 KiB
C
190 lines
6.2 KiB
C
/* pdp10_dz_stub.c: DZ11 terminal multiplexor simulator stub
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Copyright (c) 2001, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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dz DZ11 terminal multiplexor (stub)
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This version of the DZ11 is a stub to allow operating systems to play
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with the device registers. It is required for ITS, and not harmful to
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TOPS-10 or TOPS-20.
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*/
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#include "pdp10_defs.h"
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#define DZ_LINES 8 /* lines per DZ11 */
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#define DZ_LMASK (DZ_LINES - 1)
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#define DZ_SILO_ALM 16 /* silo alarm level */
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#define MAXBUF 128 /* buffer size */
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/* DZCSR - 160100 - control/status register */
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#define CSR_MAINT 0000010 /* maint - NI */
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#define CSR_CLR 0000020 /* clear */
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#define CSR_MSE 0000040 /* master scan enb */
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#define CSR_RIE 0000100 /* rcv int enb */
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#define CSR_RDONE 0000200 /* rcv done - RO */
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#define CSR_V_TLINE 8 /* xmit line - RO */
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#define CSR_TLINE (DZ_LMASK << CSR_V_TLINE)
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#define CSR_SAE 0010000 /* silo alm enb */
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#define CSR_SA 0020000 /* silo alm - RO */
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#define CSR_TIE 0040000 /* xmit int enb */
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#define CSR_TRDY 0100000 /* xmit rdy - RO */
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#define CSR_RW (CSR_MSE | CSR_RIE | CSR_SAE | CSR_TIE)
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#define CSR_MBZ (0004003 | CSR_CLR | CSR_MAINT)
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#define CSR_GETTL(x) (((x) >> CSR_V_TLINE) & DZ_LMASK)
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#define CSR_PUTTL(x,y) x = ((x) & ~CSR_TLINE) | (((y) & DZ_LMASK) << CSR_V_TLINE)
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/* DZRBUF - 160102 - receive buffer, read only */
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#define RBUF_CHAR 0000377 /* rcv char */
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#define RBUF_V_RLINE 8 /* rcv line */
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#define RBUF_PARE 0010000 /* parity err - NI */
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#define RBUF_FRME 0020000 /* frame err - NI */
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#define RBUF_OVRE 0040000 /* overrun err - NI */
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#define RBUF_VALID 0100000 /* rcv valid */
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#define RBUF_MBZ 0004000
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/* DZLPR - 160102 - line parameter register, write only, word access only */
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#define LPR_V_LINE 0 /* line */
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#define LPR_LPAR 0007770 /* line pars - NI */
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#define LPR_RCVE 0010000 /* receive enb */
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#define LPR_GETLN(x) (((x) >> LPR_V_LINE) & DZ_LMASK)
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/* DZTCR - 160104 - transmission control register */
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#define TCR_V_XMTE 0 /* xmit enables */
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#define TCR_V_DTR 7 /* DTRs */
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/* DZMSR - 160106 - modem status register, read only */
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#define MSR_V_RI 0 /* ring indicators */
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#define MSR_V_CD 7 /* carrier detect */
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/* DZTDR - 160106 - transmit data, write only */
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#define TDR_CHAR 0000377 /* xmit char */
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#define TDR_V_TBR 7 /* xmit break - NI */
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extern int32 int_req, dev_enb;
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int32 dz_csr = 0; /* csr */
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int32 dz_rbuf = 0; /* rcv buffer */
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int32 dz_lpr = 0; /* line param */
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int32 dz_tcr = 0; /* xmit control */
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int32 dz_msr = 0; /* modem status */
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int32 dz_tdr = 0; /* xmit data */
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int32 dz_mctl = 0; /* modem ctrl enab */
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int32 dz_sa_enb = 1; /* silo alarm enabled */
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t_stat dz_reset (DEVICE *dptr);
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t_stat dz_clear (t_bool flag);
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/* DZ data structures
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dz_dev DZ device descriptor
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dz_unit DZ unit list
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dz_reg DZ register list
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*/
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UNIT dz_unit = { UDATA (NULL, 0, 0) };
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REG dz_reg[] = {
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{ ORDATA (CSR, dz_csr, 16) },
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{ ORDATA (RBUF, dz_rbuf, 16) },
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{ ORDATA (LPR, dz_lpr, 16) },
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{ ORDATA (TCR, dz_tcr, 16) },
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{ ORDATA (MSR, dz_msr, 16) },
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{ ORDATA (TDR, dz_tdr, 16) },
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{ FLDATA (MDMCTL, dz_mctl, 0) },
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{ FLDATA (SAENB, dz_sa_enb, 0) },
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{ FLDATA (*DEVENB, dev_enb, INT_V_DZ0RX), REG_HRO },
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{ NULL } };
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DEVICE dz_dev = {
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"DZ", &dz_unit, dz_reg, NULL,
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1, 8, 13, 1, 8, 8,
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NULL, NULL, &dz_reset,
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NULL, NULL, NULL };
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/* IO dispatch routines, I/O addresses 17760100 - 17760107 */
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t_stat dz0_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 03) { /* case on PA<2:1> */
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case 00: /* CSR */
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*data = dz_csr = dz_csr & ~CSR_MBZ;
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break;
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case 01: /* RBUF */
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dz_csr = dz_csr & ~CSR_SA; /* clr silo alarm */
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*data = dz_rbuf;
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break;
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case 02: /* TCR */
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*data = dz_tcr;
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break;
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case 03: /* MSR */
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*data = dz_msr;
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break; }
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return SCPE_OK;
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}
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t_stat dz0_wr (int32 data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 03) { /* case on PA<2:1> */
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case 00: /* CSR */
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if (access == WRITEB) data = (PA & 1)?
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(dz_csr & 0377) | (data << 8): (dz_csr & ~0377) | data;
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dz_csr = (dz_csr & ~CSR_RW) | (data & CSR_RW);
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break;
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case 01: /* LPR */
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dz_lpr = data;
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break;
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case 02: /* TCR */
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if (access == WRITEB) data = (PA & 1)?
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(dz_tcr & 0377) | (data << 8): (dz_tcr & ~0377) | data;
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dz_tcr = data;
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break;
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case 03: /* TDR */
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if (PA & 1) { /* odd byte? */
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dz_tdr = (dz_tdr & 0377) | (data << 8); /* just save */
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break; }
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dz_tdr = data;
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break; }
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return SCPE_OK;
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}
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/* Device reset */
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t_stat dz_reset (DEVICE *dptr)
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{
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dz_csr = 0; /* clear CSR */
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dz_rbuf = 0; /* silo empty */
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dz_lpr = 0; /* no params */
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dz_tcr = 0; /* clr all */
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dz_tdr = 0;
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dz_sa_enb = 1;
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int_req = int_req & ~(INT_DZ0RX | INT_DZ0TX); /* clear int */
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sim_cancel (&dz_unit); /* no polling */
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return SCPE_OK;
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}
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