331 lines
12 KiB
C
331 lines
12 KiB
C
/*************************************************************************
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* *
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* Copyright (c) 2007-2023 Howard M. Harte. *
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* https://github.com/hharte *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- *
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* INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE *
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN *
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN *
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE *
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* SOFTWARE. *
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* *
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* Except as contained in this notice, the names of The Authors shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* from the Authors. *
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* *
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* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
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* *
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* Module Description: *
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* Vector Graphic, Inc. FlashWriter II module for SIMH *
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* *
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*************************************************************************/
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/*#define DBG_MSG*/
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#include "altairz80_defs.h"
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#ifdef DBG_MSG
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#define DBG_PRINT(args) sim_printf args
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#else
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#define DBG_PRINT(args)
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#endif
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extern int32 sio0s(const int32 port, const int32 io, const int32 data);
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extern int32 sio0d(const int32 port, const int32 io, const int32 data);
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extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
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int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
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static char ansibuf[32];
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#define FW2_MAX_BOARDS 4
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#define UNIT_V_FW2_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
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#define UNIT_FW2_VERBOSE (1 << UNIT_V_FW2_VERBOSE)
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#define FW2_CAPACITY (2048) /* FlashWriter II Memory Size */
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typedef struct {
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UNIT *uptr; /* UNIT pointer */
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uint8 cur_FL_Row; /* Current Flashwriter Row */
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uint8 cur_FL_Col; /* Current Flashwriter Column */
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uint8 FL_Row;
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uint8 FL_Col;
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uint8 reversevideo; /* Flag set if reverse video is currently on */
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uint8 M[FW2_CAPACITY]; /* FlashWriter 2K Video Memory */
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} FW2_INFO;
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static FW2_INFO *fw2_info[FW2_MAX_BOARDS];
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static uint8 port_map[FW2_MAX_BOARDS] = { 0x11, 0x15, 0x17, 0x19 };
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static int32 fw2dev(const int32 Addr, const int32 rw, const int32 data);
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static t_stat fw2_attach(UNIT *uptr, CONST char *cptr);
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static t_stat fw2_detach(UNIT *uptr);
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static uint8 FW2_Read(const uint32 Addr);
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static uint8 FW2_Write(const uint32 Addr, uint8 cData);
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static t_stat get_base_address(const char *cptr, uint32 *baseaddr);
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static const char* fw2_description(DEVICE *dptr);
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static UNIT fw2_unit[] = {
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, FW2_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, FW2_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, FW2_CAPACITY) },
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{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, FW2_CAPACITY) }
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};
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#define FWII_NAME "Vector Graphic Flashwriter 2"
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static const char* fw2_description(DEVICE *dptr) {
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return FWII_NAME;
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}
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static MTAB fw2_mod[] = {
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/* quiet, no warning messages */
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{ UNIT_FW2_VERBOSE, 0, "QUIET", "QUIET", NULL, NULL, NULL,
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"No verbose messages for unit " FWII_NAME "n" },
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/* verbose, show warning messages */
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{ UNIT_FW2_VERBOSE, UNIT_FW2_VERBOSE, "VERBOSE", "VERBOSE", NULL, NULL, NULL,
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"Verbose messages for unit " FWII_NAME "n" },
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{ 0 }
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};
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DEVICE fw2_dev = {
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"FWII", fw2_unit, NULL, fw2_mod,
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FW2_MAX_BOARDS, 10, 31, 1, FW2_MAX_BOARDS, FW2_MAX_BOARDS,
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NULL, NULL, NULL,
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NULL, &fw2_attach, &fw2_detach,
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NULL, (DEV_DISABLE | DEV_DIS), 0,
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NULL, NULL, NULL, NULL, NULL, NULL, &fw2_description
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};
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/* Attach routine */
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static t_stat fw2_attach(UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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unsigned int i = 0;
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uint32 baseaddr;
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char *tptr;
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r = get_base_address(cptr, &baseaddr);
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if(r != SCPE_OK) /* error? */
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return r;
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DBG_PRINT(("%s\n", __FUNCTION__));
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for(i = 0; i < FW2_MAX_BOARDS; i++) {
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if(&fw2_dev.units[i] == uptr) {
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if(uptr->flags & UNIT_FW2_VERBOSE) {
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sim_printf("Attaching unit %d at %04x\n", i, baseaddr);
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}
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break;
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}
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}
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if (i == FW2_MAX_BOARDS) {
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return (SCPE_IERR);
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}
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fw2_info[i] = (FW2_INFO *)calloc(1, sizeof(FW2_INFO));
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if (fw2_info[i] == NULL) {
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return SCPE_MEM;
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}
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fw2_info[i]->uptr = uptr;
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fw2_info[i]->uptr->u3 = baseaddr;
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if(sim_map_resource(baseaddr, FW2_CAPACITY, RESOURCE_TYPE_MEMORY, &fw2dev, "fw2dev", FALSE) != 0) {
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sim_printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, baseaddr);
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return SCPE_ARG;
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}
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if(sim_map_resource(0x00, 1, RESOURCE_TYPE_IO, &sio0s, "sio0s", FALSE) != 0) {
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sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, 0x00);
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return SCPE_ARG;
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}
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if(sim_map_resource(0x01, 1, RESOURCE_TYPE_IO, &sio0d, "sio0d", FALSE) != 0) {
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sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, 0x01);
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return SCPE_ARG;
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}
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tptr = (char *) malloc (strlen (cptr) + 3); /* get string buf */
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if (tptr == NULL)
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return SCPE_MEM; /* no more mem? */
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sprintf(tptr, "0x%04x", baseaddr); /* copy base address */
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uptr->filename = tptr; /* save */
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uptr->flags = uptr->flags | UNIT_ATT;
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return SCPE_OK;
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}
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/* Detach routine */
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static t_stat fw2_detach(UNIT *uptr)
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{
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uint8 i;
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DBG_PRINT(("%s\n", __FUNCTION__));
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for(i = 0; i < FW2_MAX_BOARDS; i++) {
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if(&fw2_dev.units[i] == uptr) {
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break;
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}
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}
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if (i >= FW2_MAX_BOARDS)
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return SCPE_ARG;
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/* Disconnect FlashWriter2: unmap memory and I/O resources */
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sim_map_resource(fw2_info[i]->uptr->u3, FW2_CAPACITY, RESOURCE_TYPE_MEMORY, &fw2dev, "fw2dev", TRUE);
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sim_map_resource(0x00, 1, RESOURCE_TYPE_IO, &sio0s, "sio0s", TRUE);
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sim_map_resource(0x01, 1, RESOURCE_TYPE_IO, &sio0d, "sio0d", TRUE);
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if(fw2_info[i]) {
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free(fw2_info[i]);
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}
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free (uptr->filename); /* free base address string */
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uptr->filename = NULL;
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uptr->flags = uptr->flags & ~UNIT_ATT; /* not attached */
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return SCPE_OK;
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}
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static t_stat get_base_address(const char *cptr, uint32 *baseaddr)
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{
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uint32 b;
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if (sscanf(cptr, "%x", &b) != 1) return SCPE_ARG;
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if(b & (FW2_CAPACITY-1)) {
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sim_printf("FWII must be on a %d-byte boundary.\n", FW2_CAPACITY);
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return SCPE_ARG;
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}
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*baseaddr = b & ~(FW2_CAPACITY-1);
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return SCPE_OK;
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}
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extern int32 getBankSelect(void);
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/* This is the main entry point into the Flashwriter2 emulation. */
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static int32 fw2dev(const int32 Addr, const int32 rw, const int32 data)
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{
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int32 bank = getBankSelect();
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if(bank == 0) {
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if(rw == 0) { /* Read */
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return(FW2_Read(Addr));
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} else { /* Write */
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return(FW2_Write(Addr, data));
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}
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} else
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return 0xff;
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}
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static uint8 FW2_Write(const uint32 Addr, uint8 Value)
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{
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FW2_INFO *fw2 = NULL;
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uint8 FL_Row;
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uint8 FL_Col;
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uint32 baseaddr = 0;
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uint8 i;
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uint8 outchar;
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uint8 port;
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for(i = 0; i < FW2_MAX_BOARDS; i++) {
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if(fw2_info[i] != NULL) {
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baseaddr = fw2_info[i]->uptr->u3;
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if((Addr >= baseaddr) && (Addr < (baseaddr + FW2_CAPACITY))) {
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break;
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}
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}
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}
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if(i == FW2_MAX_BOARDS) {
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return 0;
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}
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fw2 = fw2_info[i];
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port = port_map[i];
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fw2->M[Addr - baseaddr] = Value;
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/* Only print if it is in the visible part of the Flashwriter memory */
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if((Addr >= baseaddr) && (Addr < (baseaddr + (80 * 24)))) {
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FL_Col = ((Addr-baseaddr) % 80) + 1;
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FL_Row = ((Addr-baseaddr) / 80) + 1;
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if(Value & 0x80) { /* reverse video */
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if(fw2->reversevideo == 0) {
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fw2->reversevideo = 1;
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sprintf(ansibuf, "\x1b[07m");
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for(i=0;i<strlen(ansibuf);i++) {
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sio0d(port, 1, ansibuf[i]);
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}
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}
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} else {
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if(fw2->reversevideo == 1) {
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fw2->reversevideo = 0;
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sprintf(ansibuf, "\x1b[00m");
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for(i=0;i<strlen(ansibuf);i++) {
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sio0d(port, 1, ansibuf[i]);
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}
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}
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}
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outchar = Value & 0x7F;
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if(outchar < ' ') {
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outchar = 'O';
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}
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if(outchar == 0x7F) { /* this is supposed to be a square Block character on FW2 */
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outchar = 'X';
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}
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if((fw2->cur_FL_Row == FL_Row) && (FL_Col == fw2->cur_FL_Col + 1)) {
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sio0d(port, 1, outchar);
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} else {
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/* ESC[#;#H */
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sprintf(ansibuf, "\x1b[%d;%dH%c", FL_Row, FL_Col, outchar);
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for(i=0;i<strlen(ansibuf);i++) {
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sio0d(port, 1, ansibuf[i]);
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}
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}
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fw2->cur_FL_Col = FL_Col;
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fw2->cur_FL_Row = FL_Row;
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}
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return(1);
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}
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static uint8 FW2_Read(const uint32 Addr)
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{
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uint32 baseaddr = 0;
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uint8 i;
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for(i = 0; i < FW2_MAX_BOARDS; i++) {
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if(fw2_info[i] != NULL) {
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baseaddr = fw2_info[i]->uptr->u3;
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if((Addr >= baseaddr) && (Addr < (baseaddr + FW2_CAPACITY))) {
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break;
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}
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}
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}
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if(i == FW2_MAX_BOARDS) {
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return 0xFF;
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}
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return(fw2_info[i]->M[Addr - baseaddr]);
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}
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