5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
352 lines
10 KiB
C
352 lines
10 KiB
C
/*
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Work derived from Copyright (c) 2004-2012, Robert M. Supnik
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Copyright (c) 2013 Holger Veit
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the names of Robert M Supnik and Holger Veit
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shall not be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik and Holger Veit.
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20130920 hv initial version, moved some code from pdq3_cpu.c
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*/
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#include "pdq3_defs.h"
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/* the memory */
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uint16 M[MAXMEMSIZE];
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/******************************************************************************
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* IO dispatcher
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*****************************************************************************/
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static t_bool initio = FALSE;
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#define IOSIZE 4096
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#define IOPAGEMASK 0x0fff
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IOREAD ioreaders[IOSIZE];
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IOWRITE iowriters[IOSIZE];
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/* I/O devices are implemented this way:
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* a unit will register its own I/O addresses together with its handler
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* in a hash which allows simple lookup of memory mapped I/O addresses
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*/
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t_stat pdq3_ioinit() {
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int i;
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if (!initio) {
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for (i=0; i < IOSIZE; i++) {
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ioreaders[i] = NULL;
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iowriters[i] = NULL;
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}
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for (i=8; i < 32; i++)
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cpu_setIntVec(NIL, i);
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initio = TRUE;
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}
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return SCPE_OK;
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}
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t_stat add_ioh(IOINFO* ioi) {
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while (ioi) {
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int i;
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for (i=0; i<ioi->iosize; i++) {
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int idx = (ioi->iobase + i) & IOPAGEMASK;
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ioreaders[idx] = ioi->read;
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iowriters[idx] = ioi->write;
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}
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ioi = ioi->next;
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}
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return SCPE_OK;
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}
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t_stat del_ioh(IOINFO* ioi) {
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while (ioi) {
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int i;
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for (i=0; i<ioi->iosize; i++) {
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int idx = (ioi->iobase + i) & IOPAGEMASK;
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ioreaders[idx] = NULL;
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iowriters[idx] = NULL;
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}
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ioi = ioi->next;
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}
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return SCPE_OK;
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}
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/******************************************************************************
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* configuration
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*****************************************************************************/
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t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc) {
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DEVICE* dptr;
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DEVCTXT* ctxt;
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IOINFO* ioi;
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t_bool first = TRUE;
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if (!uptr) return SCPE_IERR;
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if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
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ctxt = (DEVCTXT*)dptr->ctxt;
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ioi = ctxt->ioi;
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while (ioi) {
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if (ioi->iobase) {
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if (ioi->iobase > 0xfc00) {
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fprintf(st, first ? "IOBASE=$%04x":",$%04x", ioi->iobase);
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first = FALSE;
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}
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}
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ioi = ioi->next;
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}
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return SCPE_OK;
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}
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t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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t_stat rc;
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DEVICE* dptr;
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DEVCTXT* ctxt;
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IOINFO* ioi;
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if (!cptr) return SCPE_ARG;
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if (!uptr) return SCPE_IERR;
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if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
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ctxt = (DEVCTXT*)dptr->ctxt;
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ioi = ctxt->ioi;
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if (ioi->next)
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return SCPE_ARG; /* note: fixed devices on mainboard cannot be changed */
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ioi->iobase = get_uint(cptr, 16, 0xffff, &rc);
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return rc;
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}
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t_stat set_iovec(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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t_stat rc;
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DEVICE* dptr;
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DEVCTXT* ctxt;
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IOINFO* ioi;
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if (!cptr) return SCPE_ARG;
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if (!uptr) return SCPE_IERR;
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if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
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ctxt = (DEVCTXT*)dptr->ctxt;
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ioi = ctxt->ioi;
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if (ioi->next)
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return SCPE_ARG; /* note: fixed devices on mainboard cannot be changed */
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ioi->qvector = get_uint(cptr, 16, 0xff, &rc);
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return rc;
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}
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t_stat show_iovec(FILE *st, UNIT *uptr, int value, CONST void *desc) {
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DEVICE* dptr;
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DEVCTXT* ctxt;
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IOINFO* ioi;
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t_bool first = TRUE;
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if (!uptr) return SCPE_IERR;
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if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
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ctxt = (DEVCTXT*)dptr->ctxt;
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ioi = ctxt->ioi;
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while (ioi) {
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if (ioi->qprio < 32) {
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fprintf(st, first ? "VECTOR=$%04x":",$%04x", ioi->qvector);
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first = FALSE;
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}
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ioi = ioi->next;
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}
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return SCPE_OK;
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}
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t_stat set_ioprio(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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t_stat rc;
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DEVICE* dptr;
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DEVCTXT* ctxt;
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IOINFO* ioi;
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if (!cptr) return SCPE_ARG;
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if (!uptr) return SCPE_IERR;
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if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
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ctxt = (DEVCTXT*)dptr->ctxt;
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ioi = ctxt->ioi;
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if (ioi->next)
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return SCPE_ARG; /* note: fixed devices on mainboard cannot be changed */
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ioi->qprio = get_uint(cptr, 16, 31, &rc);
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return rc;
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}
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t_stat show_ioprio(FILE *st, UNIT *uptr, int value, CONST void *desc) {
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DEVICE* dptr;
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DEVCTXT* ctxt;
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IOINFO* ioi;
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t_bool first = TRUE;
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if (!uptr) return SCPE_IERR;
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if ((dptr = find_dev_from_unit(uptr)) == 0) return SCPE_IERR;
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ctxt = (DEVCTXT*)dptr->ctxt;
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ioi = ctxt->ioi;
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while (ioi) {
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if (ioi->qprio < 32) {
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fprintf(st, first ? "PRIO=%d":",%d", ioi->qprio);
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first = FALSE;
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}
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ioi = ioi->next;
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}
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return SCPE_OK;
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}
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/******************************************************************************
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* central memory handling
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*****************************************************************************/
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t_stat Read(t_addr base, t_addr woffset, uint16 *data, uint32 dctrl) {
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t_stat rc;
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uint16 ea = base + woffset;
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/* Note: the PRIAM driver attempts to read the ready bit from FF25 (bit 9) which should be 1.
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* As long as we don't have a HDP device, the invalid value should be 0x0000 */
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*data = 0x0000; /* preload invalid data value */
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if (ea < 0xf000 || (ea == 0xfffe && cpu_unit.capac > 65535)) {
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*data = M[ea]; /* normal memory */
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rc = SCPE_OK;
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} else {
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IOREAD reader = ioreaders[ea & IOPAGEMASK];
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rc = reader ? (*reader)(ea, data) : SCPE_NXM;
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}
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if (rc != SCPE_OK) {
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cpu_buserror();
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sim_debug(DBG_CPU_READ, &cpu_dev, DBG_PCFORMAT1 "Invalid Mem read from $%04x\n", DBG_PC, ea);
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printf("read buserror: ea=$%04x at $%x:#%x\n",ea,reg_segb,reg_ipc);
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return rc;
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}
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if (dctrl & DBG_CPU_PICK) {
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sim_debug(DBG_CPU_PICK, &cpu_dev, DBG_PCFORMAT1 "Pick %04x at SP=$%04x\n", DBG_PC, *data, ea);
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} else if (dctrl & DBG_CPU_POP) {
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sim_debug(DBG_CPU_POP, &cpu_dev, DBG_PCFORMAT2 "Pop %04x from SP=$%04x\n", DBG_PC, *data, ea);
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} else {
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sim_debug(dctrl, &cpu_dev, DBG_PCFORMAT2 "Word read %04x from $%04x\n", DBG_PC, *data, ea);
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}
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return rc;
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}
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/* read routine that does not generate bus errors, for SIMH Examine
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* will read 0x0000 for unknown memory */
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t_stat ReadEx(t_addr base, t_addr woffset, uint16 *data) {
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t_stat rc;
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uint16 ea = base + woffset;
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*data = 0x0000; /* preload invalid data value */
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if (ea < 0xf000) {
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*data = M[ea]; /* normal memory */
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rc = SCPE_OK;
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} else {
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IOREAD reader = ioreaders[ea & IOPAGEMASK];
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rc = reader ? (*reader)(ea, data) : SCPE_NXM;
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}
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return rc;
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}
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t_stat Write(t_addr base, t_addr woffset, uint16 data, uint32 dctrl) {
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t_stat rc;
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uint16 ea = base + woffset;
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if (ea < 0xf000) {
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M[ea] = data;
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rc = SCPE_OK;
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} else {
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IOWRITE write = iowriters[ea & IOPAGEMASK];
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rc = write ? (*write)(ea, data) : SCPE_NXM;
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}
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if (rc != SCPE_OK) {
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cpu_buserror();
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sim_debug(DBG_CPU_WRITE, &cpu_dev, DBG_PCFORMAT0 "Invalid Mem write to $%04x\n", DBG_PC, ea);
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printf("write buserror %x at %x:%x\n",ea,reg_segb,reg_ipc);
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//exit(1);
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return rc;
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}
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if (dctrl & DBG_CPU_STACK)
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sim_debug(DBG_CPU_PUSH, &cpu_dev, DBG_PCFORMAT1 "Push %04x to SP=$%04x\n", DBG_PC, data, ea);
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else
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sim_debug(dctrl, &cpu_dev, DBG_PCFORMAT2 "Word write %04x to $%04x\n", DBG_PC, data, ea);
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return rc;
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}
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t_stat ReadB(t_addr base, t_addr boffset, uint16 *data, uint32 dctrl)
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{
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t_stat rc;
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t_addr ea = base + boffset/2;
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if ((rc=Read(ea, 0, data, DBG_NONE)) != SCPE_OK) return rc;
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if (boffset & 1)
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*data >>= 8;
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*data &= 0xff;
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if (dctrl & DBG_CPU_FETCH)
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sim_debug(DBG_CPU_FETCH, &cpu_dev, DBG_PCFORMAT0 "Fetch %02x from SEGB:%04x\n",
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DBG_PC, *data, reg_ipc);
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else
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sim_debug(dctrl, &cpu_dev, DBG_PCFORMAT2 "Byte[%d] read %02x from $%04x\n",
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DBG_PC, boffset & 1, *data, ea);
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return SCPE_OK;
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}
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t_stat ReadBEx(t_addr base, t_addr boffset, uint16 *data)
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{
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t_stat rc;
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t_addr ea = base + boffset/2;
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if ((rc=ReadEx(ea, 0, data)) != SCPE_OK) return rc;
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if (boffset & 1)
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*data >>= 8;
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*data &= 0xff;
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return SCPE_OK;
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}
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t_stat WriteB(t_addr base, t_addr boffset, uint16 data, uint32 dctrl)
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{
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uint16 wdata;
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t_addr ea = base + boffset/2;
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if (ea < 0xfc00) {
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sim_debug(dctrl, &cpu_dev, DBG_PCFORMAT2 "Byte[%d] write %02x to $%04x\n",
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DBG_PC, boffset & 1, data, ea);
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wdata = M[ea];
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} else {
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printf(DBG_PCFORMAT0 "Invalid byte[%d] write %02x to I/O addr $%04x\n", DBG_PC, boffset & 1, data, ea);
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return STOP_ERRIO;
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}
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if (boffset & 1) {
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wdata = (wdata & 0xff) | (data<<8);
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} else {
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wdata = (wdata & 0xff00) | (data & 0xff);
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}
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return Write(ea, 0, wdata, 0);
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}
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t_stat cpu_set_size (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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int32 mc;
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t_addr i;
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if (val < 0 || val > 1)
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return SCPE_ARG;
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val = val ? 65536 : 32768;
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for (mc = 0, i = val; i < memorysize; i++)
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mc = mc | M[i];
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if (mc && !get_yn ("Really truncate memory [N]?", FALSE))
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return SCPE_OK;
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memorysize = val;
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for (i = memorysize; i < MAXMEMSIZE; i++)
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M[i] = 0;
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return SCPE_OK;
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}
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t_stat rom_read(t_addr ea, uint16 *data)
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{
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*data = M[ea];
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return SCPE_OK;
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}
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t_stat rom_write(t_addr ea, uint16 data) {
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M[ea] = data;
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return SCPE_OK;
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}
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