201 lines
6.7 KiB
C
201 lines
6.7 KiB
C
/* ipc-cont.c: Intel IPC control port PIO adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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07 Jun 16 - Original file.
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NOTES:
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*/
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#include "system_defs.h" /* system header in system dir */
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#define ipc_cont_NAME "Intel IPB/IPC Controller"
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/* function prototypes */
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t_stat ipc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy);
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t_stat ipc_cont_clr(void);
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t_stat ipc_cont_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum); /* ipc_cont*/
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t_stat ipc_cont_reset (DEVICE *dptr);
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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/* globals */
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static const char* ipc_cont_desc(DEVICE *dptr) {
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return ipc_cont_NAME;
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}
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uint8 ipc_cont_baseport = -1; //base port
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UNIT ipc_cont_unit =
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{ UDATA (0, 0, 0) }; /* ipc_cont*/
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REG ipc_cont_reg[] = {
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{ HRDATA (CONTROL0, ipc_cont_unit.u3, 8) }, /* ipc_cont */
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{ NULL }
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};
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DEBTAB ipc_cont_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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MTAB ipc_cont_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, ipc_cont_show_param, NULL,
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"show configured parametes for ipc_cont" },
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE ipc_cont_dev = {
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"IPC-CONT", //name
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&ipc_cont_unit, //units
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ipc_cont_reg, //registers
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ipc_cont_mod, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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NULL, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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ipc_cont_debug, //debflags
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NULL, //msize
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NULL//&ipc_cont_desc //device description
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};
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// ipc_cont configuration
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t_stat ipc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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sim_printf(" ipc-cont: at port 0%02XH\n",
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base & 0xFF);
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ipc_cont_baseport = base & 0xff;
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reg_dev(ipc_cont, base, 0, 0);
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return SCPE_OK;
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}
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t_stat ipc_cont_clr(void)
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{
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unreg_dev(ipc_cont_baseport);
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ipc_cont_baseport = -1;
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return SCPE_OK;
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}
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// show configuration parameters
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t_stat ipc_cont_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "%s, Base port 0%04XH",
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((ipc_cont_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
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ipc_cont_baseport);
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat ipc_cont_reset(DEVICE *dptr)
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{
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ipc_cont_unit.u3 = 0x00; /* ipc reset */
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* IPC control port functions */
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uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port */
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return ipc_cont_unit.u3;
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} else { /* write control port */
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//this simulates an 74LS259 register
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//d0-d2 address the reg(in reverse order!)
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//d3 is the data to be latched (inverted)
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switch(data & 0x07) {
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case 5: //interrupt enable 8085 INTR
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if(data & 0x08) //bit low
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ipc_cont_unit.u3 &= 0xBF;
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else //bit high
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ipc_cont_unit.u3 |= 0x20;
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break;
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case 4: //*selboot ROM @ 0E800h
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if(data & 0x08) //bit low
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ipc_cont_unit.u3 &= 0xEF;
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else //bit high
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ipc_cont_unit.u3 |= 0x10;
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break;
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case 2: //*startup ROM @ 00000h
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if(data & 0x08) //bit low
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ipc_cont_unit.u3 &= 0xFB;
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else //bit high
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ipc_cont_unit.u3 |= 0x04;
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break;
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case 1: //override inhibit other multibus users
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if(data & 0x08) //bit low
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ipc_cont_unit.u3 &= 0xFD;
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else //bit high
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ipc_cont_unit.u3 |= 0x02;
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break;
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case 0: //aux prom enable
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if(data & 0x08) //bit low
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ipc_cont_unit.u3 &= 0xFE;
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else //bit high
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ipc_cont_unit.u3 |= 0x01;
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break;
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default:
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break;
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}
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}
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return 0;
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}
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/* end of ipc-cont.c */
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