764 lines
27 KiB
C
764 lines
27 KiB
C
/* isbc201.c: Intel single density disk adapter adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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31 Oct 16 - Original file.
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NOTES:
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This controller will mount 2 SD disk images on drives :F0: and :F1: addressed
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at ports 088H to 08FH.
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Registers:
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088H - Read - Subsystem status
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bit 0 - ready status of drive 0
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bit 1 - ready status of drive 1
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bit 2 - state of channel's interrupt FF
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bit 3 - controller presence indicator
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bit 4 - zero
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bit 5 - zero
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bit 6 - zero
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bit 7 - zero
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089H - Read - Read result type (bits 2-7 are zero)
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00 - I/O complete with error(unlinked)
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01 - I/O complete with error(linked)(hi 6-bits are block num)
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10 - Result byte contains diskette ready status
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11 - Reserved
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089H - Write - IOPB address low byte.
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08AH - Write - IOPB address high byte and start operation.
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08BH - Read - Read result byte
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If result type is 00H
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bit 0 - deleted record
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bit 1 - CRC error
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bit 2 - seek error
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bit 3 - address error
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bit 4 - data overrun/underrun
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bit 5 - write protect
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bit 6 - write error
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bit 7 - not ready
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If result type is 02H and ready has changed
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bit 0 - zero
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bit 1 - zero
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bit 2 - zero
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bit 3 - zero
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bit 4 - drive 2 ready
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bit 5 - drive 3 ready
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bit 6 - drive 0 ready
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bit 7 - drive 1 ready
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else return 0
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08FH - Write - Reset diskette system.
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Operations:
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NOP - 0x00
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Seek - 0x01
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Format Track - 0x02
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Recalibrate - 0x03
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Read Data - 0x04
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Verify CRC - 0x05
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Write Data - 0x06
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Write Deleted Data - 0x07
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IOPB - I/O Parameter Block
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Byte 0 - Channel Word
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bit 0 - wait
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bit 1 - branch on wait
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bit 2 - successor bit
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bit 3 - data word length (=8-bit, 1=16-bit)
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bit 4-5 - interrupt control
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00 - I/O complete interrupt to be issued
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01 - I/O complete interrupts are disabled
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10 - illegal code
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11 - illegal code
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bit 6 - randon format sequence
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bit 7 - lock override
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Byte 1 - Diskette Instruction
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bit 0-2 - operation code
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000 - no operation
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001 - seek
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010 - format track
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011 - recalibrate
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100 - read data
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101 - verify CRC
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110 - write data
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111 - write deleted data
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bit 3 - data word length ( same as byte-0, bit-3)
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bit 4-5 - unit select
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00 - drive 0
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01 - drive 1
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10 - drive 2
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11 - drive 3
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bit 6-7 - reserved (zero)
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Byte 2 - Number of Records
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Byte 3 - Track Address
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Byte 4 - Sector Address
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Byte 5 - Buffer Low Address
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Byte 7 - Buffer High Address
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Byte 8 - Block Number
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Byte 9 - Next IOPB Lower Address
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Byte 10 - Next IOPB Upper Address
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u3 -
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u4 -
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u5 -
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u6 - fdd number.
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SSSD - Bootable
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This is actually an IBM 3740 format disk. It has 77 tracks of 26 SD
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sectors of 128 bytes each for a total of 2002 sectors. The disk layout
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of the first 6 tracks of the SSSD 256256 byte disk image is as follows:
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File Link Blk Addr Data Blk Addr
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From To
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Trk Sec Trk Sec Trk Sec
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ISIS.T0 000h 018h 000h 001h 000h 017h bin file 0B80 0000 0B00
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ISIS.DIR 001h 001h 001h 002h 001h 01Ah 0D00 0D80 1980
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ISIS.MAP 002h 001h 002h 002h 002h 003h 1A00 1A80 1B00
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ISIS.LAB 000h 019h 000h 01Ah 000h 01Ah 0C00 0C80 0C80
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ISIS.BIN 002h 004h 002h 005h 004h 00Eh pkd file 1B80 1C00 3A80
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004h 00Fh 004h 010h 005h 013h 3B00 3B80 4A00
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ISIS.CLI 005h 014h 005h 015h 006h 00Dh reg file 4A80 4B00 5480
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NEXT BLK 006h 00Eh 5500
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*/
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#include "system_defs.h" /* system header in system dir */
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#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
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#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
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#define FDD_NUM 2
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#define SECSIZ 128
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//disk controoler operations
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#define DNOP 0x00 //disk no operation
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#define DSEEK 0x01 //disk seek
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#define DFMT 0x02 //disk format
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#define DHOME 0x03 //disk home
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#define DREAD 0x04 //disk read
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#define DVCRC 0x05 //disk verify CRC
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#define DWRITE 0x06 //disk write
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//status
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#define RDY0 0x01 //FDD 0 ready
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#define RDY1 0x02 //FDD 1 ready
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#define FDCINT 0x04 //FDC interrupt flag
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#define FDCPRE 0x08 //FDC board present
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//result type
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#define ROK 0x00 //FDC OK OR ERROR
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#define RCHG 0x02 //FDC DISK CHANGED
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// If result type is ROK then rbyte is
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#define RB0DR 0x01 //deleted record
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#define RB0CRC 0x02 //CRC error
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#define RB0SEK 0x04 //seek error
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#define RB0ADR 0x08 //address error
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#define RB0OU 0x10 //data overrun/underrun
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#define RB0WP 0x20 //write protect
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#define RB0WE 0x40 //write error
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#define RB0NR 0x80 //not ready
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// If result type is RCHG then rbyte is
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#define RB1RD0 0x40 //drive 0 ready
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#define RB1RD1 0x80 //drive 1 ready
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//disk geometry values
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#define MDSSD 256256 //single density FDD size
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#define MAXSECSD 26 //single density last sector
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#define MAXTRK 76 //last track
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#define isbc201_NAME "Intel iSBC 201 Floppy Disk Controller Board"
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/* external globals */
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extern uint16 PCX;
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16 port);
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extern uint8 get_mbyte(uint16 addr);
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extern void put_mbyte(uint16 addr, uint8 val);
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/* function prototypes */
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t_stat isbc201_cfg(uint16 baseport, uint16 devnum, uint8 intnum);
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t_stat isbc201_clr(void);
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t_stat isbc201_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc201_set_port (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc201_set_int (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc201_set_verb (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat isbc201_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat isbc201_reset(DEVICE *dptr);
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void isbc201_reset_dev(void);
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t_stat isbc201_attach (UNIT *uptr, CONST char *cptr);
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uint8 isbc201r0(t_bool io, uint8 data, uint8 devnum); /* isbc201 0 */
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uint8 isbc201r1(t_bool io, uint8 data, uint8 devnum); /* isbc201 1 */
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uint8 isbc201r2(t_bool io, uint8 data, uint8 devnum); /* isbc201 2 */
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uint8 isbc201r3(t_bool io, uint8 data, uint8 devnum); /* isbc201 3 */
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uint8 isbc201r7(t_bool io, uint8 data, uint8 devnum); /* isbc201 7 */
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void isbc201_diskio(void); //do actual disk i/o
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/* globals */
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int isbc201_onetime = 1;
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static const char* isbc201_desc(DEVICE *dptr) {
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return isbc201_NAME;
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}
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typedef struct { //FDD definition
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uint8 sec;
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uint8 cyl;
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} FDDDEF;
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typedef struct { //FDC board definition
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uint8 baseport; //FDC base port
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uint8 intnum; //interrupt number
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uint8 verb; //verbose flag
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uint16 iopb; //FDC IOPB
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uint8 stat; //FDC status
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uint8 rdychg; //FDC ready changed
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uint8 rtype; //FDC result type
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uint8 rbyte0; //FDC result byte for type 00
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uint8 rbyte1; //FDC result byte for type 10
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uint8 intff; //FDC interrupt FF
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FDDDEF fdd[FDD_NUM]; //indexed by the FDD number
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} FDCDEF;
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FDCDEF fdc201; //indexed by the isbc-201 instance number
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/* isbc201 Standard I/O Data Structures */
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UNIT isbc201_unit[] = { //2 FDDs
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSSD) },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSSD) }
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};
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REG isbc201_reg[] = {
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{ HRDATA (STAT0, fdc201.stat, 8) }, //fdc201 0 status
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{ HRDATA (RTYP0, fdc201.rtype, 8) }, //fdc201 0 result type
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{ HRDATA (RBYT0A, fdc201.rbyte0, 8) }, //fdc201 0 result byte 0
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{ HRDATA (RBYT0B, fdc201.rbyte1, 8) }, //fdc201 0 result byte 1
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{ HRDATA (INTFF0, fdc201.intff, 8) }, //fdc201 0 interrupt f/f
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{ NULL }
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};
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MTAB isbc201_mod[] = {
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{ UNIT_WPMODE, 0, "RW", "RW", &isbc201_set_mode },
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{ UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &isbc201_set_mode },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "VERB", &isbc201_set_verb,
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NULL, NULL, "Sets the verbose mode for iSBC201"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "PORT", &isbc201_set_port,
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NULL, NULL, "Sets the base port for iSBC201"},
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "INT", &isbc201_set_int,
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NULL, NULL, "Sets the interrupt number for iSBC201"},
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, &isbc201_show_param, NULL,
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"show configured parametes for iSBC201" },
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{ 0 }
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};
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DEBTAB isbc201_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE isbc201_dev = {
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"SBC201", //name
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isbc201_unit, //units
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isbc201_reg, //registers
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isbc201_mod, //modifiers
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FDD_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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isbc201_reset, //reset
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NULL, //boot
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&isbc201_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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0, //dctrl
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isbc201_debug, //debflags
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NULL, //msize
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&isbc201_desc //device description
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};
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// iSBC 201 configuration
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t_stat isbc201_cfg(uint16 baseport, uint16 devnum, uint8 intnum)
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{
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int i;
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UNIT *uptr;
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// one-time initialization for all FDDs for this FDC instance
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for (i = 0; i < FDD_NUM; i++) {
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uptr = isbc201_dev.units + i;
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uptr->u6 = i; //fdd unit number
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uptr->flags &= ~UNIT_ATT;
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}
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fdc201.baseport = baseport & 0xff; //set port
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fdc201.intnum = intnum; //set interrupt
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fdc201.verb = 0; //clear verb
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reg_dev(isbc201r0, fdc201.baseport, 0, 0); //read status
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reg_dev(isbc201r1, fdc201.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
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reg_dev(isbc201r2, fdc201.baseport + 2, 0, 0); //write IOPB addr-h and start
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reg_dev(isbc201r3, fdc201.baseport + 3, 0, 0); //read rstl byte
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reg_dev(isbc201r7, fdc201.baseport + 7, 0, 0); //write reset fdc201
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isbc201_reset_dev(); //software reset
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// if (fdc201.verb)
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sim_printf(" sbc201: Enabled base port at 0%02XH, Interrupt #=%02X, %s\n",
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fdc201.baseport, fdc201.intnum, fdc201.verb ? "Verbose" : "Quiet" );
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return SCPE_OK;
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}
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// iSBC 201 deconfiguration
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t_stat isbc201_clr(void)
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{
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fdc201.intnum = -1; //set default interrupt
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fdc201.verb = 0; //set verb = 0
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unreg_dev(fdc201.baseport); //read status
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unreg_dev(fdc201.baseport + 1); //read rslt type/write IOPB addr-l
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unreg_dev(fdc201.baseport + 2); //write IOPB addr-h and start
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unreg_dev(fdc201.baseport + 3); //read rstl byte
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unreg_dev(fdc201.baseport + 7); //write reset fdc201
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// if (fdc201.verb)
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sim_printf(" sbc201: Disabled\n");
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return SCPE_OK;
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}
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/* fdc201 set mode = Write protect */
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t_stat isbc201_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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if (uptr->flags & UNIT_ATT)
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return sim_messagef (SCPE_ALATT, "%s is already attached to %s\n",
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sim_uname(uptr), uptr->filename);
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if (val & UNIT_WPMODE) { /* write protect */
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uptr->flags |= val;
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if (fdc201.verb)
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sim_printf(" sbc201: WP\n");
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} else { /* read write */
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uptr->flags &= ~val;
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if (fdc201.verb)
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sim_printf(" sbc201: RW\n");
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}
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return SCPE_OK;
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}
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// set base port address parameter
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t_stat isbc201_set_port(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result;
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if (uptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%02x", &size);
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fdc201.baseport = size;
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// if (fdc201.verb)
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sim_printf("SBC201: Installed at base port=%04X\n", fdc201.baseport);
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reg_dev(isbc201r0, fdc201.baseport, 0, 0); //read status
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reg_dev(isbc201r1, fdc201.baseport + 1, 0, 0); //read rslt type/write IOPB addr-l
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reg_dev(isbc201r2, fdc201.baseport + 2, 0, 0); //write IOPB addr-h and start
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reg_dev(isbc201r3, fdc201.baseport + 3, 0, 0); //read rstl byte
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reg_dev(isbc201r7, fdc201.baseport + 7, 0, 0); //write reset fdc201
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return SCPE_OK;
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}
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// set interrupt parameter
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t_stat isbc201_set_int(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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uint32 size, result;
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if (uptr == NULL)
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return SCPE_ARG;
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result = sscanf(cptr, "%02x", &size);
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fdc201.intnum = size;
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// if (fdc201.verb)
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sim_printf("SBC201: Interrupt number=%04X\n", fdc201.intnum);
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return SCPE_OK;
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}
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t_stat isbc201_set_verb(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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if (cptr == NULL)
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return SCPE_ARG;
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if (strncasecmp(cptr, "OFF", 4) == 0) {
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fdc201.verb = 0;
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return SCPE_OK;
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}
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if (strncasecmp(cptr, "ON", 3) == 0) {
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fdc201.verb = 1;
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return SCPE_OK;
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}
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return SCPE_ARG;
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}
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// show configuration parameters
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t_stat isbc201_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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if (uptr == NULL)
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return SCPE_ARG;
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fprintf(st, "%s Base port at %04X Interrupt # is %i %s",
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((isbc201_dev.flags & DEV_DIS) == 0) ? "Enabled" : "Disabled",
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fdc201.baseport, fdc201.intnum,
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fdc201.verb ? "Verbose" : "Quiet"
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);
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return SCPE_OK;
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}
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/* Hardware reset routine */
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t_stat isbc201_reset(DEVICE *dptr)
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{
|
|
if (dptr == NULL)
|
|
return SCPE_ARG;
|
|
isbc201_reset_dev();
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Software reset routine */
|
|
|
|
void isbc201_reset_dev(void)
|
|
{
|
|
int32 i;
|
|
UNIT *uptr;
|
|
|
|
fdc201.stat = 0; //clear status
|
|
for (i = 0; i < FDD_NUM; i++) { /* handle all units */
|
|
uptr = isbc201_dev.units + i;
|
|
fdc201.stat |= FDCPRE; //set the FDC status
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
if (uptr->flags & UNIT_ATT) { /* if attached */
|
|
switch(i){
|
|
case 0:
|
|
fdc201.stat |= RDY0; //set FDD 0 ready
|
|
fdc201.rbyte1 |= RB1RD0;
|
|
break;
|
|
case 1:
|
|
fdc201.stat |= RDY1; //set FDD 1 ready
|
|
fdc201.rbyte1 |= RB1RD1;
|
|
break;
|
|
}
|
|
fdc201.rdychg = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* fdc201 attach - attach an .IMG file to a FDD */
|
|
|
|
t_stat isbc201_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
t_stat r;
|
|
uint8 fddnum;
|
|
|
|
fddnum = uptr->u6;
|
|
if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
|
|
sim_printf(" SBC201_attach: Attach error %d\n", r);
|
|
return r;
|
|
}
|
|
switch(fddnum){
|
|
case 0:
|
|
fdc201.stat |= RDY0; //set FDD 0 ready
|
|
fdc201.rbyte1 |= RB1RD0;
|
|
break;
|
|
case 1:
|
|
fdc201.stat |= RDY1; //set FDD 1 ready
|
|
fdc201.rbyte1 |= RB1RD1;
|
|
break;
|
|
}
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* I/O instruction handlers, called from the CPU module when an
|
|
IN or OUT instruction is issued.
|
|
*/
|
|
|
|
/* ISBC201 control port functions */
|
|
|
|
uint8 isbc201r0(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read status*/
|
|
return fdc201.stat;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc201r1(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
fdc201.intff = 0; //clear interrupt FF
|
|
fdc201.stat &= ~FDCINT;
|
|
fdc201.rtype = ROK;
|
|
return fdc201.rtype;
|
|
} else { /* write data port */
|
|
fdc201.iopb = data;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc201r2(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
fdc201.iopb |= (data << 8);
|
|
isbc201_diskio();
|
|
if (fdc201.intff)
|
|
fdc201.stat |= FDCINT;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc201r3(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
if (fdc201.rtype == ROK) {
|
|
return fdc201.rbyte0;
|
|
} else {
|
|
if (fdc201.rdychg) {
|
|
return fdc201.rbyte1;
|
|
} else {
|
|
return fdc201.rbyte0;
|
|
}
|
|
}
|
|
} else { /* write data port */
|
|
; //stop diskette operation after current linked IOPB finishes
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 isbc201r7(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
isbc201_reset_dev();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
// perform the actual disk I/O operation
|
|
|
|
void isbc201_diskio(void)
|
|
{
|
|
uint8 cw, di, nr, ta, sa, bn, data, nrptr;
|
|
uint16 ba, ni;
|
|
uint32 dskoff;
|
|
uint8 fddnum, fmtb;
|
|
uint32 i;
|
|
UNIT *uptr;
|
|
uint8 *fbuf;
|
|
|
|
//parse the IOPB
|
|
cw = get_mbyte(fdc201.iopb); //Channel Word
|
|
di = get_mbyte(fdc201.iopb + 1); //Diskette Instruction
|
|
nr = get_mbyte(fdc201.iopb + 2); //Number of Records
|
|
ta = get_mbyte(fdc201.iopb + 3); //Track Address
|
|
sa = get_mbyte(fdc201.iopb + 4) & 0x1f; //Sector Address - without bank/fddnum
|
|
ba = get_mbyte(fdc201.iopb + 5);
|
|
ba |= (get_mbyte(fdc201.iopb + 6) << 8); //Buffer Address
|
|
bn = get_mbyte(fdc201.iopb + 7); //Block Number
|
|
ni = get_mbyte(fdc201.iopb + 8);
|
|
ni |= (get_mbyte(fdc201.iopb + 9) << 8); //Next IOPB Address
|
|
fddnum = (di & 0x10) >> 4; //Floppy Disk Number
|
|
uptr = isbc201_dev.units + fddnum; //Unit Pointer
|
|
fbuf = (uint8 *) uptr->filebuf; //File Buffer
|
|
if (fdc201.verb)
|
|
sim_printf("\n SBC201: FDD %d - nr=%02XH ta=%02XH sa=%02XH IOPB=%04XH PCX=%04XH",
|
|
fddnum, nr, ta, sa, fdc201.iopb, PCX);
|
|
//check for not ready
|
|
switch(fddnum) {
|
|
case 0:
|
|
if ((fdc201.stat & RDY0) == 0) {
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = RB0NR;
|
|
fdc201.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC201: FDD %d - Ready error", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 1:
|
|
if ((fdc201.stat & RDY1) == 0) {
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = RB0NR;
|
|
fdc201.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC201: FDD %d - Ready error", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
//check for address error
|
|
if (
|
|
((di & 0x07) != DHOME) && ( //this is not in manual
|
|
(sa > MAXSECSD) ||
|
|
((sa + nr) > (MAXSECSD + 1)) ||
|
|
(sa == 0) ||
|
|
(ta > MAXTRK)
|
|
)) {
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = RB0ADR;
|
|
fdc201.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC201: FDD %d - Address error nr=%02XH ta=%02XH sa=%02XH IOPB=%04XH PCX=%04XH",
|
|
fddnum, nr, ta, sa, fdc201.iopb, PCX);
|
|
return;
|
|
}
|
|
switch (di & 0x07) {
|
|
case DNOP:
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
case DSEEK:
|
|
fdc201.fdd[fddnum].sec = sa;
|
|
fdc201.fdd[fddnum].cyl = ta;
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
case DHOME:
|
|
fdc201.fdd[fddnum].sec = sa;
|
|
fdc201.fdd[fddnum].cyl = 0;
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
case DVCRC:
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0;
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
case DFMT:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = RB0WP;
|
|
fdc201.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC201: FDD %d - Write protect error DFMT", fddnum);
|
|
return;
|
|
}
|
|
fmtb = get_mbyte(ba); //get the format byte
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * MAXSECSD) + (sa - 1)) * SECSIZ;
|
|
for(i=0; i<=((uint32)(MAXSECSD) * SECSIZ); i++) {
|
|
*(fbuf + (dskoff + i)) = fmtb;
|
|
}
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
case DREAD:
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * MAXSECSD) + (sa - 1)) * SECSIZ;
|
|
//copy sector from disk image to RAM
|
|
for (i=0; i<SECSIZ; i++) {
|
|
data = *(fbuf + (dskoff + i));
|
|
put_mbyte(ba + i, data);
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
case DWRITE:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = RB0WP;
|
|
fdc201.intff = 1; //set interrupt FF
|
|
sim_printf("\n SBC201: FDD %d - Write protect error DWRITE", fddnum);
|
|
return;
|
|
}
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
dskoff = ((ta * MAXSECSD) + (sa - 1)) * SECSIZ;
|
|
//copy sector from RAM to disk image
|
|
for (i=0; i<SECSIZ; i++) {
|
|
data = get_mbyte(ba + i);
|
|
*(fbuf + (dskoff + i)) = data;
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
fdc201.rtype = ROK;
|
|
fdc201.rbyte0 = 0; //set no error
|
|
fdc201.intff = 1; //set interrupt FF
|
|
break;
|
|
default:
|
|
sim_printf("\n SBC201: FDD %d - isbc201_diskio bad di=%02X",
|
|
fddnum, di & 0x07);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* end of isbc201.c */
|