9d849283a4
- This change introduces a full refactor of the interrupt subsystem
for the system board (SBD) and the I/O bus (CIO). Interrupt decode
should now be significantly faster, and not require an expensive
calculation on every step.
- The TIMER device has been split into Rev 2 and Rev 3
implementations.
- The optional 3B2/400 Debug Monitor ROMs can now be booted by passing
the "DEMON" argument to the 3B2/400 simulator BOOT command. Any
of the following will cause the Debug Monitor ROM to be booted
instead of the standard 3B2/400 ROM:
sim> BOOT DEMON
sim> BOOT CPU DEMON
sim> BOOT DEMON CPU
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/* 3b2_rev2_stddev.h: 82C54 Interval Timer.
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Copyright (c) 2021, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#ifndef _3B2_REV3_TIMER_H_
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#define _3B2_REV3_TIMER_H_
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#include "3b2_defs.h"
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/* Timer definitions */
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#define TIMER_STP_US 1
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#define tmrnum u3
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#define tmr up7
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#define TIMER_REG_DIVA 0x03
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#define TIMER_REG_DIVB 0x07
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#define TIMER_REG_DIVC 0x0b
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#define TIMER_REG_CTRL 0x0f
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#define TIMER_CLR_LATCH 0x13
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#define TIMER_MODE(ctr) (((ctr->ctrl) >> 1) & 7)
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#define TIMER_RW(ctr) (((ctr->ctrl) >> 4) & 3)
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#define CLK_LATCH 0
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#define CLK_LSB 1
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#define CLK_MSB 2
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#define CLK_LMB 3
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struct timer_ctr {
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uint16 divider;
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uint16 val;
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uint8 ctrl_latch;
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uint16 cnt_latch;
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uint8 ctrl;
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t_bool r_lmb;
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t_bool w_lmb;
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t_bool enabled;
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t_bool r_ctrl_latch;
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t_bool r_cnt_latch;
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};
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/* 82C54 Timer */
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t_stat timer_reset(DEVICE *dptr);
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uint32 timer_read(uint32 pa, size_t size);
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void timer_write(uint32 pa, uint32 val, size_t size);
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t_stat timer0_svc(UNIT *uptr);
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t_stat timer1_svc(UNIT *uptr);
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t_stat timer2_svc(UNIT *uptr);
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/* void timer_tick(uint8 ctrnum); */
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void timer_disable(uint8 ctrnum);
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void timer_enable(uint8 ctrnum);
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#endif /* _3B2_REV3_TIMER_H_ */
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