44cc9f3f6d
Custom TTL design by Marvin Minsky. There are two displays: one raster scan for bitmapped characters, and another random scan for vector graphics. There is also a keyboard, and a UART for talking to a host computer. The computer is normally booted off a ROM which reads and starts a secondary loader from the UART. The loader is responsible for reading the payload, which comes in checksummed blocks. The LOAD command accepts files in same format.
485 lines
12 KiB
C
485 lines
12 KiB
C
/* tt2500_sys.c: TT2500 simulator interface
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Copyright (c) 2020, Lars Brinkhoff
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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LARS BRINKHOFF BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Lars Brinkhoff shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Lars Brinkhoff.
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24-Sep-20 LB New simulator.
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*/
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#include "tt2500_defs.h"
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static uint16 null_read (uint16 reg);
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static void null_write (uint16 reg, uint16 data);
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int32 sim_emax = 1;
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char sim_name[] = "TT2500";
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uint16 CRM[4096];
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uint16 MEM[65536];
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REG *sim_PC = &cpu_reg[0];
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TTDEV *dev_tab[0100];
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static t_addr sym_addr = -1;
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static int sym_immediate = 0;
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static TTDEV null_dev = {
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{ 0, 0, 0, 0 },
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null_read,
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null_write,
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};
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&dpy_dev,
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&crt_dev,
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&tv_dev,
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&key_dev,
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&uart_dev,
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NULL
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};
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const char *sim_stop_messages[SCPE_BASE] = {
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"Unknown error",
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"HALT instruction",
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"Breakpoint",
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"Invalid access",
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};
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static t_stat
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get4 (FILE *fileref, uint16 *x)
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{
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int c = Fgetc (fileref);
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if (c == EOF)
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return SCPE_FMT;
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*x = c & 017;
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return SCPE_OK;
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}
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static t_stat
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get6 (FILE *fileref, uint16 *x)
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{
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int c = Fgetc (fileref);
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if (c == EOF)
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return SCPE_FMT;
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*x = c & 077;
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return SCPE_OK;
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}
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static t_stat
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get8 (FILE *fileref, uint16 *x)
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{
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uint16 y;
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t_stat r;
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r = get4 (fileref, x);
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if (r != SCPE_OK)
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return r;
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r = get4 (fileref, &y);
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if (r != SCPE_OK)
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return r;
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*x = (*x << 4) | y;
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return SCPE_OK;
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}
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static t_stat
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get16 (FILE *fileref, uint16 *x)
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{
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uint16 y;
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t_stat r;
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r = get8 (fileref, x);
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if (r != SCPE_OK)
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return r;
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r = get8 (fileref, &y);
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if (r != SCPE_OK)
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return r;
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*x = (*x << 8) | y;
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return SCPE_OK;
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}
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static uint16 checksum;
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static t_stat
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get18 (FILE *fileref, uint16 *x)
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{
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uint16 y;
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t_stat r;
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r = get6 (fileref, x);
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if (r != SCPE_OK)
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return r;
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r = get6 (fileref, &y);
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if (r != SCPE_OK)
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return r;
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*x = (*x << 6) | y;
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r = get6 (fileref, &y);
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if (r != SCPE_OK)
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return r;
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*x = (*x << 6) | y;
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checksum = (checksum + *x) & 0177777;
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return SCPE_OK;
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}
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static t_stat load_loader (FILE *f, int verbose)
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{
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uint16 i, x, y, count, addr;
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t_stat r;
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x = 0;
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do {
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r = get4 (f, &y);
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if (r != SCPE_OK)
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return r;
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x = ((x << 4) + y) & 0177777;
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} while (x != 0147577);
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/* Read count and address. */
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r = get16 (f, &addr);
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if (r != SCPE_OK)
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return r;
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r = get16 (f, &count);
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if (r != SCPE_OK)
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return r;
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if (verbose)
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fprintf (stderr, "Loader: address %06o, %o words\n", addr, count);
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for (i = 1; i <= count; i++) {
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r = get16 (f, &x);
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if (r != SCPE_OK)
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return r;
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CRM[addr - i] = x;
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}
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return SCPE_OK;
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}
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static t_stat load_block (FILE *f, int verbose)
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{
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uint16 i, x, y, type, count, addr;
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t_stat r;
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x = 0;
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do {
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r = get6 (f, &y);
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if (r != SCPE_OK)
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return r;
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x = ((x << 6) + y) & 0177777;
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} while (x != 0120116);
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checksum = 0;
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/* Read type. */
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r = get18 (f, &type);
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if (r != SCPE_OK)
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return r;
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switch (type) {
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case 0:
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r = get18 (f, &x);
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if (r != SCPE_OK)
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return r;
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if (verbose) {
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t_value val = x;
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fprintf (stderr, "Execute: instruction %06o\n", x);
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fprint_sym (stderr, 0, &val, 0, SWMASK ('M'));
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fputc ('\n', stderr);
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}
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return SCPE_EOF;
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case 1:
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case 2:
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break;
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default:
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return SCPE_FMT;
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}
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r = get18 (f, &addr);
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if (r != SCPE_OK)
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return r;
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r = get18 (f, &count);
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if (r != SCPE_OK)
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return r;
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if (type == 1) {
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if (verbose)
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fprintf (stderr, "Load control store: address %06o, %o words\n",
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addr, count);
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for (i = 0; i < count; i++) {
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r = get18 (f, &x);
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if (r != SCPE_OK)
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return r;
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CRM[(addr++) & 07777] = x;
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}
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} else if (type == 2) {
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if (verbose)
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fprintf (stderr, "Load RAM: address %06o, %o words\n",
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addr, count);
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for (i = 0; i < count; i++) {
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r = get18 (f, &x);
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if (r != SCPE_OK)
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return r;
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if ((addr & 0170000) == 0170000) {
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FONT[(addr++) & 07777] = x & 0377;
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FONT[(addr++) & 07777] = x >> 8;
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i++;
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} else
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MEM[(addr++) & 0177777] = x;
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}
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}
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r = get18 (f, &x);
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if (r != SCPE_OK)
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return r;
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/* Should be 0, but some blocks checksum to 1. */
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if (checksum != 0 && checksum != 1)
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return SCPE_CSUM;
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return SCPE_OK;
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}
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t_stat
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sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
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{
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int verbose = sim_switches & SWMASK ('V');
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t_stat r;
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r = load_loader (fileref, verbose);
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if (r != SCPE_OK)
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return r;
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for (;;) {
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r = load_block (fileref, verbose);
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if (r == SCPE_EOF)
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return SCPE_OK;
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if (r != SCPE_OK)
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return r;
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}
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}
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static uint16 null_read (uint16 reg)
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{
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return 0;
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}
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static void null_write (uint16 reg, uint16 data)
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{
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}
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t_bool build_dev_tab (void)
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{
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TTDEV *ttdev;
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DEVICE *dev;
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int i, j;
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for (i = 0; i < 0100; i++)
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dev_tab[i] = &null_dev;
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for (i = 0; (dev = sim_devices[i]) != NULL; i++) {
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ttdev = (TTDEV *)dev->ctxt;
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if (ttdev != NULL) {
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for (j = 0; j < 4; j++)
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if (ttdev->reg[j] != 0)
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dev_tab[ttdev->reg[j]] = ttdev;
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}
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}
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return SCPE_OK;
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}
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static const char *register_names[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"A-latch", "s11", "s12", "s13", "MAGIC", "CHARTV", "s16", "s17",
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"YCOR", "XCOR", "SCROLL", "XR", "UART", "DSR", "KEY", "d27",
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"d30", "d31", "d32", "d33", "d34", "d35", "d36", "d37",
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"scratch40", "scratch41", "scratch42", "scratch43", "scratch44", "scratch45", "scratch46", "scratch47",
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"scratch50", "scratch51", "scratch52", "scratch53", "scratch54", "scratch55", "scratch56", "scratch57",
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"scratch60", "scratch61", "scratch62", "scratch63", "scratch64", "scratch65", "scratch66", "scratch67",
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"scratch70", "scratch71", "scratch72", "scratch73", "scratch74", "scratch75", "scratch76", "scratch77"
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};
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static t_stat
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fprint_sto (FILE *of, uint16 insn)
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{
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uint16 a = (insn >> 6) & 7;
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uint16 b = insn & 017;
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const char *op;
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switch (insn & 077060) {
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case 020000: op = "READ"; break;
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case 020020: op = "READD"; break;
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case 021000: op = "CREAD"; break;
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case 021020: op = "CREADD"; break;
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case 022040: op = "READI"; break;
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case 023040: op = "CREADI"; break;
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case 024000: op = "WRITE"; break;
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case 024020: op = "WRITED"; break;
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case 025000: op = "CWRITE"; break;
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case 025020: op = "CWRITED"; break;
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case 026040: op = "WRITEI"; break;
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case 027040: op = "CWRITEI"; break;
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case 074000: op = "GET"; break;
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default: fprintf (of, "???"); return SCPE_OK;
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}
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fprintf (of, "%s %s %s", op, register_names[a], register_names[b]);
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return SCPE_OK;
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}
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static t_stat
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fprint_reg (FILE *of, uint16 insn)
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{
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static const char *name[] =
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{ "A", "ANDN", "AND", "NOR", "IOR", "XOR", "MROT", "??",
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"ROT", "DEC", "XADD", "ADD", "SUB", "XSUB", "INC", "ARS" };
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uint16 op = (insn >> 4) & 3;
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uint16 a = (insn >> 6) & 7;
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uint16 b = insn & 017;
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if (insn == 010000) {
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fprintf (of, "NOP");
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return SCPE_OK;
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} else if ((insn & 037060) == 01000) {
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sym_immediate = 1;
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fprintf (of, "LOD %s", register_names[a]);
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return SCPE_OK;
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}
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switch (insn & 030000) {
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case 000000: break;
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case 010000: fprintf (of, "T "); break;
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case 020000: return fprint_sto (of, insn);
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case 030000: fprintf (of, "IFC "); break;
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}
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sym_immediate = insn & 01000;
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op += (insn >> 8) & 014;
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fprintf (of, "%s%s %s %s", name[op], sym_immediate ? "I" : "",
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register_names[a], register_names[b]);
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return SCPE_OK;
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}
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static t_stat
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fprint_dis (FILE *of, uint16 insn)
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{
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fprintf (of, "DIS ");
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switch (insn & 01400) {
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case 00000: fprintf (of, "BUS"); break;
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case 00400: fprintf (of, "FLAGS"); break;
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case 01000: fprintf (of, "INTS"); break;
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case 01400: fprintf (of, "STARS"); break;
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}
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fprintf (of, " %o", (~insn >> 4) & 017);
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return SCPE_OK;
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}
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static t_stat
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fprint_bus (FILE *of, uint16 insn)
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{
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uint16 a = (insn >> 6) & 7;
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uint16 b = insn & 077;
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if ((insn & 076000) == 072000)
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return fprint_dis (of, insn);
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switch (insn) {
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case 0075400: fprintf (of, "MAGIC"); return SCPE_OK;
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case 0076014: fprintf (of, "MAGIC"); return SCPE_OK;
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case 0076015: fprintf (of, "CHARTV"); return SCPE_OK;
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case 0075500: fprintf (of, "CHARTV"); return SCPE_OK;
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case 0075600: fprintf (of, "POPJ"); return SCPE_OK;
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case 0076016: fprintf (of, "POPJ"); return SCPE_OK;
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case 0076716: fprintf (of, "POPJI"); return SCPE_OK;
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}
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fprintf (of, "%s ", insn & 02000 ? "PUT" : "GET");
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fprintf (of, "%s %s", register_names[a], register_names[b]);
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return SCPE_OK;
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}
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static t_stat
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fprint_branch (FILE *of, uint16 insn, uint16 addr)
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{
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static const char *condition[] =
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{ "CC", "CS", "VS", "VC", "MI", "PL", "NE", "EQ",
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"GE", "LT", "IS", "IC", "XCI", "XSI", "FS", "FC" };
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uint16 target = insn & 03777;
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if (insn & 02000)
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target = target - 04000;
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target += addr + 1;
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fprintf (of, "B%s %06o", condition[(insn >> 11) & 017], target);
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return SCPE_OK;
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}
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static t_stat
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fprint_cpu (FILE *of, uint16 insn, uint16 addr)
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{
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switch ((insn >> 12) & 017) {
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case 000: case 001: case 002: case 003:
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return fprint_reg (of, insn);
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case 004:
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fprintf (of, "PUSHJ %04o", insn & 07777);
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break;
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case 005:
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fprintf (of, "JUMP %04o", insn & 07777);
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break;
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case 006:
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fprintf (of, "(undef)");
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break;
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case 007:
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fprint_bus (of, insn);
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break;
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case 010: case 011: case 012: case 013:
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case 014: case 015: case 016: case 017:
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fprint_branch (of, insn, addr);
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break;
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}
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return SCPE_OK;
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}
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw)
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{
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t_stat reason;
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if ((reason = build_dev_tab ()) != SCPE_OK)
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return reason;
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if (sym_addr == addr - 1 && sym_immediate) {
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fprintf (of, "%06o", (unsigned)*val);
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return SCPE_OK;
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}
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sym_addr = addr;
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sym_immediate = 0;
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if (sw & SWMASK ('M'))
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return fprint_cpu (of, *val, addr);
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return SCPE_ARG;
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}
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t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr,
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t_value *val, int32 sw)
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{
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t_stat reason;
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*val = get_uint (cptr, 8, ~0, &reason);
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if (reason != SCPE_OK)
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return reason;
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return 0;
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}
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