99b4730dc0
PDP11/pdp11_io_lib.c: In function 'show_iospace': PDP11/pdp11_io_lib.c:363: warning: too few arguments for format PDP10/pdp10_lp20.c: In function 'lp20_set_vfu_type': PDP10/pdp10_lp20.c:1038: warning: implicit declaration of function 'toupper' PDP10/pdp10_lp20.c:1121: warning: implicit declaration of function 'isspace'
798 lines
32 KiB
C
798 lines
32 KiB
C
/* pdp11_io_lib.c: Unibus/Qbus common support routines
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Copyright (c) 1993-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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*/
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#if defined (VM_PDP10) /* PDP10 version */
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#include "pdp10_defs.h"
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#elif defined (VM_VAX) /* VAX version */
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#include "vax_defs.h"
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#else /* PDP-11 version */
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#include "pdp11_defs.h"
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#endif
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#include "sim_ether.h"
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extern int32 autcon_enb;
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extern int32 int_vec[IPL_HLVL][32];
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extern int32 (*int_ack[IPL_HLVL][32])(void);
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extern t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
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extern t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
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extern t_stat build_dib_tab (void);
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static DIB *iodibp[IOPAGESIZE >> 1];
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#define AUTO_MAXC 32 /* Maximum number of controllers */
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#define AUTO_CSRBASE 0010
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#define AUTO_CSRMAX 04000
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#define AUTO_VECBASE 0300
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/* Enable/disable autoconfiguration */
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t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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if (cptr != NULL)
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return SCPE_ARG;
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autcon_enb = val;
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return auto_config (NULL, 0);
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}
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/* Show autoconfiguration status */
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t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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fprintf (st, "autoconfiguration ");
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fprintf (st, autcon_enb? "enabled": "disabled");
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return SCPE_OK;
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}
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/* Change device address */
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t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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DEVICE *dptr;
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DIB *dibp;
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uint32 newba;
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t_stat r;
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if (cptr == NULL)
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return SCPE_ARG;
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if ((val == 0) || (uptr == NULL))
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return SCPE_IERR;
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dptr = find_dev_from_unit (uptr);
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if (dptr == NULL)
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return SCPE_IERR;
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dibp = (DIB *) dptr->ctxt;
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if (dibp == NULL)
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return SCPE_IERR;
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newba = (uint32) get_uint (cptr, DEV_RDX, IOPAGEBASE+IOPAGEMASK, &r); /* get new */
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if (r != SCPE_OK)
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return r;
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if ((newba <= IOPAGEBASE) || /* > IO page base? */
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(newba % ((uint32) val))) /* check modulus */
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return SCPE_ARG;
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dibp->ba = newba; /* store */
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autcon_enb = 0; /* autoconfig off */
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return SCPE_OK;
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}
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/* Show device address */
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t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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DEVICE *dptr;
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DIB *dibp;
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if (uptr == NULL)
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return SCPE_IERR;
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dptr = find_dev_from_unit (uptr);
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if (dptr == NULL)
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return SCPE_IERR;
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dibp = (DIB *) dptr->ctxt;
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if ((dibp == NULL) || (dibp->ba <= IOPAGEBASE))
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return SCPE_IERR;
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fprintf (st, "address=");
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fprint_val (st, (t_value) dibp->ba, DEV_RDX, 32, PV_LEFT);
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if (dibp->lnt > 1) {
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fprintf (st, "-");
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fprint_val (st, (t_value) dibp->ba + dibp->lnt - 1, DEV_RDX, 32, PV_LEFT);
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}
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if (dibp->ba < IOPAGEBASE + AUTO_CSRBASE + AUTO_CSRMAX)
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fprintf (st, "*");
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return SCPE_OK;
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}
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/* Set address floating */
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t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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DEVICE *dptr;
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if (cptr != NULL)
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return SCPE_ARG;
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if (uptr == NULL)
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return SCPE_IERR;
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dptr = find_dev_from_unit (uptr);
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if (dptr == NULL)
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return SCPE_IERR;
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return auto_config (NULL, 0); /* autoconfigure */
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}
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/* Change device vector */
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t_stat set_vec (UNIT *uptr, int32 arg, char *cptr, void *desc)
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{
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DEVICE *dptr;
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DIB *dibp;
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uint32 newvec;
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t_stat r;
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if (cptr == NULL)
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return SCPE_ARG;
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if (uptr == NULL)
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return SCPE_IERR;
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dptr = find_dev_from_unit (uptr);
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if (dptr == NULL)
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return SCPE_IERR;
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dibp = (DIB *) dptr->ctxt;
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if (dibp == NULL)
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return SCPE_IERR;
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newvec = (uint32) get_uint (cptr, DEV_RDX, VEC_Q + 01000, &r);
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if ((r != SCPE_OK) || (newvec == VEC_Q) ||
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((newvec + (dibp->vnum * 4)) >= (VEC_Q + 01000)) ||
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(newvec & ((dibp->vnum > 1)? 07: 03)))
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return SCPE_ARG;
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dibp->vec = newvec;
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autcon_enb = 0; /* autoconfig off */
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return SCPE_OK;
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}
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/* Show device vector */
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t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc)
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{
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DEVICE *dptr;
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DIB *dibp;
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uint32 vec, numvec;
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if (uptr == NULL)
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return SCPE_IERR;
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dptr = find_dev_from_unit (uptr);
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if (dptr == NULL)
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return SCPE_IERR;
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dibp = (DIB *) dptr->ctxt;
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if (dibp == NULL)
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return SCPE_IERR;
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vec = dibp->vec;
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if (arg)
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numvec = arg;
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else numvec = dibp->vnum;
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if (vec == 0)
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fprintf (st, "no vector");
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else {
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fprintf (st, "vector=");
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fprint_val (st, (t_value) vec, DEV_RDX, 16, PV_LEFT);
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if (numvec > 1) {
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fprintf (st, "-");
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fprint_val (st, (t_value) vec + (4 * (numvec - 1)), DEV_RDX, 16, PV_LEFT);
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}
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}
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if (vec >= VEC_Q + AUTO_VECBASE)
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fprintf (st, "*");
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return SCPE_OK;
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}
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/* Show vector for terminal multiplexor */
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t_stat show_vec_mux (FILE *st, UNIT *uptr, int32 arg, void *desc)
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{
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TMXR *mp = (TMXR *) desc;
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if ((mp == NULL) || (arg == 0))
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return SCPE_IERR;
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return show_vec (st, uptr, ((mp->lines * 2) / arg), desc);
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}
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/* Init Unibus tables */
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void init_ubus_tab (void)
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{
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size_t i, j;
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for (i = 0; i < IPL_HLVL; i++) { /* clear intr tab */
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for (j = 0; j < 32; j++) {
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int_vec[i][j] = 0;
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int_ack[i][j] = NULL;
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}
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}
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for (i = 0; i < (IOPAGESIZE >> 1); i++) { /* clear dispatch tab */
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iodispR[i] = NULL;
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iodispW[i] = NULL;
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iodibp[i] = NULL;
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}
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return;
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}
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/* Build Unibus tables */
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t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp)
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{
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int32 i, idx, vec, ilvl, ibit;
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if ((dptr == NULL) || (dibp == NULL)) /* validate args */
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return SCPE_IERR;
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if (dibp->vnum > VEC_DEVMAX)
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return SCPE_IERR;
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for (i = 0; i < dibp->vnum; i++) { /* loop thru vec */
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idx = dibp->vloc + i; /* vector index */
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vec = dibp->vec? (dibp->vec + (i * 4)): 0; /* vector addr */
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ilvl = idx / 32;
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ibit = idx % 32;
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if ((int_ack[ilvl][ibit] && dibp->ack[i] && /* conflict? */
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(int_ack[ilvl][ibit] != dibp->ack[i])) ||
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(int_vec[ilvl][ibit] && vec &&
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(int_vec[ilvl][ibit] != vec))) {
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printf ("Device %s interrupt slot conflict at %d\n",
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sim_dname (dptr), idx);
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if (sim_log)
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fprintf (sim_log, "Device %s interrupt slot conflict at %d\n",
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sim_dname (dptr), idx);
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return SCPE_STOP;
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}
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if (dibp->ack[i])
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int_ack[ilvl][ibit] = dibp->ack[i];
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else if (vec)
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int_vec[ilvl][ibit] = vec;
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}
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for (i = 0; i < (int32) dibp->lnt; i = i + 2) { /* create entries */
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idx = ((dibp->ba + i) & IOPAGEMASK) >> 1; /* index into disp */
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if ((iodispR[idx] && dibp->rd && /* conflict? */
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(iodispR[idx] != dibp->rd)) ||
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(iodispW[idx] && dibp->wr &&
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(iodispW[idx] != dibp->wr))) {
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printf ("Device %s address conflict at \n", sim_dname (dptr));
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fprint_val (stdout, (t_value) dibp->ba, DEV_RDX, 32, PV_LEFT);
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if (sim_log) {
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fprintf (sim_log, "Device %s address conflict at \n", sim_dname (dptr));
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fprint_val (sim_log, (t_value) dibp->ba, DEV_RDX, 32, PV_LEFT);
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}
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return SCPE_STOP;
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}
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if (dibp->rd) /* set rd dispatch */
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iodispR[idx] = dibp->rd;
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if (dibp->wr) /* set wr dispatch */
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iodispW[idx] = dibp->wr;
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iodibp[idx] = dibp; /* remember DIB */
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}
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return SCPE_OK;
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}
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/* Show IO space */
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t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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uint32 i, j;
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DEVICE *dptr;
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DIB *dibp;
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uint32 maxaddr, maxname, maxdev;
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int32 maxvec, vecwid;
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char valbuf[40];
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if (build_dib_tab ()) /* build IO page */
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return SCPE_OK;
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maxaddr = 0;
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maxvec = 0;
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maxname = 0;
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maxdev = 1;
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for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) { /* loop thru entries */
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size_t l;
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if (iodibp[i] && (iodibp[i] != dibp)) { /* new block? */
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dibp = iodibp[i]; /* DIB for block */
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for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
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if (((DIB*) sim_devices[j]->ctxt) == dibp) {
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dptr = sim_devices[j]; /* locate device */
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break;
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} /* end if */
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} /* end for j */
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if ((dibp->ba+ dibp->lnt - 1) > maxaddr)
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maxaddr = dibp->ba+ dibp->lnt - 1;
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if (dibp->vec > maxvec)
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maxvec = dibp->vec;
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l = strlen (dptr? sim_dname (dptr): "CPU");
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if (l>maxname)
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maxname = (int32)l;
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j = (dibp->ulnt? dibp->lnt/dibp->ulnt:
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(dptr? dptr->numunits: 1));
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if (j > maxdev)
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maxdev = j;
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} /* end if */
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} /* end for i */
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maxaddr = fprint_val (NULL, (t_value) dibp->ba, DEV_RDX, 32, PV_LEFT);
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sprintf (valbuf, "%03o", maxvec);
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vecwid = maxvec = (int32) strlen (valbuf);
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if (vecwid < 3)
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vecwid = 3;
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sprintf (valbuf, "%u", maxdev);
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maxdev = (uint32)strlen (valbuf);
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j = strlen ("Address");
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i = (maxaddr*2)+3+1;
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if (i <= j)
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i = 0;
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else
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i -= j;
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maxaddr = i+j;
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fprintf (st, "%*.*sAddress%*.*s", i/2, i/2, " ", (i/2)+i%2, (i/2)+i%2, " ");
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j = strlen ("Vector");
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i = ((maxvec*2)+1+1);
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if (i <= j)
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i = 0;
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else
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i -= j;
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maxvec = i+j;
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fprintf (st, " %*.*sVector%*.*s", i/2, i/2, " ", (i/2)+i%2, (i/2)+i%2, " ");
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fprintf (st, " BR %*.*s# Device\n", (maxdev -1), (maxdev-1), " ");
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for (i = 0; i < maxaddr; i++)
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fputc ('-', st);
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fprintf (st, " ");
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for (i = 0; i < (uint32)maxvec; i++)
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fputc ('-', st);
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fprintf (st, " -- ");
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for (i=0; i < maxdev; i++) {
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fputc ('-', st);
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}
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fputc (' ', st);
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i = strlen ("Device");
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if (maxname < i)
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maxname = i;
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for (i = 0; i < maxname; i++)
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fputc ('-', st);
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fputc ('\n', st);
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for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) { /* loop thru entries */
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if (iodibp[i] && (iodibp[i] != dibp)) { /* new block? */
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dibp = iodibp[i]; /* DIB for block */
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for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
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if (((DIB*) sim_devices[j]->ctxt) == dibp) {
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dptr = sim_devices[j]; /* locate device */
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break;
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} /* end if */
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} /* end for j */
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fprint_val (st, (t_value) dibp->ba, DEV_RDX, 32, PV_LEFT);
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fprintf (st, " - ");
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fprint_val (st, (t_value) dibp->ba + dibp->lnt - 1, DEV_RDX, 32, PV_LEFT);
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fprintf (st, "%c ", /* print block entry */
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(dibp->ba < IOPAGEBASE + AUTO_CSRBASE + AUTO_CSRMAX)? '*': ' ');
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if (dibp->vec == 0)
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fprintf (st, "%*s", ((vecwid*2)+1+1), " ");
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else {
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fprintf (st, "%0*o", vecwid, dibp->vec);
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if (dibp->vnum > 1)
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fprintf (st, "-%0*o", vecwid, dibp->vec + (4 * (dibp->vnum - 1)));
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else
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fprintf (st, " %*s", vecwid, " ");
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fprintf (st, "%1s", (dibp->vnum >= AUTO_VECBASE)? "*": " ");
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}
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if (dibp->vnum || dibp->vloc)
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fprintf (st, " %2u", dibp->vloc/32);
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else
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fprintf (st, " ");
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fprintf (st, " %*u %s\n", maxdev, (dibp->ulnt? dibp->lnt/dibp->ulnt:
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(dptr? dptr->numunits: 1)),
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dptr? sim_dname (dptr): "CPU");
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} /* end if */
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} /* end for i */
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return SCPE_OK;
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}
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/* Autoconfiguration
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The table reflects the MicroVAX 3900 microcode, with one field addition - the
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number of controllers field handles devices where multiple instances
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are simulated through a single DEVICE structure (e.g., DZ, VH, DL, DC).
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The table has been reviewed, extended and updated to reflect the contents of
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the auto configure table in VMS sysgen (V5.5-2)
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A minus number of vectors indicates a field that should be calculated
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but not placed in the DIB (RQ, TQ dynamic vectors)
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An amod value of 0 indicates that all addresses are FIXED
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An vmod value of 0 indicates that all vectors are FIXED */
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typedef struct {
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char *dnam[AUTO_MAXC];
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int32 numc;
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int32 numv;
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uint32 amod;
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uint32 vmod;
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uint32 fixa[AUTO_MAXC];
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uint32 fixv[AUTO_MAXC];
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} AUTO_CON;
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AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */
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{ { "QBA" }, 1, 0, 0, 0,
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{017500} }, /* doorbell - fx CSR, no VEC */
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{ { "MCTL" }, 1, 0, 0, 0,
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{012100} }, /* MSV11-P/MSV11-Q - fx CSR, no VEC */
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{ { "KE" }, 1, 0, 0, 0,
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{017300} }, /* KE11-A - fx CSR, no VEC */
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{ { "KG" }, 1, 0, 0, 0,
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{010700} }, /* KG11-A - fx CSR, no VEC */
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{ { "RHA", "RHB", "RHC" }, 1, 1, 0, 0,
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{016700, 012440, 012040}, {0254, 0224, 0204} }, /* RH11/RH70 - fx CSR, fx VEC */
|
|
{ { "CLK" }, 1, 1, 0, 0,
|
|
{017546}, {0100} }, /* KW11L - fx CSR, fx VEC */
|
|
{ { "PCLK" }, 1, 1, 0, 0,
|
|
{012540}, {0104} }, /* KW11P - fx CSR, fx VEC */
|
|
{ { "PTR" }, 1, 1, 0, 0,
|
|
{017550}, {0070} }, /* PC11 reader - fx CSR, fx VEC */
|
|
{ { "PTP" }, 1, 1, 0, 0,
|
|
{017554}, {0074} }, /* PC11 punch - fx CSR, fx VEC */
|
|
{ { "RK" }, 1, 1, 0, 0,
|
|
{017400}, {0220} }, /* RK11 - fx CSR, fx VEC */
|
|
{ { "TM" }, 1, 1, 0, 0,
|
|
{012520}, {0224} }, /* TM11 - fx CSR, fx VEC */
|
|
{ { "RC" }, 1, 1, 0, 0,
|
|
{017440}, {0210} }, /* RC11 - fx CSR, fx VEC */
|
|
{ { "RF" }, 1, 1, 0, 0,
|
|
{017460}, {0204} }, /* RF11 - fx CSR, fx VEC */
|
|
{ { "CR" }, 1, 1, 0, 0,
|
|
{017160}, {0230} }, /* CR11 - fx CSR, fx VEC */
|
|
{ { "HK" }, 1, 1, 0, 0,
|
|
{017440}, {0210} }, /* RK611 - fx CSR, fx VEC */
|
|
{ { "LPT" }, 1, 1, 0, 0,
|
|
{017514, 004004, 004014, 004024, 004034},
|
|
{0200, 0170, 0174, 0270, 0274} }, /* LP11 - fx CSR, fx VEC */
|
|
{ { "RB" }, 1, 1, 0, 0,
|
|
{015606}, {0250} }, /* RB730 - fx CSR, fx VEC */
|
|
{ { "RL" }, 1, 1, 0, 0,
|
|
{014400}, {0160} }, /* RL11 - fx CSR, fx VEC */
|
|
{ { "RL" }, 1, 1, 0, 0,
|
|
{014400}, {0160} }, /* RL11 - fx CSR, fx VEC */
|
|
{ { "DCI" }, 1, 2, 0, 8,
|
|
{014000, 014010, 014020, 014030,
|
|
014040, 014050, 014060, 014070,
|
|
014100, 014110, 014120, 014130,
|
|
014140, 014150, 014160, 014170,
|
|
014200, 014210, 014220, 014230,
|
|
014240, 014250, 014260, 014270,
|
|
014300, 014310, 014320, 014330,
|
|
014340, 014350, 014360, 014370} }, /* DC11 - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{016500, 016510, 016520, 016530,
|
|
016540, 016550, 016560, 016570,
|
|
016600, 016610, 016620, 016630,
|
|
016640, 016650, 016660, 016670} }, /* TU58 - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 4,
|
|
{015200, 015210, 015220, 015230,
|
|
015240, 015250, 015260, 015270,
|
|
015300, 015310, 015320, 015330,
|
|
015340, 015350, 015360, 015370} }, /* DN11 - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 4,
|
|
{010500, 010510, 010520, 010530,
|
|
010540, 010550, 010560, 010570,
|
|
010600, 010610, 010620, 010630,
|
|
010640, 010650, 010660, 010670} }, /* DM11B - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{007600, 007570, 007560, 007550,
|
|
007540, 007530, 007520, 007510,
|
|
007500, 007470, 007460, 007450,
|
|
007440, 007430, 007420, 007410} }, /* DR11C - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 8,
|
|
{012600, 012604, 012610, 012614,
|
|
012620, 012624, 012620, 012624} }, /* PR611 - fx CSRs */
|
|
{ { NULL }, 1, 1, 0, 8,
|
|
{017420, 017422, 017424, 017426,
|
|
017430, 017432, 017434, 017436} }, /* DT11 - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{016200, 016240} }, /* DX11 */
|
|
{ { "DLI" }, 1, 2, 0, 8,
|
|
{016500, 016510, 016520, 016530,
|
|
016540, 016550, 016560, 016570,
|
|
016600, 016610, 016620, 016630,
|
|
016740, 016750, 016760, 016770} }, /* KL11/DL11/DLV11 - fx CSRs */
|
|
{ { NULL }, 1, 2, 0, 8, { 0 } }, /* DLV11J - fx CSRs */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DJ11 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* DH11 */
|
|
{ { NULL }, 1, 4, 0, 8,
|
|
{012000, 012010, 012020, 012030} }, /* GT40 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{010400} }, /* LPS11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DQ11 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{012400} }, /* KW11W */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DU11 */
|
|
{ { "DUP" }, 1, 2, 8, 8 }, /* DUP11 */
|
|
{ { NULL }, 1, 3, 0, 8,
|
|
{015000, 015040, 015100, 015140, }}, /* DV11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* LK11A */
|
|
{ { "DMC0", "DMC1", "DMC2", "DMC3" },
|
|
1, 2, 8, 8 }, /* DMC11 */
|
|
{ { "DZ" }, 1, 2, 8, 8 }, /* DZ11 */
|
|
{ { "KMC" }, 1, 2, 8, 8 }, /* KMC11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* LPP11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* VMV21 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* VMV31 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DWR70 */
|
|
{ { "RL", "RLB"}, 1, 1, 8, 4,
|
|
{014400}, {0160} }, /* RL11 */
|
|
{ { "TS", "TSB", "TSC", "TSD"},
|
|
1, 1, 0, 4, /* TS11 */
|
|
{012520, 012524, 012530, 012534},
|
|
{0224} },
|
|
{ { NULL }, 1, 2, 16, 8,
|
|
{010460} }, /* LPA11K */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* KW11C */
|
|
{ { NULL }, 1, 1, 8, 8 }, /* reserved */
|
|
{ { "RX", "RY" }, 1, 1, 8, 4,
|
|
{017170} , {0264} }, /* RX11/RX211 */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* DR11W */
|
|
{ { NULL }, 1, 1, 8, 4,
|
|
{012410, 012410}, {0124} }, /* DR11B - fx CSRs,vec */
|
|
{ { "DMP" }, 1, 2, 8, 8 }, /* DMP11 */
|
|
{ { "DPV" }, 1, 2, 8, 8 }, /* DPV11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* ISB11 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* DMV11 */
|
|
{ { "XU", "XUB" }, 1, 1, 8, 4,
|
|
{014510}, {0120} }, /* DEUNA */
|
|
{ { "XQ", "XQB" }, 1, -1, 0, 4,
|
|
{014440, 014460, 014520, 014540}, {0120} }, /* DEQNA */
|
|
{ { "RQ", "RQB", "RQC", "RQD" },
|
|
1, -1, 4, 4, /* RQDX3 */
|
|
{012150}, {0154} },
|
|
{ { NULL }, 1, 8, 32, 4 }, /* DMF32 */
|
|
{ { NULL }, 1, 3, 16, 8 }, /* KMS11 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{004200, 004240, 004300, 004340} }, /* PLC11 */
|
|
{ { NULL }, 1, 1, 16, 4 }, /* VS100 */
|
|
{ { "TQ", "TQB" }, 1, -1, 4, 4,
|
|
{014500}, {0260} }, /* TQK50 */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* KMV11 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{004400, 004440, 004500, 004540} }, /* KTC32 */
|
|
{ { NULL }, 1, 2, 0, 8,
|
|
{004100} }, /* IEQ11 */
|
|
{ { "VH" }, 1, 2, 16, 8 }, /* DHU11/DHQ11 */
|
|
{ { NULL }, 1, 6, 32, 4 }, /* DMZ32 */
|
|
{ { NULL }, 1, 6, 32, 4 }, /* CP132 */
|
|
{ { "TC" }, 1, 1, 0, 0,
|
|
{017340}, {0214} }, /* TC11 */
|
|
{ { "TA" }, 1, 1, 0, 0,
|
|
{017500}, {0260} }, /* TA11 */
|
|
{ { "QVSS" }, 1, 2, 64, 8,
|
|
{017200} }, /* QVSS - fx CSR */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* VS31 */
|
|
{ { NULL }, 1, 1, 0, 4,
|
|
{016200} }, /* LNV11 - fx CSR */
|
|
{ { NULL }, 1, 1, 16, 4 }, /* LNV21/QPSS */
|
|
{ { NULL }, 1, 1, 8, 4,
|
|
{012570} }, /* QTA - fx CSR */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* DSV11 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* CSAM */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* ADV11C */
|
|
{ { NULL }, 1, 0, 8, 8,
|
|
{010440} }, /* AAV11/AAV11C */
|
|
{ { NULL }, 1, 2, 8, 8,
|
|
{016400}, {0140} }, /* AXV11C - fx CSR,vec */
|
|
{ { NULL }, 1, 2, 4, 8,
|
|
{010420} }, /* KWV11C - fx CSR */
|
|
{ { NULL }, 1, 2, 8, 8,
|
|
{016410} }, /* ADV11D - fx CSR */
|
|
{ { NULL }, 1, 2, 8, 8,
|
|
{016420} }, /* AAV11D - fx CSR */
|
|
{ { "QDSS" }, 1, 3, 0, 16,
|
|
{017400, 017402, 017404, 017406,
|
|
017410, 017412, 017414, 017416} }, /* VCB02 - QDSS - fx CSR */
|
|
{ { NULL }, 1, 16, 0, 4,
|
|
{004160, 004140, 004120} }, /* DRV11J - fx CSR */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* DRQ3B */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* VSV24 */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* VSV21 */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* IBQ01 */
|
|
{ { NULL }, 1, 1, 8, 8 }, /* IDV11A */
|
|
{ { NULL }, 1, 0, 8, 8 }, /* IDV11B */
|
|
{ { NULL }, 1, 0, 8, 8 }, /* IDV11C */
|
|
{ { NULL }, 1, 1, 8, 8 }, /* IDV11D */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* IAV11A */
|
|
{ { NULL }, 1, 0, 8, 8 }, /* IAV11B */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* MIRA */
|
|
{ { NULL }, 1, 2, 16, 8 }, /* IEQ11 */
|
|
{ { NULL }, 1, 2, 32, 8 }, /* ADQ32 */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* DTC04, DECvoice */
|
|
{ { NULL }, 1, 1, 32, 4 }, /* DESNA */
|
|
{ { NULL }, 1, 2, 4, 8 }, /* IGQ11 */
|
|
{ { NULL }, 1, 2, 32, 8 }, /* KMV1F */
|
|
{ { NULL }, 1, 1, 8, 4 }, /* DIV32 */
|
|
{ { NULL }, 1, 2, 4, 8 }, /* DTCN5, DECvoice */
|
|
{ { NULL }, 1, 2, 4, 8 }, /* DTC05, DECvoice */
|
|
{ { NULL }, 1, 2, 8, 8 }, /* KWV32 (DSV11) */
|
|
{ { NULL }, 1, 1, 64, 4 }, /* QZA */
|
|
{ { NULL }, -1 } /* end table */
|
|
};
|
|
|
|
#if !defined(DEV_NEXUS)
|
|
#if defined(DEV_MBUS)
|
|
#define DEV_NEXUS DEV_MBUS
|
|
#else
|
|
#define DEV_NEXUS 0
|
|
#endif
|
|
#endif
|
|
t_stat auto_config (char *name, int32 nctrl)
|
|
{
|
|
uint32 csr = IOPAGEBASE + AUTO_CSRBASE;
|
|
uint32 vec = VEC_Q + AUTO_VECBASE;
|
|
AUTO_CON *autp;
|
|
DEVICE *dptr;
|
|
DIB *dibp;
|
|
uint32 j, vmask, amask;
|
|
|
|
if (autcon_enb == 0) /* enabled? */
|
|
return SCPE_OK;
|
|
if (name) { /* updating? */
|
|
if (nctrl < 0)
|
|
return SCPE_ARG;
|
|
for (autp = auto_tab; autp->numc >= 0; autp++) {
|
|
for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
|
|
if (strcmp (name, autp->dnam[j]) == 0) {
|
|
autp->numc = nctrl;
|
|
break;
|
|
}
|
|
}
|
|
if ((j < AUTO_MAXC) && autp->dnam[j] && (strcmp (name, autp->dnam[j]) == 0))
|
|
break;
|
|
}
|
|
}
|
|
for (autp = auto_tab; autp->numc >= 0; autp++) { /* loop thru table */
|
|
if (autp->amod) { /* floating csr? */
|
|
amask = autp->amod - 1;
|
|
csr = (csr + amask) & ~amask; /* align csr */
|
|
}
|
|
for (j = 0; (j < AUTO_MAXC) && autp->dnam[j]; j++) {
|
|
if (autp->dnam[j] == NULL) /* no device? */
|
|
break;
|
|
dptr = find_dev (autp->dnam[j]); /* find ctrl */
|
|
if ((dptr == NULL) || /* enabled, not (nexus or unibus or qbus)? */
|
|
(dptr->flags & DEV_DIS) ||
|
|
(dptr->flags & DEV_NEXUS) ||
|
|
!(dptr->flags & (DEV_UBUS | DEV_QBUS | DEV_Q18)) )
|
|
continue;
|
|
/* Sanity check that enabled devices can work on the current bus */
|
|
if ((!UNIBUS && !(dptr->flags & DEV_QBUS)) ||
|
|
(UNIBUS && !(dptr->flags & (DEV_UBUS | DEV_Q18)))) {
|
|
dptr->flags |= DEV_DIS;
|
|
if (sim_switches & SWMASK ('P'))
|
|
continue;
|
|
printf ("%s device not compatible with system bus\n", sim_dname(dptr));
|
|
if (sim_log)
|
|
fprintf (sim_log, "%s device not compatible with system bus\n", sim_dname(dptr));
|
|
return SCPE_NOFNC;
|
|
}
|
|
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
|
if (dibp == NULL) /* not there??? */
|
|
return SCPE_IERR;
|
|
if (autp->fixa[j]) /* fixed csr avail? */
|
|
dibp->ba = IOPAGEBASE + autp->fixa[j]; /* use it */
|
|
else { /* no fixed left */
|
|
dibp->ba = csr; /* set CSR */
|
|
csr += (autp->numc * autp->amod); /* next CSR */
|
|
} /* end else */
|
|
if (autp->numv) { /* vec needed? */
|
|
if (autp->fixv[j]) { /* fixed vec avail? */
|
|
if (autp->numv > 0)
|
|
dibp->vec = VEC_Q + autp->fixv[j]; /* use it */
|
|
}
|
|
else { /* no fixed left */
|
|
uint32 numv = abs (autp->numv); /* get num vec */
|
|
vmask = autp->vmod - 1;
|
|
vec = (vec + vmask) & ~vmask; /* align vector */
|
|
if (autp->numv > 0)
|
|
dibp->vec = vec; /* set vector */
|
|
vec += (autp->numc * numv * 4);
|
|
} /* end else */
|
|
} /* end vec needed */
|
|
} /* end for j */
|
|
if (autp->amod) /* flt CSR? gap */
|
|
csr = csr + 2;
|
|
} /* end for i */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Factory bad block table creation routine
|
|
|
|
This routine writes a DEC standard 044 compliant bad block table on the
|
|
last track of the specified unit. The bad block table consists of 10
|
|
repetitions of the same table, formatted as follows:
|
|
|
|
words 0-1 pack id number
|
|
words 2-3 cylinder/sector/surface specifications
|
|
:
|
|
words n-n+1 end of table (-1,-1)
|
|
|
|
Inputs:
|
|
uptr = pointer to unit
|
|
sec = number of sectors per surface
|
|
wds = number of words per sector
|
|
Outputs:
|
|
sta = status code
|
|
*/
|
|
|
|
t_stat pdp11_bad_block (UNIT *uptr, int32 sec, int32 wds)
|
|
{
|
|
int32 i;
|
|
t_addr da;
|
|
uint16 *buf;
|
|
char *namebuf, *c;
|
|
uint32 packid;
|
|
|
|
if ((sec < 2) || (wds < 16))
|
|
return SCPE_ARG;
|
|
if ((uptr->flags & UNIT_ATT) == 0)
|
|
return SCPE_UNATT;
|
|
if (uptr->flags & UNIT_RO)
|
|
return SCPE_RO;
|
|
if (!get_yn ("Overwrite last track? [N]", FALSE))
|
|
return SCPE_OK;
|
|
da = (uptr->capac - (sec * wds)) * sizeof (uint16);
|
|
if (sim_fseek (uptr->fileref, da, SEEK_SET))
|
|
return SCPE_IOERR;
|
|
if ((buf = (uint16 *) malloc (wds * sizeof (uint16))) == NULL)
|
|
return SCPE_MEM;
|
|
if ((namebuf = (char *) malloc (1 + strlen (uptr->filename))) == NULL) {
|
|
free (buf);
|
|
return SCPE_MEM;
|
|
}
|
|
strcpy (namebuf, uptr->filename);
|
|
if ((c = strrchr (namebuf, '/')))
|
|
strcpy (namebuf, c+1);
|
|
if ((c = strrchr (namebuf, '\\')))
|
|
strcpy (namebuf, c+1);
|
|
if ((c = strrchr (namebuf, ']')))
|
|
strcpy (namebuf, c+1);
|
|
packid = eth_crc32(0, namebuf, strlen (namebuf));
|
|
buf[0] = (uint16)packid;
|
|
buf[1] = (uint16)(packid >> 16) & 0x7FFF; /* Make sure MSB is clear */
|
|
buf[2] = buf[3] = 0;
|
|
for (i = 4; i < wds; i++)
|
|
buf[i] = 0177777u;
|
|
for (i = 0; (i < sec) && (i < 10); i++)
|
|
sim_fwrite (buf, sizeof (uint16), wds, uptr->fileref);
|
|
free (namebuf);
|
|
free (buf);
|
|
if (ferror (uptr->fileref))
|
|
return SCPE_IOERR;
|
|
return SCPE_OK;
|
|
}
|