143 lines
5.8 KiB
C
143 lines
5.8 KiB
C
/* id4_defs.h: Interdata 4 simulator definitions
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Copyright (c) 1993-2000, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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07-Oct-00 RMS Overhauled I/O subsystem
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14-Apr-99 RMS Changed t_addr to unsigned
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The author gratefully acknowledges the help of Carl Friend, who provided
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key documents about the Interdata 4. Questions answered to date:
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1. Do device interrupt enables mask interrupt requests or prevent
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interrupt requests? A: Mask interrupt requests.
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2. Does SLHA set C from shift out of bit <0> or bit <1>? A: From <1>.
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3. What is the limit on device numbers? A: 256. How big must the
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interrupt request and enable arrays be? A: 8 x 32b.
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4. Does BXH subtract or add the second argument?
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5. Do BXH and BXLE do a logical or arithmetic compare? A: Logical.
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6. Do ACH and SCH produce normal GL codes, or do they take into account
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prior GL codes?
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*/
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#include "sim_defs.h" /* simulator defns */
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/* Memory */
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#define MAXMEMSIZE 65536 /* max memory size */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define AMASK (MAXMEMSIZE - 1) /* address mask */
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#define MEM_ADDR_OK(x) (((t_addr) (x)) < MEMSIZE)
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#define ReadW(x) M[(x) >> 1]
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#define WriteW(x,d) if (MEM_ADDR_OK (x)) M[(x) >> 1] = d
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#define ReadB(x) ((M[(x) >> 1] >> (((x) & 1)? 0: 8)) & 0xFF)
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#define WriteB(x,d) if (MEM_ADDR_OK (x)) M[(x) >> 1] = \
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(((x) & 1)? ((M[(x) >> 1] & ~0xFF) | (d)): \
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((M[(x) >> 1] & 0xFF) | ((d) << 8)))
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/* Architectural constants */
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#define SIGN 0x8000 /* sign bit */
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#define DMASK 0xFFFF /* data mask */
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#define MAGMASK 0x7FFF /* magnitude mask */
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#define OP_4B 0x40 /* 2 byte vs 4 byte */
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#define CC_C 0x8 /* carry */
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#define CC_V 0x4 /* overflow */
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#define CC_G 0x2 /* greater than */
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#define CC_L 0x1 /* less than */
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#define CC_MASK (CC_C | CC_V | CC_G | CC_L)
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#define PSW_WAIT 0x8000 /* wait */
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#define PSW_EXI 0x4000 /* ext intr enable */
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#define PSW_MCI 0x2000 /* machine check enable */
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#define PSW_DFI 0x1000 /* divide fault enable */
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#define PSW_FDI 0x0400 /* flt divide fault enable */
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#define FDOPSW 0x28 /* flt div fault old PSW */
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#define FDNPSW 0x2C /* flt div fault new PSW */
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#define ILOPSW 0x30 /* illegal op old PSW */
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#define ILNPSW 0x34 /* illegal op new PSW */
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#define MCOPSW 0x38 /* machine check old PSW */
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#define MCNPSW 0x3C /* machine check new PSW */
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#define EXOPSW 0x40 /* external intr old PSW */
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#define EXNPSW 0x44 /* external intr new PSW */
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#define IDOPSW 0x48 /* int div fault old PSW */
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#define IDNPSW 0x4C /* int div fault new PSW */
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/* Simulator stop codes */
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#define STOP_RSRV 1 /* must be 1 */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_WAIT 4 /* wait */
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/* I/O operations */
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#define IO_ADR 0x0 /* address select */
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#define IO_RD 0x1 /* read */
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#define IO_WD 0x2 /* write */
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#define IO_OC 0x3 /* output command */
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#define IO_SS 0x5 /* sense status */
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/* Device return codes: data byte is <7:0> */
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#define IOT_V_EXM 8 /* set V flag */
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#define IOT_EXM (1u << IOT_V_EXM)
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#define IOT_V_REASON 9 /* set reason */
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/* Device command byte */
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#define CMD_V_INT 6 /* interrupt control */
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#define CMD_M_INT 0x3
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#define CMD_IENB 1 /* enable */
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#define CMD_IDIS 2 /* disable */
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#define CMD_ICOM 3 /* complement */
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#define CMD_GETINT(x) (((x) >> CMD_V_INT) & CMD_M_INT)
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/* Device status byte */
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#define STA_BSY 0x8 /* busy */
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#define STA_EX 0x4 /* examine status */
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#define STA_EOM 0x2 /* end of medium */
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#define STA_DU 0x1 /* device unavailable */
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/* Range of implemented device numbers */
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#define DEV_LOW 0x01 /* lowest intr dev */
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#define DEV_MAX 0xFF /* highest intr dev */
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#define DEVNO (DEV_MAX + 1) /* number of devices */
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#define INTSZ ((DEVNO + 31) / 32) /* number of interrupt words */
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#define DS 0x01 /* display and switches */
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#define TT 0x02 /* teletype */
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#define PT 0x03 /* paper tape */
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#define CD 0x04 /* card reader */
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#define INT_V(d) (1u << ((d) & 0x1F))
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#define SET_INT(d) int_req[(d)/32] = int_req[(d)/32] | INT_V (d)
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#define CLR_INT(d) int_req[(d)/32] = int_req[(d)/32] & ~INT_V (d)
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#define SET_ENB(d) int_enb[(d)/32] = int_enb[(d)/32] | INT_V (d)
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#define COM_ENB(d) int_enb[(d)/32] = int_enb[(d)/32] ^ INT_V (d)
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#define CLR_ENB(d) int_enb[(d)/32] = int_enb[(d)/32] & ~INT_V (d)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
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