221 lines
6.2 KiB
C
221 lines
6.2 KiB
C
/* vax730_mem.c: VAX 11/730 memory adapter
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Copyright (c) 2010-2011, Matt Burke
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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This module contains the VAX 11/730 memory controller registers.
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mctl MS730 memory adapter
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29-Mar-2011 MB First Version
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*/
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#include "vax_defs.h"
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/* Memory adapter register 0 */
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#define MCSR0_OF 0x00
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#define MCSR0_ES 0x0000007F /* Error syndrome */
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#define MCSR0_V_FPN 9
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#define MCSR0_M_FPN 0x7FFF
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#define MCSR0_FPN (MCSR0_M_FPN << MCSR0_V_FPN) /* Failing page number */
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/* Memory adapter register 1 */
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#define MCSR1_OF 0x01
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#define MCSR1_RW 0x3E000000
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#define MCSR1_MBZ 0x01FFFF80
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/* Memory adapter register 2 */
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#define MCSR2_OF 0x02
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#define MCSR2_M_MAP 0xFFFF;
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#define MCSR2_V_CS 24
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#define MCSR2_CS (1u << MCSR2_V_CS)
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#define MCSR2_MBZ 0xFEFF0000
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/* Debug switches */
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#define MCTL_DEB_RRD 0x01 /* reg reads */
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#define MCTL_DEB_RWR 0x02 /* reg writes */
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#define MEM_SIZE_16K (1u << 17) /* Board size (16k chips) */
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#define MEM_SIZE_64K (1u << 19) /* Board size (64k chips) */
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#define MEM_BOARD_MASK(x,y) ((1u << (uint32)(x/y)) - 1)
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extern UNIT cpu_unit;
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uint32 mcsr0 = 0;
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uint32 mcsr1 = 0;
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uint32 mcsr2 = 0;
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t_stat mctl_reset (DEVICE *dptr);
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t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
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t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
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char *mctl_description (DEVICE *dptr);
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/* MCTLx data structures
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mctlx_dev MCTLx device descriptor
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mctlx_unit MCTLx unit
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mctlx_reg MCTLx register list
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*/
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DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
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UNIT mctl_unit = { UDATA (NULL, 0, 0) };
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REG mctl_reg[] = {
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{ HRDATAD (CSR0, mcsr0, 32, "ECC syndrome bits") },
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{ HRDATAD (CSR1, mcsr1, 32, "CPU error control/check bits") },
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{ HRDATAD (CSR2, mcsr2, 32, "Unibus error control/check bits") },
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{ NULL }
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};
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MTAB mctl_mod[] = {
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{ MTAB_XTD|MTAB_VDV, TR_MCTL, "NEXUS", NULL,
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NULL, &show_nexus, NULL, "Display nexus" },
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{ 0 }
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};
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DEBTAB mctl_deb[] = {
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{ "REGREAD", MCTL_DEB_RRD },
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{ "REGWRITE", MCTL_DEB_RWR },
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{ NULL, 0 }
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};
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DEVICE mctl_dev = {
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"MCTL", &mctl_unit, mctl_reg, mctl_mod,
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1, 16, 16, 1, 16, 8,
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NULL, NULL, &mctl_reset,
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NULL, NULL, NULL,
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&mctl_dib, DEV_NEXUS | DEV_DEBUG, 0,
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mctl_deb, NULL, NULL, NULL, NULL, NULL,
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&mctl_description
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};
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/* Memory controller register read */
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t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt)
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{
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int32 ofs;
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ofs = NEXUS_GETOFS (pa); /* get offset */
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switch (ofs) { /* case on offset */
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case MCSR0_OF: /* CSR0 */
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*val = mcsr0;
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break;
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case MCSR1_OF: /* CSR1 */
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*val = mcsr1 & ~MCSR1_MBZ;
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break;
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case MCSR2_OF: /* CSR2 */
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*val = mcsr2 & ~MCSR2_MBZ;
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break;
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default:
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return SCPE_NXM;
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}
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if (DEBUG_PRI (mctl_dev, MCTL_DEB_RRD))
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fprintf (sim_deb, ">>MCTL: reg %d read, value = %X\n", ofs, *val);
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return SCPE_OK;
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}
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/* Memory controller register write */
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t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt)
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{
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int32 ofs;
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ofs = NEXUS_GETOFS (pa); /* get offset */
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switch (ofs) { /* case on offset */
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case MCSR0_OF: /* CSR0 */
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break;
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case MCSR1_OF: /* CSR1 */
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mcsr1 = val & MCSR1_RW;
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break;
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case MCSR2_OF: /* CSR2 */
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break;
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default:
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return SCPE_NXM;
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}
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if (DEBUG_PRI (mctl_dev, MCTL_DEB_RWR))
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fprintf (sim_deb, ">>MCTL: reg %d write, value = %X\n", ofs, val);
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return SCPE_OK;
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}
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/* Used by CPU and loader */
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void rom_wr_B (int32 pa, int32 val)
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{
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return;
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}
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/* MEMCTL reset */
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t_stat mctl_reset (DEVICE *dptr)
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{
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mcsr0 = 0;
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mcsr1 = 0;
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mcsr2 = MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) | MCSR2_CS; /* Use 64k chips */
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return SCPE_OK;
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}
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char *mctl_description (DEVICE *dptr)
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{
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return "memory controller";
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}
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t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, void* desc)
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{
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uint32 memsize = (uint32)(MEMSIZE>>20);
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uint32 baseaddr = 0;
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uint32 slot = 6;
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struct {
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uint32 capacity;
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char *option;
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} boards[] = {
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{ 1, "MS730-CA M8750"},
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{ 0, NULL}};
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int32 bd;
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while (memsize) {
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bd = 0;
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fprintf(st, "Memory slot %d (@0x%08x): %3d Mbytes (%s)\n", slot, baseaddr, boards[bd].capacity, boards[bd].option);
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memsize -= boards[bd].capacity;
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baseaddr += boards[bd].capacity<<20;
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++slot;
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}
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return SCPE_OK;
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}
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