9c4779c061
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
421 lines
12 KiB
C
421 lines
12 KiB
C
/* vax_stddev.c: VAX 3900 standard I/O devices
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Copyright (c) 1998-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tti terminal input
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tto terminal output
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clk 100Hz and TODR clock
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17-Aug-08 RMS Resync TODR on any clock reset
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18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock
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17-Oct-06 RMS Synced keyboard poll to real-time clock for idling
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22-Nov-05 RMS Revised for new terminal processing routines
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09-Sep-04 RMS Integrated powerup into RESET (with -p)
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28-May-04 RMS Removed SET TTI CTRL-C
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29-Dec-03 RMS Added console backpressure support
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25-Apr-03 RMS Revised for extended file support
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02-Mar-02 RMS Added SET TTI CTRL-C
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22-Dec-02 RMS Added console halt capability
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01-Nov-02 RMS Added 7B/8B capability to terminal
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12-Sep-02 RMS Removed paper tape, added variable vector support
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30-May-02 RMS Widened POS to 32b
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30-Apr-02 RMS Automatically set TODR to VMS-correct value during boot
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*/
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#include "vax_defs.h"
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#include <time.h>
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#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTICSR_RW (CSR_IE)
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#define TTIBUF_ERR 0x8000 /* error */
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#define TTIBUF_OVR 0x4000 /* overrun */
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#define TTIBUF_FRM 0x2000 /* framing error */
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#define TTIBUF_RBR 0x0400 /* receive break */
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#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOCSR_RW (CSR_IE)
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#define CLKCSR_IMP (CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 5000 /* 100 Hz */
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#define TMXR_MULT 1 /* 100 Hz */
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extern int32 int_req[IPL_HLVL];
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extern int32 hlt_pin;
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extern int32 sim_switches;
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int32 tti_csr = 0; /* control/status */
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int32 tto_csr = 0; /* control/status */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 100; /* ticks/second */
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int32 todr_reg = 0; /* TODR register */
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int32 todr_blow = 1; /* TODR battery low */
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int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
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t_stat tti_svc (UNIT *uptr);
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t_stat tto_svc (UNIT *uptr);
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t_stat clk_svc (UNIT *uptr);
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t_stat tti_reset (DEVICE *dptr);
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t_stat tto_reset (DEVICE *dptr);
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t_stat clk_reset (DEVICE *dptr);
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t_stat todr_resync (void);
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extern int32 sysd_hlt_enb (void);
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/* TTI data structures
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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*/
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DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
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UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
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REG tti_reg[] = {
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{ HRDATA (BUF, tti_unit.buf, 16) },
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{ HRDATA (CSR, tti_csr, 16) },
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{ FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
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{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
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{ FLDATA (IE, tti_csr, CSR_V_IE) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
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{ NULL }
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};
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MTAB tti_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 16, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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&tti_dib, 0
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};
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/* TTO data structures
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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*/
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DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } };
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UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ HRDATA (BUF, tto_unit.buf, 8) },
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{ HRDATA (CSR, tto_csr, 16) },
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{ FLDATA (INT, int_req[IPL_TTO], INT_V_TTO) },
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{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
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{ FLDATA (IE, tto_csr, CSR_V_IE) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ NULL }
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};
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MTAB tto_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 16, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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&tto_dib, 0
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};
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } };
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UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
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REG clk_reg[] = {
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{ HRDATA (CSR, clk_csr, 16) },
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{ FLDATA (INT, int_req[IPL_CLK], INT_V_CLK) },
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{ FLDATA (IE, clk_csr, CSR_V_IE) },
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{ DRDATA (TODR, todr_reg, 32), PV_LEFT },
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{ FLDATA (BLOW, todr_blow, 0) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (POLL, tmr_poll, 24), REG_NZ + PV_LEFT + REG_HRO },
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{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
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{ 0 }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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&clk_dib, 0
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};
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/* Clock and terminal MxPR routines
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iccs_rd/wr interval timer
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todr_rd/wr time of year clock
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rxcs_rd/wr input control/status
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rxdb_rd input buffer
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txcs_rd/wr output control/status
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txdb_wr output buffer
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*/
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int32 iccs_rd (void)
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{
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return (clk_csr & CLKCSR_IMP);
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}
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int32 todr_rd (void)
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{
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return todr_reg;
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}
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int32 rxcs_rd (void)
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{
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return (tti_csr & TTICSR_IMP);
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}
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int32 rxdb_rd (void)
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{
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int32 t = tti_unit.buf; /* char + error */
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tti_csr = tti_csr & ~CSR_DONE; /* clr done */
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tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
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CLR_INT (TTI);
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return t;
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}
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int32 txcs_rd (void)
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{
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return (tto_csr & TTOCSR_IMP);
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}
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void iccs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (CLK);
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clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
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return;
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}
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void todr_wr (int32 data)
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{
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todr_reg = data;
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if (data)
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todr_blow = 0;
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return;
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}
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void rxcs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (TTI);
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else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTI);
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tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);
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return;
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}
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void txcs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (TTO);
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else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTO);
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tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
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return;
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}
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void txdb_wr (int32 data)
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{
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tto_unit.buf = data & 0377;
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tto_csr = tto_csr & ~CSR_DONE;
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CLR_INT (TTO);
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sim_activate (&tto_unit, tto_unit.wait);
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return;
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}
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/* Terminal input routines
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tti_svc process event (character ready)
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tti_reset process reset
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*/
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t_stat tti_svc (UNIT *uptr)
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{
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int32 c;
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sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */
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if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
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return c;
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if (c & SCPE_BREAK) { /* break? */
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if (sysd_hlt_enb ()) /* if enabled, halt */
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hlt_pin = 1;
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tti_unit.buf = TTIBUF_ERR | TTIBUF_FRM | TTIBUF_RBR;
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}
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else tti_unit.buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
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uptr->pos = uptr->pos + 1;
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tti_csr = tti_csr | CSR_DONE;
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if (tti_csr & CSR_IE)
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SET_INT (TTI);
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return SCPE_OK;
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}
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t_stat tti_reset (DEVICE *dptr)
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{
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tti_unit.buf = 0;
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tti_csr = 0;
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CLR_INT (TTI);
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sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
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return SCPE_OK;
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}
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/* Terminal output routines
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tto_svc process event (character typed)
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tto_reset process reset
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*/
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t_stat tto_svc (UNIT *uptr)
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{
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int32 c;
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t_stat r;
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c = sim_tt_outcvt (tto_unit.buf, TT_GET_MODE (uptr->flags));
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if (c >= 0) {
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if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* retry */
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return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
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}
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}
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tto_csr = tto_csr | CSR_DONE;
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if (tto_csr & CSR_IE)
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SET_INT (TTO);
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uptr->pos = uptr->pos + 1;
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return SCPE_OK;
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}
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t_stat tto_reset (DEVICE *dptr)
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{
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tto_unit.buf = 0;
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tto_csr = CSR_DONE;
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CLR_INT (TTO);
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sim_cancel (&tto_unit); /* deactivate unit */
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return SCPE_OK;
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}
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/* Clock routines
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clk_svc process event (clock tick)
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clk_reset process reset
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todr_powerup powerup for TODR (get date from system)
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*/
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t_stat clk_svc (UNIT *uptr)
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{
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int32 t;
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if (clk_csr & CSR_IE)
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SET_INT (CLK);
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t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
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sim_activate (&clk_unit, t); /* reactivate unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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if (!todr_blow) /* incr TODR */
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todr_reg = todr_reg + 1;
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return SCPE_OK;
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}
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/* Clock coscheduling routine */
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int32 clk_cosched (int32 wait)
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{
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int32 t;
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t = sim_is_active (&clk_unit);
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return (t? t - 1: wait);
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}
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/* TODR resync routine */
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t_stat todr_resync (void)
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{
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uint32 base;
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time_t curr;
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struct tm *ctm;
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curr = time (NULL); /* get curr time */
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if (curr == (time_t) -1) /* error? */
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return SCPE_NOFNC;
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ctm = localtime (&curr); /* decompose */
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if (ctm == NULL) /* error? */
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return SCPE_NOFNC;
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base = (((((ctm->tm_yday * 24) + /* sec since 1-Jan */
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ctm->tm_hour) * 60) +
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ctm->tm_min) * 60) +
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ctm->tm_sec;
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todr_reg = (base * 100) + 0x10000000; /* cvt to VAX form */
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todr_blow = 0;
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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todr_resync (); /* resync clock */
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clk_csr = 0;
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CLR_INT (CLK);
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
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sim_activate_abs (&clk_unit, t); /* activate unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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return SCPE_OK;
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}
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