458 lines
25 KiB
C
458 lines
25 KiB
C
/* hp2100_io.h: HP 2100 device-to-CPU interface declarations
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Copyright (c) 2018, J. David Bryan
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be used
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in advertising or otherwise to promote the sale, use or other dealings in
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this Software without prior written authorization from the author.
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04-Sep-18 JDB Added card_description and rom_description to the DIB
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10-Jul-18 JDB Created
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This file contains declarations used by I/O devices to interface with
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the HP 21xx/1000 CPU. It is required by any module that uses Device
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Information Blocks (DIBs), i.e., is addressed by an I/O select code.
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*/
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/* I/O devices - fixed select code assignments */
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#define CPU 000 /* interrupt control */
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#define OVF 001 /* overflow */
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#define DMALT1 002 /* DMA 1 alternate */
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#define DMALT2 003 /* DMA 2 alternate */
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#define PWR 004 /* power fail */
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#define MPPE 005 /* memory protect/parity error */
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#define DMA1 006 /* DMA channel 1 */
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#define DMA2 007 /* DMA channel 2 */
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/* I/O devices - variable select code assignment defaults */
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#define PTR 010 /* 12597A-002 paper tape reader */
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#define TTY 011 /* 12531C teleprinter */
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#define PTP 012 /* 12597A-005 paper tape punch */
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#define TBG 013 /* 12539C time-base generator */
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#define LPS 014 /* 12653A line printer */
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#define LPT 015 /* 12845A line printer */
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#define MTD 020 /* 12559A data */
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#define MTC 021 /* 12559A control */
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#define DPD 022 /* 12557A data */
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#define DPC 023 /* 12557A control */
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#define DQD 024 /* 12565A data */
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#define DQC 025 /* 12565A control */
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#define DRD 026 /* 12610A data */
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#define DRC 027 /* 12610A control */
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#define MSD 030 /* 13181A data */
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#define MSC 031 /* 13181A control */
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#define IPLI 032 /* 12566B link in */
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#define IPLO 033 /* 12566B link out */
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#define DS 034 /* 13037A control */
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#define BACI 035 /* 12966A Buffered Async Comm Interface */
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#define MPX 036 /* 12792A/B/C 8-channel multiplexer */
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#define PIF 037 /* 12620A/12936A Privileged Interrupt Fence */
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#define MUXL 040 /* 12920A lower data */
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#define MUXU 041 /* 12920A upper data */
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#define MUXC 042 /* 12920A control */
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#define DI_DA 043 /* 12821A Disc Interface with Amigo disc devices */
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#define DI_DC 044 /* 12821A Disc Interface with CS/80 disc and tape devices */
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#define MC1 045 /* 12566B Microcircuit Interface */
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#define MC2 046 /* 12566B Microcircuit Interface */
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#define SC_OPT 002 /* start of optional devices */
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#define SC_CRS 006 /* start of devices that receive CRS */
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#define SC_VAR 010 /* start of variable assignments */
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#define SC_MAX 077 /* the maximum select code */
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#define SC_MASK 077u /* the mask for the select code */
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#define SC_BASE 8 /* the radix for the select code */
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/* I/O backplane signals.
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The INBOUND_SIGNAL and OUTBOUND_SIGNAL declarations mirror the hardware
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signals that are received and asserted, respectively, by the interfaces on
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the I/O backplane. A set of one or more signals forms an INBOUND_SET or
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OUTBOUND_SET that is sent to or returned from a device interface. Under
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simulation, the CPU and DMA dispatch one INBOUND_SET to the target device
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interface per I/O cycle. The interface returns an OUTBOUND_SET and a
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data value combined into a SIGNALS_VALUE structure to the caller.
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In addition, some signals must be asserted asynchronously, e.g., in response
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to an event service call. The "io_assert" function, provided by the CPU
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module, provides asynchronous assertion for the ENF, SIR, PON, POPIO,
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CRS, and IAK signals.
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In hardware, signals are assigned to one or more specific I/O T-periods, and
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some signals are asserted concurrently. For example, a programmed STC sc,C
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instruction asserts the STC and CLF signals together in period T4. Under
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simulation, signals are ORed to form an I/O cycle; in this example, the
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signal handler would receive an INBOUND_SET value of "ioSTC | ioCLF".
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Hardware allows parallel action for concurrent signals. Under simulation, a
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"concurrent" set of signals is processed sequentially by the signal handler
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in order of ascending numerical value. Although assigned T-periods differ
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between programmed I/O and DMA I/O cycles, a single processing order is used.
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The order of execution generally follows the order of T-period assertion,
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except that SIR is processed after all other signals that may affect the
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interrupt request chain.
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Implementation notes:
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1. The enumerations describe signals. A set of signals normally would be
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modeled as an unsigned integer, as a set may contain more than one
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signal. However, we define a set as the enumeration, as the "gdb"
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debugger has special provisions for an enumeration of discrete bit values
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and will display the set in "ORed" form.
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2. The null signal ("ioNONE") cannot be defined as an enumeration constant
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because the C language has a single name space for all enumeration
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constants, so separate "no inbound signals" and "no outbound signals"
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identifiers would be required, and because including them would require
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handlers for them in "switch" statements, which is undesirable.
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Therefore, we define "ioNONE" as an explicit integer 0, so that it is
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compatible with both enumerations.
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3. The ioCLF signal must be processed after ioSFS/ioSFC to ensure that a
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true skip test generates ioSKF before the flag is cleared, and after
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ioIOI/ioIOO/ioSTC/ioCLC to meet the requirement that executing an
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instruction having the H/C bit set is equivalent to executing the same
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instruction with the H/C bit clear and then a CLF instruction.
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4. The ioENF signal must be processed after ioSTF and ioPOPIO to ensure that
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the flag buffer flip-flop has been set before it is used to set the flag
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flip-flop.
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5. The ioPRH signal must be processed after ioIEN. The latter sets an
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internal "interrupts are enabled" flag that must be tested before
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interrupts are asserted by PRH.
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6. An I/O handler will receive ioCRS as a result of a CLC 0 instruction,
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ioPOPIO and ioCRS as a result of a RESET command, and ioPON, ioPOPIO, and
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ioCRS as a result of a RESET -P command.
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7. An I/O handler will receive ioNONE when a HLT instruction is executed
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that has the H/C bit clear (i.e., no CLF generated).
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8. In hardware, the SIR signal is generated unconditionally every T5 period
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to time the setting of the IRQ flip-flop. Under simulation, ioSIR
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indicates that the I/O handler must set the PRL, IRQ, and SRQ signals as
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required by the interface logic. ioSIR will be included in the I/O cycle
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if any of the flip-flops affecting these signals are changed and the
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interface supports interrupts or DMA transfers.
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9. In hardware, the ENF signal is unconditionally generated every T2 period
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to time the setting of the flag flip-flop and to reset the IRQ flip-flop.
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If the flag buffer flip-flip is set, then flag will be set by ENF. If
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the flag buffer is clear, ENF will not affect flag. Under simulation,
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ioENF is sent to set the flag flip-flop after the flag buffer flip-flop
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is set explicitly.
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10. In hardware, the PON signal is asserted continuously while the CPU is
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operating. Under simulation, ioPON is asserted only at simulator
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initialization or when processing a RESET -P command.
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11. To avoid polling each interface when IEN or PRH asserts from a prior
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denied condition, interfaces return two conditional signals: cnIRQ and
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cnPRL. These are identical in meaning to the ioIRQ and ioPRL signals,
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except their assertions do not depend on IEN or PRH. To identify an
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interrupting interface rapidly, the CPU keeps these conditional signals
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in the "interrupt_request_set" and "priority_holdoff_set" arrays. These
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bit vectors are examined when a higher-priority interface reasserts PRL
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or when the interrupt system is reenabled.
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12. An interface will assert cnVALID if the conditional PRL and IRQ were
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determined. If cnVALID is not asserted by the interface, then the states
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of the cnPRL and cnIRQ signals cannot be inferred from their presence or
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absence in the oubound signal set. The cnVALID pseudo-signal is required
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because although most interfaces determine the PRL and IRQ states in
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response to an SIR assertion, not all do. In particular, the 12936A
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Privileged Interrupt Fence determines PRL in response to an IOO signal.
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*/
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typedef enum { /* I/O T-Period Description */
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/* ============== ============================= */
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ioPON = 000000000001, /* T2 T3 T4 T5 T6 Power On Normal */
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ioIOI = 000000000002, /* -- -- T4 T5 -- I/O Data Input (CPU) */
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/* T2 T3 -- -- -- I/O Data Input (DMA) */
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ioIOO = 000000000004, /* -- T3 T4 -- -- I/O Data Output */
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ioSFS = 000000000010, /* -- T3 T4 T5 -- Skip if Flag is Set */
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ioSFC = 000000000020, /* -- T3 T4 T5 -- Skip if Flag is Clear */
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ioSTC = 000000000040, /* -- -- T4 -- -- Set Control flip-flop (CPU) */
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/* -- T3 -- -- -- Set Control flip-flop (DMA) */
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ioCLC = 000000000100, /* -- -- T4 -- -- Clear Control flip-flop (CPU) */
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/* -- T3 T4 -- -- Clear Control flip-flop (DMA) */
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ioSTF = 000000000200, /* -- T3 -- -- -- Set Flag flip-flop */
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ioCLF = 000000000400, /* -- -- T4 -- -- Clear Flag flip-flop (CPU) */
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/* -- T3 -- -- -- Clear Flag flip-flop (DMA) */
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ioEDT = 000000001000, /* -- -- T4 -- -- End Data Transfer */
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ioCRS = 000000002000, /* -- -- -- T5 -- Control Reset */
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ioPOPIO = 000000004000, /* -- -- -- T5 -- Power-On Preset to I/O */
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ioIAK = 000000010000, /* -- -- -- -- T6 Interrupt Acknowledge */
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ioENF = 000000020000, /* T2 -- -- -- -- Enable Flag */
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ioSIR = 000000040000, /* -- -- -- T5 -- Set Interrupt Request */
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ioIEN = 000000100000, /* T2 T3 T4 T5 T6 Interrupt system Enable */
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ioPRH = 000000200000 /* T2 T3 T4 T5 T6 Priority High */
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} INBOUND_SIGNAL;
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typedef INBOUND_SIGNAL INBOUND_SET; /* a set of INBOUND_SIGNALs */
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typedef enum { /* I/O T-Period Description */
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/* ============== ================= */
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ioSKF = 000000000001, /* -- T3 T4 T5 -- skip on flag */
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ioPRL = 000000000002, /* T2 T3 T4 T5 T6 priority low */
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ioFLG = 000000000004, /* -- -- T4 T5 -- flag */
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ioIRQ = 000000000010, /* -- -- T4 T5 -- interrupt request */
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ioSRQ = 000000000020, /* T2 T3 T4 T5 T6 service request */
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cnIRQ = 000000000040, /* conditional interrupt request */
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cnPRL = 000000000100, /* conditional priority low */
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cnVALID = 000000000200 /* conditional signals are valid */
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} OUTBOUND_SIGNAL;
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typedef OUTBOUND_SIGNAL OUTBOUND_SET; /* a set of OUTBOUND_SIGNALs */
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#define ioNONE 0 /* a universal "no signals are asserted" value */
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typedef struct { /* the I/O interface return structure */
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OUTBOUND_SET signals; /* the outbound signal set */
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HP_WORD value; /* the outbound value */
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} SIGNALS_VALUE;
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/* I/O backplane signal assertions */
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typedef enum { /* assertions passed to the "io_assert" call */
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ioa_ENF, /* Enable Flag */
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ioa_SIR, /* Set Interrupt Request */
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ioa_PON, /* Power On Normal */
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ioa_POPIO, /* Power-On Preset to I/O */
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ioa_CRS, /* Control Reset */
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ioa_IAK /* Interrupt Acknowledge */
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} IO_ASSERTION;
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/* I/O macros.
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The following macros are useful in device interface signal handlers and unit
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service routines. The parameter definition symbols employed are:
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P = a priority set value
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S = an INBOUND_SET or OUTBOUND_SET value
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L = an INBOUND_SIGNAL value
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A priority set is an unsigned value, where each bit represents an assertion
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of some nature (e.g., I/O signals, interrupt requests, etc.), and the
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position of the bit represents its priority, which decreases from LSB to MSB.
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The IOPRIORITY macro isolates the highest-priority bit from the set. It does
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this by ANDing the value with its two's complement; only the lowest-order bit
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will differ. For example (bits are numbered here from the LSB):
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priority set : ...0 0 1 1 0 1 0 0 0 0 0 0 (bits 6, 8, and 9 are asserted)
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one's compl : ...1 1 0 0 1 0 1 1 1 1 1 1
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two's compl : ...1 1 0 0 1 1 0 0 0 0 0 0
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ANDed value : ...0 0 0 0 0 1 0 0 0 0 0 0 (bit 6 is highest priority)
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If the request set indicates requests by 0 bits, rather than 1 bits, the
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IOPRIORITY macro must be called with the one's complement of the bits.
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The IONEXTSIG macro isolates the next inbound signal in sequence to process
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from the inbound signal set S.
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The IOCLEARSIG macro removes the processed signal L from the inbound signal
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set S.
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Implementation notes:
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1. The IOPRIORITY macro implements two's complement explicitly, rather than
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using a signed negation, to be compatible with machines using a
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sign-magnitude integer format. "gcc" and "clang" optimize the complement
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and add to a single NEG instruction on x86 machines.
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*/
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#define IOPRIORITY(P) ((P) & ~(P) + 1)
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#define IONEXTSIG(S) ((INBOUND_SIGNAL) IOPRIORITY (S))
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#define IOCLEARSIG(S,L) S = (INBOUND_SIGNAL) ((S) ^ (L))
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/* I/O structures.
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The Device Information Block (DIB) allows devices to be relocated in the
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machine's I/O space. Each DIB contains a pointer to the device interface
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routine, a value corresponding to the location of the interface card in the
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CPU's I/O card cage (which determines the card's select code), a card index
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that is non-zero if the interface routine services multiple cards, a pointer
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to a string that describes the card, and an optional pointer to a string
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that describes the 1000-series boot loader ROM that boots from the device
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associated with the interface card. The card description is printed by the
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SHOW CPU IOCAGE command, while the ROM description is printed by the SHOW CPU
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ROMS command. All devices should have card descriptions, but only those
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devices having boot loader ROMs will have ROM descriptions. The latter will
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be NULL if no there is no associated ROM.
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Implementation notes:
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1. The select_code and card_index fields could be smaller than the defined
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32-bit sizes, but IA-32 processors execute instructions with 32-bit
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operands much faster than those with 16- or 8-bit operands.
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2. The DIB_REGS macro provides hidden register entries needed to save and
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restore the state of a DIB. Only the potentially variable fields are
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referenced. In particular, the "io_interface" field must not be saved,
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as the address of the device's interface routine may change from version
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to version of the simulator.
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3. The Windows SDK defines an INTERFACE macro. Because "sim_defs.h"
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includes "windows.h", a name clash occurs, even though we never use any
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Windows features. So we undefine INTERFACE here to repurpose it for our
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own use.
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*/
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#undef INTERFACE /* remove any previous definition */
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typedef struct dib DIB; /* an incomplete definition */
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typedef SIGNALS_VALUE INTERFACE /* the I/O device interface function prototype */
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(const DIB *dibptr, /* a pointer to the constant device information block */
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INBOUND_SET inbound_signals, /* a set of inbound signals */
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HP_WORD inbound_value); /* a 16-bit inbound value */
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struct dib { /* the Device Information Block */
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INTERFACE *io_interface; /* the controller I/O interface function pointer */
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uint32 select_code; /* the device's select code (02-77) */
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uint32 card_index; /* the card index if multiple interfaces are supported */
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const char *card_description; /* the card description (model number and name) */
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const char *rom_description; /* the 1000 boot loader ROM description (model number and name) */
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};
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#define DIB_REGS(dib) \
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/* Macro Name Location Width Flags */ \
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/* ------ ------- -------------------------- ----- ----------------- */ \
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{ ORDATA (DIBSC, dib.select_code, 32), PV_LEFT | REG_HRO }
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/* Initial Binary Loader.
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HP 1000-series CPUs contain from one to four bootstrap loader ROMs that
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contain the 64-word initial binary loaders for the associated devices. The
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loader program to use is selected by setting the S-register as follows:
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
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| ROM # | - - | select code | - - - - - - |
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+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
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...and then pressing the front panel IBL button to copy the program into
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main memory for execution.
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Bits 15-14 select one of four loader ROM sockets on the CPU board that may
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contain ROMs, and bits 11-6 specify the select code of the associated
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interface card. If the specified socket does, the contents of the ROM are
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copied into the upper 64 words of memory and configured to use the specified
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select code. The unspecified bits of the S register are available for use by
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the bootstrap program.
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The 21xx CPUs store their initial binary loaders in the last 64 words of
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available memory. This memory is protected by a LOADER ENABLE switch on the
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front panel. When the switch is off (disabled), main memory effectively ends
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64 locations earlier, i.e., the loader area is treated as non-existent.
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Because these are core machines, the loader is retained when system power is
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off.
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In simulation, we define a BOOT_LOADER structure containing three indicies
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and a 64-word array that holds the bootstrap program. The start_index gives
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the array index of the first program word to execute, the dma_index gives the
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array index of the DMA control word that specifies the interface select code,
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and the fwa_index gives the array index of the word containing the negative
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starting address of the loader in memory; this is used to ensure that the
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bootstrap does not overlay itself when reading from the device.
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A LOADER_ARRAY consists of two BOOT_LOADER structures: one for 21xx-series
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machines, and one for 1000-series machines. If either BOOT_LOADER is not
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applicable, e.g., because the CPU series does not support booting from the
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given device, then the associated start_index is set to IBL_NA. If the boot
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loader exists but does not use DMA and/or does not configure a starting
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address word, the associated indicies are set to IBL_NA.
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*/
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#define IBL_WIDTH 6 /* loader ROM address width */
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#define IBL_MASK ((1u << IBL_WIDTH) - 1) /* loader ROM address mask (2 ** 6 - 1) */
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#define IBL_MAX ((1u << IBL_WIDTH) - 1) /* loader ROM address maximum (2 ** 6 - 1) */
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#define IBL_SIZE (IBL_MAX + 1) /* loader ROM size in words */
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#define IBL_START 0 /* ROM array index of the program start */
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#define IBL_DMA (IBL_MAX - 1) /* ROM array index of the DMA configuration word */
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#define IBL_FWA (IBL_MAX - 0) /* ROM array index of the negative starting address */
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#define IBL_NA (IBL_MAX + 1) /* "not-applicable" ROM array index */
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#define IBL_S_CLEAR 0000000u /* cpu_copy_loader mask to clear the S register */
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#define IBL_S_NOCLEAR 0177777u /* cpu_copy_loader mask to preserve the S register */
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#define IBL_S_NOSET 0000000u /* cpu_copy_loader mask to preserve the S register */
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#define IBL_ROM_MASK 0140000u /* ROM socket selector mask */
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#define IBL_SC_MASK 0007700u /* device select code mask */
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#define IBL_USER_MASK ~(IBL_ROM_MASK | IBL_SC_MASK)
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#define IBL_ROM_SHIFT 14
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#define IBL_SC_SHIFT 6
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#define IBL_ROM(s) (((s) & IBL_ROM_MASK) >> IBL_ROM_SHIFT)
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#define IBL_SC(s) (((s) & IBL_SC_MASK) >> IBL_SC_SHIFT)
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#define IBL_TO_SC(c) ((c) << IBL_SC_SHIFT & IBL_SC_MASK)
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typedef struct {
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uint32 start_index; /* the array index of the start of the program */
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uint32 dma_index; /* the array index of the DMA configuration word */
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uint32 fwa_index; /* the array index of the negative starting address */
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MEMORY_WORD loader [IBL_SIZE]; /* the 64-word bootstrap loader program */
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} BOOT_LOADER;
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typedef BOOT_LOADER LOADER_ARRAY [2]; /* array (21xx, 1000) of bootstrap loaders */
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/* CPU global utility routine declarations */
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extern uint32 cpu_copy_loader (const LOADER_ARRAY boot, uint32 sc, HP_WORD sr_clear, HP_WORD sr_set);
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extern t_bool cpu_io_stop (UNIT *uptr);
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/* I/O subsystem global utility routine declarations */
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extern void io_assert (DEVICE *dptr, IO_ASSERTION assertion);
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/* Main memory global utility routine declarations */
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extern HP_WORD mem_examine (uint32 address);
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extern void mem_deposit (uint32 address, HP_WORD value);
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