551 lines
23 KiB
C
551 lines
23 KiB
C
/* sys.c: Intel System Configuration Device
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Copyright (c) 2020, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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11 Sep 20 - Original file.
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NOTES:
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*/
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#include "system_defs.h" /* system header in system dir */
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//option board types
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#define SBC064 128
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#define SBC464 129
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#define SBC201 130
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#define SBC202 131
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#define SBC204 132
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#define SBC206 133
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#define SBC208 134
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#define ZX200A 135
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//Single board computer device types
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#define i3214 1
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#define i8080 2
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#define i8085 3
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#define i8251 4
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#define i8253 5
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#define i8255 6
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#define i8259 7
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#define IOC_CONT 8
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#define IPC_CONT 9
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#define MULTI 64
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#define EPROM 65
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#define RAM 66
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//System types
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#define MDS_210 0
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#define MDS_220 1
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#define MDS_225 2
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#define MDS_230 3
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#define MDS_800 4
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#define MDS_810 5
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#define SDK_80 6
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#define SYS_8010 7
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#define SYS_8010A 8
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#define SYS_8010B 9
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#define SYS_8020 10
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#define SYS_80204 11
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#define SYS_8024 12
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#define SYS_8030 13
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#define sys_name "Intel MDS Configuration Controller"
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/* external globals */
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extern uint16 PCX;
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/* function prototypes */
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t_stat sys_cfg(uint16 base, uint16 devnum, uint8 dummy);
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t_stat sys_clr(void);
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t_stat sys_reset(DEVICE *dptr);
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static const char* sys_desc(DEVICE *dptr);
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t_stat sys_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat sys_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16, uint16, uint8);
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extern uint8 unreg_dev(uint16);
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extern t_stat i3214_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat i8251_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat i8253_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat i8255_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat i8259_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat ioc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat ipc_cont_cfg(uint16 base, uint16 devnum, uint8 dummy);
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extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
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extern t_stat RAM_cfg(uint16 base, uint16 size, uint8 dummy);
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extern t_stat isbc064_cfg(uint16 base, uint16 size, uint8 dummy);
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extern t_stat isbc464_cfg(uint16 base, uint16 size, uint8 dummy);
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extern t_stat i3214_clr(void);
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extern t_stat i8251_clr(void);
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extern t_stat i8253_clr(void);
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extern t_stat i8255_clr(void);
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extern t_stat i8259_clr(void);
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extern t_stat ioc_cont_clr(void);
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extern t_stat ipc_cont_clr(void);
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extern t_stat EPROM_clr(void);
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extern t_stat RAM_clr(void);
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extern t_stat isbc064_clr(void);
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extern t_stat isbc464_clr(void);
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extern void clr_dev(void);
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/* globals */
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int model = -1; //force no model
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int mem_map = 0; //memory model
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typedef struct device {
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int id;
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const char *name;
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int num;
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int args;
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t_stat (*cfg_routine)(uint16 val1, uint16 val2, uint8 val3);
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t_stat (*clr_routine)(void);
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uint16 val[8];
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} SYS_DEV;
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typedef struct system_model {
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int id;
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const char *name;
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int num;
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SYS_DEV devices[30];
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} SYS_MODEL;
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#define SYS_NUM 15
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SYS_MODEL models[SYS_NUM+1] = {
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{MDS_210, "MDS-210 ", 9,
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// id name num arg routine routine1 val1 val2 val3
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{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
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{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
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{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0x7FFF },
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{ SBC464, "SBC464", 1, 2, isbc464_cfg, isbc464_clr, 0xA800, 0x47FF }},
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},
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{MDS_220, "MDS-220 ", 8,
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{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
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{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
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{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0x7FFF }}
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},
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{MDS_225, "MDS-225 ", 8,
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{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
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{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
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{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0xFFFF }},
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},
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{MDS_230, "MDS-230 ", 9,
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{{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xF0 },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ i8259, "I8259", 2, 1, i8259_cfg, i8259_clr, 0xFA, 0xFC },
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{ IOC_CONT, "IOC-CONT", 1, 1, ioc_cont_cfg, ioc_cont_clr, 0xC0 },
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{ IPC_CONT, "IPC-CONT", 1, 1, ipc_cont_cfg, ipc_cont_clr, 0xFF },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x0000, 0x7FFF },
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{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x8000, 0x7FFF }},
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},
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{MDS_800, "MDS-800 ", 5,
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{{ i3214, "I3214", 1, 1, i3214_cfg, i3214_clr, 0xFC },
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{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x00FF },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0xF800, 0x07FF },
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{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0x7FFF }},
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},
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{MDS_810, "MDS-810 ", 6,
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{{ i3214, "I3214", 1, 1, i3214_cfg, i3214_clr, 0xFC },
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{ i8251, "I8251", 2, 1, i8251_cfg, i8251_clr, 0xF4, 0xF6 },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x00FF },
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{ EPROM, "EPROM2", 1, 2, EPROM_cfg, EPROM_clr, 0xF800, 0x07FF },
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{ SBC064, "SBC064", 1, 2, isbc064_cfg, isbc064_clr, 0x0000, 0x7FFF },
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{ SBC464, "SBC464", 1, 2, isbc464_cfg, isbc464_clr, 0xA800, 0x47FF }},
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},
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{SDK_80, "SDK-80 ", 4,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xFA },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xF4, 0xEC },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x1000, 0x03FF }},
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},
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{SYS_8010, "SYS-80/10 ", 4,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x0FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
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},
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{SYS_8010A, "SYS-80/10A ", 4,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
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},
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{SYS_8010B, "SYS-80/10B ", 4,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8255, "I8255", 2, 1, i8255_cfg, i8255_clr, 0xE4, 0xE8 },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x3FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
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},
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{SYS_8020, "SYS-80/20 ", 6,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
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{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
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{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3800, 0x07FF }},
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},
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{SYS_8020-4, "SYS-80/20-4", 6,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
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{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
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{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3000, 0x0FFF }},
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},
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{SYS_8024, "SYS-80/24 ", 6,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
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{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
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{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x3c00, 0x03FF }},
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},
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{SYS_8030, "SYS-80/30 ", 6,
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{{ i8251, "I8251", 1, 1, i8251_cfg, i8251_clr, 0xEC },
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{ i8253, "I8253", 1, 1, i8253_cfg, i8253_clr, 0xDC },
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{ i8255, "I8255", 1, 1, i8255_cfg, i8255_clr, 0xE8 },
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{ i8259, "I8259", 1, 1, i8259_cfg, i8259_clr, 0xDA },
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{ EPROM, "EPROM", 1, 2, EPROM_cfg, EPROM_clr, 0x0000, 0x1FFF },
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{ RAM, "RAM", 1, 2, RAM_cfg, RAM_clr, 0x2000, 0x3FFF }},
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},
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{0}
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};
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UNIT sys_unit = { UDATA (NULL, 0, 0) };
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REG sys_reg[] = {
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{ NULL }
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};
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MTAB sys_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "MODEL", &sys_set_model, NULL, NULL,
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"Sets the system model" },
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{ MTAB_XTD | MTAB_VDV, 0, "MODEL", NULL, NULL, &sys_show_model, NULL,
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"Shows the system devices" },
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{ 0 }
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};
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DEBTAB sys_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE sys_dev = {
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"SYS", //name
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&sys_unit, //units
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sys_reg, //registers
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sys_mod, //modifiers
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1, //numunits
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0, //aradix
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0, //awidth
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0, //aincr
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0, //dradix
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0, //dwidth
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NULL, //examine
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NULL, //deposit
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sys_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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sys_debug, //debflags
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NULL, //msize
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NULL, //lname
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NULL, //help routine
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NULL, //attach help routine
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NULL, //help context
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&sys_desc //device description
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};
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static const char* sys_desc(DEVICE *dptr) {
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return sys_name;
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}
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t_stat sys_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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int i, j;
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DEVICE *dptr;
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if (model == (-1)) return SCPE_ARG; //no valid config
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sim_printf("sys_cfg: Configure %s:\n", models[model].name);
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switch (model) { //set memory map type
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case 0: //mds-210
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mem_map = 0; //ipb
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break;
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case 1: //mds-220
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mem_map = 0; //ipb
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break;
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case 2: //mds-225
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mem_map = 1; //ipc
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break;
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case 3: //mds-230
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mem_map = 0; //ipb
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break;
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case 4: //mds-800
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mem_map = 2; //800
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break;
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case 5: //mds-810
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mem_map = 2; //800
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break;
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case 6: //sdk-80
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mem_map = 3; //sdk-80
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break;
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case 7: //sys-8010
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mem_map = 4; //sys-8010
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break;
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case 8: //sys-8010A
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mem_map = 4; //sys-8010A
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break;
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case 9: //sys-8010B
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mem_map = 4; //sys-8010B
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break;
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case 10: //sys-8020
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mem_map = 4; //sys-8020
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break;
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case 11: //sys-8020-4
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mem_map = 4; //sys-8020-4
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break;
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case 12: //sys-8024
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mem_map = 4; //sys-8024
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break;
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case 13: //sys-8030
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mem_map = 4; //sys-8030
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break;
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default:
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return SCPE_ARG;
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}
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for (i=0; i<models[model].num; i++) { //for each device in model
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dptr = find_dev (models[model].devices[i].name);
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if ((dptr != NULL) && ((dptr->flags & DEV_DIS) != 0)) { // disabled
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dptr->flags &= ~DEV_DIS; //enable device
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}
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for (j=0; j<models[model].devices[i].num; j++) { //for each instance of a device
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switch(models[model].devices[i].args) {
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case 1: //one argument
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models[model].devices[i].cfg_routine (models[model].devices[i].val[j], j, 0);
|
|
break;
|
|
case 2: //two arguments
|
|
models[model].devices[i].cfg_routine (models[model].devices[i].val[j],
|
|
models[model].devices[i].val[j+1], j);
|
|
break;
|
|
case 3: //three arguments
|
|
models[model].devices[i].cfg_routine (models[model].devices[i].val[j],
|
|
models[model].devices[i].val[j+1], models[model].devices[i].val[j+1] & 0xff);
|
|
break;
|
|
default:
|
|
return SCPE_ARG;
|
|
}
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat sys_clr(void)
|
|
{
|
|
int i, j;
|
|
DEVICE *dptr;
|
|
|
|
printf("sys_clr: Unconfiguring %s\n", models[model].name);
|
|
for (i=0; i<models[model].num; i++) { //for each device in model
|
|
dptr = find_dev (models[model].devices[i].name);
|
|
if ((dptr != NULL) && (dptr->flags & DEV_DIS)) { // enabled
|
|
dptr->flags |= DEV_DIS; //disable device
|
|
}
|
|
for (j=0; j<models[model].devices[i].num; j++) { //for each instance of a device
|
|
printf(" %s%d\n", models[model].devices[i].name, j);
|
|
models[model].devices[i].clr_routine ();
|
|
}
|
|
}
|
|
sim_name[0] = '\0';
|
|
// models[model].name[0] = '\0';
|
|
model = -1;
|
|
mem_map = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat sys_reset(DEVICE *dptr)
|
|
{
|
|
if (dptr == NULL)
|
|
return SCPE_ARG;
|
|
sim_printf("SYS Reset\n");
|
|
sys_cfg(0, 0, 0);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Set/show CPU model */
|
|
|
|
t_stat sys_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
|
{
|
|
int i, j;
|
|
DEVICE *dptr;
|
|
|
|
if (cptr == NULL)
|
|
return SCPE_ARG;
|
|
if (model != -1) sys_clr();
|
|
for (i=0; i<SYS_NUM; i++) { //search stored configurations
|
|
if (!strncmp(cptr, models[i].name, strlen(cptr))) { //find the system
|
|
model = models[i].id;
|
|
strncpy(sim_name, models[i].name, 11);
|
|
printf("sys_set_model: Configuring %s\n", sim_name);
|
|
switch (model) { //set memory map type
|
|
case 0: //mds-210
|
|
mem_map = 0; //ipb
|
|
break;
|
|
case 1: //mds-220
|
|
mem_map = 0; //ipb
|
|
break;
|
|
case 2: //mds-225
|
|
mem_map = 1; //ipc
|
|
break;
|
|
case 3: //mds-230
|
|
mem_map = 0; //ipb
|
|
break;
|
|
case 4: //mds-800
|
|
mem_map = 2; //800
|
|
break;
|
|
case 5: //mds-810
|
|
mem_map = 2; //800
|
|
break;
|
|
case 6: //SDK-80
|
|
mem_map = 3; //sdk-80
|
|
break;
|
|
case 7: //sys-8010
|
|
mem_map = 4; //sys-8010
|
|
break;
|
|
case 8: //sys-8010A
|
|
mem_map = 4; //sys-8010A
|
|
break;
|
|
case 9: //sys-8010B
|
|
mem_map = 4; //sys-8010B
|
|
break;
|
|
case 10: //sys-8020
|
|
mem_map = 4; //sys-8020
|
|
break;
|
|
case 11: //sys-8020-4
|
|
mem_map = 4; //sys-8020-4
|
|
break;
|
|
case 12: //sys-8024
|
|
mem_map = 4; //sys-8024
|
|
break;
|
|
case 13: //sys-8030
|
|
mem_map = 4; //sys-8030
|
|
break;
|
|
default:
|
|
return SCPE_ARG;
|
|
}
|
|
for (i=0; i<models[model].num; i++) { //for each device in model
|
|
dptr = find_dev (models[model].devices[i].name);
|
|
if ((dptr != NULL) && ((dptr->flags & DEV_DIS) != 0)) { // disabled
|
|
dptr->flags &= ~DEV_DIS; //enable device
|
|
}
|
|
for (j=0; j<models[model].devices[i].num; j++) { //for each instance of a device
|
|
switch(models[model].devices[i].args) {
|
|
case 1: //one argument
|
|
models[model].devices[i].cfg_routine (models[model].devices[i].val[j], j, 0);
|
|
break;
|
|
case 2: //two arguments
|
|
models[model].devices[i].cfg_routine (models[model].devices[i].val[j],
|
|
models[model].devices[i].val[j+1], j);
|
|
break;
|
|
case 3: //three arguments
|
|
models[model].devices[i].cfg_routine (models[model].devices[i].val[j],
|
|
models[model].devices[i].val[j+1], models[model].devices[i].val[j+1] & 0xff);
|
|
break;
|
|
default:
|
|
return SCPE_ARG;
|
|
}
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
}
|
|
printf("Unknown Model Name %s\n", cptr);
|
|
return SCPE_ARG;
|
|
}
|
|
|
|
t_stat sys_show_model (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
|
|
{
|
|
int i, j;
|
|
|
|
if (uptr == NULL)
|
|
return SCPE_ARG;
|
|
return SCPE_OK;
|
|
fprintf(st, "%s: %d\n", models[model].name, models[model].num);
|
|
for (i=0; i<models[model].num; i++) {
|
|
fprintf(st, " %s:", models[model].devices[i].name);
|
|
fprintf(st, " %d", models[model].devices[i].num);
|
|
fprintf(st, " %d", models[model].devices[i].args);
|
|
for (j=0; j<models[model].devices[i].num; j++) {
|
|
if (models[model].devices[i].args == 2)
|
|
fprintf(st, " 0%04XH 0%04XH", models[model].devices[i].val[j],
|
|
models[model].devices[i].val[j+1]);
|
|
else
|
|
fprintf(st, " 0%04XH", models[model].devices[i].val[j]);
|
|
}
|
|
fprintf(st, "\n");
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* end of sys.c */
|