797 lines
27 KiB
C
797 lines
27 KiB
C
/* zx-200a.c: ZENDEX single/double density disk adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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28 Jun 16 - Original file.
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NOTES:
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This controller will mount 4 DD disk images on drives :F0: thru :F3: addressed
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at ports 078H to 07FH. It also will mount 2 SD disk images on :F4: and :F5:
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addressed at ports 088H to 08FH. These are on physical drives :F0: and :F1:.
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Registers:
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078H - Read - Subsystem status
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bit 0 - ready status of drive 0
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bit 1 - ready status of drive 1
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bit 2 - state of channel's interrupt FF
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bit 3 - controller presence indicator
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bit 4 - DD controller presence indicator
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bit 5 - ready status of drive 2
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bit 6 - ready status of drive 3
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bit 7 - zero
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079H - Read - Read result type (bits 2-7 are zero)
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00 - I/O complete with error
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01 - Reserved
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10 - Result byte contains diskette ready status
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11 - Reserved
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079H - Write - IOPB address low byte.
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07AH - Write - IOPB address high byte and start operation.
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07BH - Read - Read result byte
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If result type is 00H
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bit 0 - deleted record
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bit 1 - CRC error
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bit 2 - seek error
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bit 3 - address error
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bit 4 - data overrun/underrun
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bit 5 - write protect
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bit 6 - write error
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bit 7 - not ready
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If result type is 02H and ready has changed
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bit 0 - zero
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bit 1 - zero
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bit 2 - zero
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bit 3 - zero
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bit 4 - drive 2 ready
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bit 5 - drive 3 ready
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bit 6 - drive 0 ready
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bit 7 - drive 1 ready
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else return 0
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07FH - Write - Reset diskette system.
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Operations:
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NOP - 0x00
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Seek - 0x01
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Format Track - 0x02
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Recalibrate - 0x03
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Read Data - 0x04
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Verify CRC - 0x05
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Write Data - 0x06
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Write Deleted Data - 0x07
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IOPB - I/O Parameter Block
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Byte 0 - Channel Word
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bit 3 - data word length (=8-bit, 1=16-bit)
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bit 4-5 - interrupt control
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00 - I/O complete interrupt to be issued
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01 - I/O complete interrupts are disabled
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10 - illegal code
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11 - illegal code
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bit 6- randon format sequence
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Byte 1 - Diskette Instruction
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bit 0-2 - operation code
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000 - no operation
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001 - seek
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010 - format track
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011 - recalibrate
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100 - read data
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101 - verify CRC
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110 - write data
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111 - write deleted data
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bit 3 - data word length ( same as byte-0, bit-3)
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bit 4-5 - unit select
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00 - drive 0
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01 - drive 1
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10 - drive 2
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11 - drive 3
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bit 6-7 - reserved (zero)
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Byte 2 - Number of Records
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Byte 4 - Track Address
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Byte 5 - Sector Address
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Byte 6 - Buffer Low Address
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Byte 7 - Buffer High Address
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u3 -
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u4 -
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u5 -
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u6 - fdd number.
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The ZX-200A appears to the multibus system as if there were an iSBC-201
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installed addressed at 0x88-0x8f and an iSBC-202 installed addressed at
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0x78-0x7F. The DD disks are drive 0 - 3. The SD disks are mapped over
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DD disks 0 - 1. Thus drive 0 - 1 can be SD or DD, but not both. Drive
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2 - 3 are always DD.
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*/
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#include "system_defs.h" /* system header in system dir */
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#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
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#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
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#define FDD_NUM 6
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//disk controoler operations
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#define DNOP 0x00 //disk no operation
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#define DSEEK 0x01 //disk seek
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#define DFMT 0x02 //disk format
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#define DHOME 0x03 //disk home
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#define DREAD 0x04 //disk read
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#define DVCRC 0x05 //disk verify CRC
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#define DWRITE 0x06 //disk write
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//status
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#define RDY0 0x01 //FDD 0 ready
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#define RDY1 0x02 //FDD 1 ready
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#define FDCINT 0x04 //FDC interrupt flag
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#define FDCPRE 0x08 //FDC board present
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#define FDCDD 0x10 //fdc is DD
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#define RDY2 0x20 //FDD 2 ready
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#define RDY3 0x40 //FDD 3 ready
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//result type
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#define ROK 0x00 //FDC error
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#define RCHG 0x02 //FDC OK OR disk changed
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// If result type is ROK then rbyte is
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#define RB0DR 0x01 //deleted record
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#define RB0CRC 0x02 //CRC error
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#define RB0SEK 0x04 //seek error
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#define RB0ADR 0x08 //address error
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#define RB0OU 0x10 //data overrun/underrun
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#define RB0WP 0x20 //write protect
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#define RB0WE 0x40 //write error
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#define RB0NR 0x80 //not ready
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// If result type is RCHG then rbyte is
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#define RB1RD2 0x10 //drive 2 ready
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#define RB1RD3 0x20 //drive 3 ready
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#define RB1RD0 0x40 //drive 0 ready
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#define RB1RD1 0x80 //drive 1 ready
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//disk geometry values
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#define MDSSD 256256 //single density FDD size
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#define MDSDD 512512 //double density FDD size
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#define MAXSECSD 26 //single density last sector
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#define MAXSECDD 52 //double density last sector
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#define MAXTRK 76 //last track
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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extern uint8 multibus_get_mbyte(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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/* external globals */
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extern uint16 PCX;
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/* internal function prototypes */
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t_stat isbc064_cfg(uint16 base);
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t_stat zx200a_reset(DEVICE *dptr);
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void zx200a_reset1(void);
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t_stat zx200a_attach (UNIT *uptr, CONST char *cptr);
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t_stat zx200a_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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uint8 zx200ar0SD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar0DD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar1DD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar2SD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar2DD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar7(t_bool io, uint8 data, uint8 devnum);
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void zx200a_diskio(void);
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/* globals */
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typedef struct { //FDD definition
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// uint8 *buf;
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// int t0;
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// int rdy;
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uint8 sec;
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uint8 cyl;
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uint8 dd;
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// uint8 maxsec;
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// uint8 maxcyl;
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} FDDDEF;
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typedef struct { //FDC definition
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uint16 baseport; //FDC base port
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uint16 iopb; //FDC IOPB
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uint8 DDstat; //FDC DD status
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uint8 SDstat; //FDC SD status
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uint8 rdychg; //FDC ready change
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uint8 rtype; //FDC result type
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uint8 rbyte0; //FDC result byte for type 00
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uint8 rbyte1; //FDC result byte for type 10
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uint8 intff; //fdc interrupt FF
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FDDDEF fdd[FDD_NUM]; //indexed by the FDD number
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} FDCDEF;
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FDCDEF zx200a;
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/* ZX-200A Standard I/O Data Structures */
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UNIT zx200a_unit[] = {
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSSD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSSD), 20 },
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};
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REG zx200a_reg[] = {
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{ HRDATA (STAT0, zx200a.SDstat, 8) }, /* zx200a 0 SD status */
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{ HRDATA (STAT0, zx200a.DDstat, 8) }, /* zx200a 0 DD status */
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{ HRDATA (RTYP0, zx200a.rtype, 8) }, /* zx200a 0 result type */
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{ HRDATA (RBYT0A, zx200a.rbyte0, 8) }, /* zx200a 0 result byte 0 */
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{ HRDATA (RBYT0B, zx200a.rbyte1, 8) }, /* zx200a 0 result byte 1 */
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{ HRDATA (INTFF0, zx200a.intff, 8) }, /* zx200a 0 interrupt f/f */
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{ NULL }
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};
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MTAB zx200a_mod[] = {
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{ UNIT_WPMODE, 0, "RW", "RW", &zx200a_set_mode },
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{ UNIT_WPMODE, UNIT_WPMODE, "WP", "WP", &zx200a_set_mode },
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{ 0 }
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};
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DEBTAB zx200a_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE zx200a_dev = {
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"ZX200A", //name
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zx200a_unit, //units
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zx200a_reg, //registers
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zx200a_mod, //modifiers
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FDD_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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zx200a_reset, //reset
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NULL, //boot
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&zx200a_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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// DEBUG_flow + DEBUG_read + DEBUG_write, //dctrl
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0, //dctrl
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zx200a_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* Service routines to handle simulator functions */
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// configuration routine
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t_stat zx200a_cfg(uint8 base)
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{
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int32 i;
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UNIT *uptr;
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sim_printf(" zx200a: at base 0%02XH\n",
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base);
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//register I/O port addresses for each function
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reg_dev(zx200ar0DD, base, 0); //read status
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reg_dev(zx200ar1DD, base + 1, 0); //read rslt type/write IOPB addr-l
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reg_dev(zx200ar2DD, base + 2, 0); //write IOPB addr-h and start
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reg_dev(zx200ar3, base + 3, 0); //read rstl byte
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reg_dev(zx200ar7, base + 7, 0); //write reset zx200a
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reg_dev(zx200ar0SD, base + 16, 0); //read status
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reg_dev(zx200ar1SD, base + 17, 0); //read rslt type/write IOPB addr-l
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reg_dev(zx200ar2SD, base + 18, 0); //write IOPB addr-h and start
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reg_dev(zx200ar3, base + 19, 0); //read rstl byte
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reg_dev(zx200ar7, base + 23, 0); //write reset zx200a
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// one-time initialization for all FDDs
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for (i = 0; i < FDD_NUM; i++) {
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uptr = zx200a_dev.units + i;
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uptr->u6 = i; //fdd unit number
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat zx200a_reset(DEVICE *dptr)
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{
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zx200a_reset1(); //software reset
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return SCPE_OK;
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}
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/* Software reset routine */
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void zx200a_reset1(void)
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{
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int32 i;
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UNIT *uptr;
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zx200a.DDstat = 0; //clear the FDC DD status
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zx200a.SDstat = 0; //clear the FDC SD status
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for (i = 0; i < FDD_NUM; i++) { /* handle all units */
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uptr = zx200a_dev.units + i;
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zx200a.DDstat |= FDCPRE | FDCDD; //set the FDC DD status
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zx200a.SDstat |= FDCPRE; //set the FDC SD status
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if (i <= 3 ) { //first 4 are DD, last 2 are SD
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zx200a.fdd[i].dd = 1; //set double density
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} else {
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zx200a.fdd[i].dd = 0; //set single density
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}
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zx200a.rtype = ROK;
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zx200a.rbyte0 = 0; //set no error
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if (uptr->flags & UNIT_ATT) { /* if attached */
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switch(i){
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case 0:
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zx200a.DDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 1:
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zx200a.DDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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case 2:
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zx200a.DDstat |= RDY2; //set FDD 2 ready
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zx200a.rbyte1 |= RB1RD2;
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break;
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case 3:
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zx200a.DDstat |= RDY3; //set FDD 3 ready
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zx200a.rbyte1 |= RB1RD3;
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break;
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case 4:
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zx200a.SDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 5:
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zx200a.SDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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}
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zx200a.rdychg = 0;
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}
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}
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}
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/* zx200a attach - attach an .IMG file to a FDD */
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t_stat zx200a_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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uint8 fddnum;
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sim_debug (DEBUG_flow, &zx200a_dev, " zx200a_attach: Entered with cptr=%s\n", cptr);
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" zx200a_attach: Attach error %d\n", r);
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return r;
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}
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fddnum = uptr->u6;
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switch(fddnum){
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case 0:
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zx200a.DDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 1:
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zx200a.DDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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case 2:
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zx200a.DDstat |= RDY2; //set FDD 2 ready
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zx200a.rbyte1 |= RB1RD2;
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break;
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case 3:
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zx200a.DDstat |= RDY3; //set FDD 3 ready
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zx200a.rbyte1 |= RB1RD3;
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break;
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case 4:
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zx200a.SDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 5:
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zx200a.SDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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}
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zx200a.rtype = ROK;
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zx200a.rbyte0 = 0; //set no error
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return SCPE_OK;
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}
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/* zx200a set mode = Write protect */
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t_stat zx200a_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (uptr->flags & UNIT_ATT)
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return sim_messagef (SCPE_ALATT, "%s is already attached to %s\n", sim_uname(uptr), uptr->filename);
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if (val & UNIT_WPMODE) { /* write protect */
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uptr->flags |= val;
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} else { /* read write */
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uptr->flags &= ~val;
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}
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* zx200a control port functions */
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uint8 zx200ar0SD(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read ststus*/
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return zx200a.SDstat;
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}
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return 0;
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}
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uint8 zx200ar0DD(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read ststus*/
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return zx200a.DDstat;
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}
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return 0;
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}
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|
|
uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read operation */
|
|
zx200a.intff = 0; //clear interrupt FF
|
|
if (zx200a.intff)
|
|
zx200a.SDstat &= ~FDCINT;
|
|
zx200a.rtype = ROK;
|
|
return zx200a.rtype;
|
|
} else { /* write control port */
|
|
zx200a.iopb = data;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 zx200ar1DD(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read operation */
|
|
zx200a.intff = 0; //clear interrupt FF
|
|
if (zx200a.intff)
|
|
zx200a.DDstat &= ~FDCINT;
|
|
if (zx200a.rdychg) {
|
|
zx200a.rtype = ROK;
|
|
return zx200a.rtype;
|
|
} else {
|
|
zx200a.rtype = ROK;
|
|
return zx200a.rtype;
|
|
}
|
|
} else { /* write control port */
|
|
zx200a.iopb = data;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 zx200ar2SD(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
zx200a.iopb |= (data << 8);
|
|
zx200a_diskio();
|
|
if (zx200a.intff)
|
|
zx200a.SDstat |= FDCINT;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 zx200ar2DD(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
zx200a.iopb |= (data << 8);
|
|
zx200a_diskio();
|
|
if (zx200a.intff)
|
|
zx200a.DDstat |= FDCINT;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
if (zx200a.rtype == 0) {
|
|
return zx200a.rbyte0;
|
|
} else {
|
|
if (zx200a.rdychg) {
|
|
return zx200a.rbyte1;
|
|
} else {
|
|
return zx200a.rbyte0;
|
|
}
|
|
}
|
|
} else { /* write data port */
|
|
; //stop diskette operation
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* reset ZX-200A */
|
|
uint8 zx200ar7(t_bool io, uint8 data, uint8 devnum)
|
|
{
|
|
if (io == 0) { /* read data port */
|
|
;
|
|
} else { /* write data port */
|
|
zx200a_reset1();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
// perform the actual disk I/O operation
|
|
|
|
void zx200a_diskio(void)
|
|
{
|
|
uint8 cw, di, nr, ta, sa, data, nrptr;
|
|
uint16 ba;
|
|
uint32 dskoff;
|
|
uint8 fddnum, fmtb;
|
|
uint32 i;
|
|
UNIT *uptr;
|
|
uint8 *fbuf;
|
|
|
|
//parse the IOPB
|
|
cw = multibus_get_mbyte(zx200a.iopb);
|
|
di = multibus_get_mbyte(zx200a.iopb + 1);
|
|
nr = multibus_get_mbyte(zx200a.iopb + 2);
|
|
ta = multibus_get_mbyte(zx200a.iopb + 3);
|
|
sa = multibus_get_mbyte(zx200a.iopb + 4);
|
|
ba = multibus_get_mbyte(zx200a.iopb + 5);
|
|
ba |= (multibus_get_mbyte(zx200a.iopb + 6) << 8);
|
|
fddnum = (di & 0x30) >> 4;
|
|
uptr = zx200a_dev.units + fddnum;
|
|
fbuf = (uint8 *) uptr->filebuf;
|
|
//check for not ready
|
|
switch(fddnum) {
|
|
case 0:
|
|
if ((zx200a.DDstat & RDY0) == 0) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0NR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 1:
|
|
if ((zx200a.DDstat & RDY1) == 0) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0NR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 2:
|
|
if ((zx200a.DDstat & RDY2) == 0) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0NR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 3:
|
|
if ((zx200a.DDstat & RDY3) == 0) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0NR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 4:
|
|
if ((zx200a.SDstat & RDY0) == 0) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0NR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
case 5:
|
|
if ((zx200a.SDstat & RDY1) == 0) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0NR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
//check for address error
|
|
if (zx200a.fdd[fddnum].dd == 1) {
|
|
if (
|
|
((di & 0x07) != DHOME) && (
|
|
(sa > MAXSECDD) ||
|
|
((sa + nr) > (MAXSECDD + 1)) ||
|
|
(sa == 0) ||
|
|
(ta > MAXTRK)
|
|
)) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0ADR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n ZX200A: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
|
|
fddnum, sa, nr, ta, PCX);
|
|
return;
|
|
}
|
|
} else {
|
|
if (
|
|
((di & 0x07) != DHOME) && (
|
|
(sa > MAXSECSD) ||
|
|
((sa + nr) > (MAXSECSD + 1)) ||
|
|
(sa == 0) ||
|
|
(ta > MAXTRK)
|
|
)) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0ADR;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n ZX200A: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
|
|
fddnum, sa, nr, ta, PCX);
|
|
return;
|
|
}
|
|
}
|
|
switch (di & 0x07) {
|
|
case DNOP:
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
case DSEEK:
|
|
zx200a.fdd[fddnum].sec = sa;
|
|
zx200a.fdd[fddnum].cyl = ta;
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
case DHOME:
|
|
zx200a.fdd[fddnum].sec = sa;
|
|
zx200a.fdd[fddnum].cyl = 0;
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
case DVCRC:
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
case DFMT:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0WP;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Write protect error 1 on drive %d", fddnum);
|
|
return;
|
|
}
|
|
fmtb = multibus_get_mbyte(ba); //get the format byte
|
|
if (zx200a.fdd[fddnum].dd == 1) {
|
|
//calculate offset into DD disk image
|
|
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;
|
|
for(i=0; i<=((uint32)(MAXSECDD) * 128); i++) {
|
|
*(fbuf + (dskoff + i)) = fmtb;
|
|
}
|
|
} else {
|
|
//calculate offset into SD disk image
|
|
dskoff = ((ta * MAXSECSD) + (sa - 1)) * 128;
|
|
for(i=0; i<=((uint32)(MAXSECSD) * 128); i++) {
|
|
*(fbuf + (dskoff + i)) = fmtb;
|
|
}
|
|
}
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
case DREAD:
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
if (zx200a.fdd[fddnum].dd == 1) {
|
|
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;
|
|
} else {
|
|
dskoff = ((ta * MAXSECSD) + (sa - 1)) * 128;
|
|
}
|
|
//copy sector from image to RAM
|
|
for (i=0; i<128; i++) {
|
|
data = *(fbuf + (dskoff + i));
|
|
multibus_put_mbyte(ba + i, data);
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
case DWRITE:
|
|
//check for WP
|
|
if(uptr->flags & UNIT_WPMODE) {
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = RB0WP;
|
|
zx200a.intff = 1; //set interrupt FF
|
|
sim_printf("\n zx200a: Write protect error 2 on drive %d", fddnum);
|
|
return;
|
|
}
|
|
nrptr = 0;
|
|
while(nrptr < nr) {
|
|
//calculate offset into disk image
|
|
if (zx200a.fdd[fddnum].dd == 1) {
|
|
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;
|
|
} else {
|
|
dskoff = ((ta * MAXSECSD) + (sa - 1)) * 128;
|
|
}
|
|
for (i=0; i<128; i++) { //copy sector from image to RAM
|
|
data = multibus_get_mbyte(ba + i);
|
|
*(fbuf + (dskoff + i)) = data;
|
|
}
|
|
sa++;
|
|
ba+=0x80;
|
|
nrptr++;
|
|
}
|
|
zx200a.rtype = ROK;
|
|
zx200a.rbyte0 = 0; //set no error
|
|
zx200a.intff = 1; //set interrupt FF
|
|
break;
|
|
default:
|
|
sim_printf("\n zx200a: zx200a_diskio bad di=%02X", di & 0x07);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* end of zx-200a.c */
|