65402fbaa1
This summer a group of us worked together to resurrect the original ARPAnet IMP software, and I’m now happy to say that the IMP lives again in simulation. It’s possible to run the original IMP software on a modified version of the H316 simh and to set up a virtual network of simulated IMPs talking to each other. IMP to IMP connections, which would have originally been carried over leased telephone lines, are tunneled over IP. As far as we can tell, everything works pretty much as it did in the early 1970s. IMPs are able to exchange routing information, console to console communications, network statistics, and they would carry host traffic if there were hosts on the network. The hooks are in there to allow simh to support the IMP side of the 1822 host interface, and the next step would be to recover the OS for an ARPAnet era host and then extend the corresponding simulator to talk to the IMP simulation.
420 lines
15 KiB
C
420 lines
15 KiB
C
/* h316_sys.c: Honeywell 316/516 simulator interface
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Copyright (c) 1999-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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21-May-13 RLA Add IMP/TIP devices
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01-Dec-04 RMS Fixed fprint_opr calling sequence
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24-Oct-03 RMS Added DMA/DMC support
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17-Sep-01 RMS Removed multiconsole support
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*/
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#include "h316_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern UNIT cpu_unit;
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extern DEVICE ptr_dev;
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extern DEVICE ptp_dev;
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extern DEVICE tty_dev;
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extern DEVICE lpt_dev;
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extern DEVICE clk_dev;
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extern DEVICE dp_dev;
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extern DEVICE fhd_dev;
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extern DEVICE mt_dev;
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#ifdef VM_IMPTIP
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extern DEVICE rtc_dev, wdt_dev, imp_dev;
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extern DEVICE mi1_dev, mi2_dev, mi3_dev, mi4_dev, mi5_dev;
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extern DEVICE hi1_dev, hi2_dev, hi3_dev, hi4_dev;
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#endif
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extern REG cpu_reg[];
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extern uint16 M[];
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax maximum number of words for examine/deposit
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "H316";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 1;
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&ptr_dev,
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&ptp_dev,
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&lpt_dev,
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&tty_dev,
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&mt_dev,
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&clk_dev,
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&fhd_dev,
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&dp_dev,
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#ifdef VM_IMPTIP
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&wdt_dev,
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&rtc_dev,
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&imp_dev,
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&mi1_dev, &mi2_dev, &mi3_dev, &mi4_dev, &mi5_dev,
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&hi1_dev, &hi2_dev, &hi3_dev, &hi4_dev,
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#endif
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NULL
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};
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Unimplemented instruction",
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"Unimplemented I/O device",
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"HALT instruction",
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"Breakpoint",
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"Indirect address loop",
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"DMA error",
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"MT write protected",
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"DP write overrun, track destroyed",
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"DP track format invalid"
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};
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/* Binary loader
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Tbs.
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*/
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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return SCPE_FMT;
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}
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/* Symbol tables */
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#define I_V_FL 16 /* flag start */
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#define I_M_FL 07 /* flag mask */
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#define I_V_NPN 0 /* no operand */
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#define I_V_MRF 1 /* mem ref */
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#define I_V_MRX 2 /* mem ref, no idx */
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#define I_V_IOT 3 /* I/O */
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#define I_V_SHF 4 /* shift */
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#define I_V_SK0 5 /* skip 0 */
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#define I_V_SK1 6 /* skip 1 */
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#define I_NPN (I_V_NPN << I_V_FL)
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#define I_MRF (I_V_MRF << I_V_FL)
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#define I_MRX (I_V_MRX << I_V_FL)
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#define I_IOT (I_V_IOT << I_V_FL)
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#define I_SHF (I_V_SHF << I_V_FL)
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#define I_SK0 (I_V_SK0 << I_V_FL)
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#define I_SK1 (I_V_SK1 << I_V_FL)
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static const int32 masks[] = {
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0177777, 0136000, 0176000, 0176000,
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0177700, 0177000, 0177000
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};
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static const char *opcode[] = {
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"HLT", "SGL", "DBL",
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"DXA", "EXA", "RMP",
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"SCA", "INK", "NRM",
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"IAB", "ENB", "INH", "ERM",
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"CHS", "CRA", "SSP",
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"RCB", "CSA", "CMA",
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"TCA", "SSM", "SCB",
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"CAR", "CAL", "ICL",
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"AOA", "ACA", "ICR", "ICA",
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"NOP", "SKP", "SSR", "SSS",
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"JMP", "JMP*",
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"LDA", "LDA*", "ANA", "ANA*",
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"STA", "STA*", "ERA", "ERA*",
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"ADD", "ADD*", "SUB", "SUB*",
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"JST", "JST*", "CAS", "CAS*",
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"IRS", "IRS*", "IMA", "IMA*",
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"MPY", "MPY*", "DIV", "DIV*",
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"STX", "STX*", "LDX", "LDX*",
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"LRL", "LRS", "LRR",
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"LGR", "ARS", "ARR",
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"LLL", "LLS", "LLR",
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"LGL", "ALS", "ALR",
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"OCP", "SKS", "INA", "OTA",
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"SMK",
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"SPL", "SPN", "SLZ", /* encode only */
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"SZE", "SR1", "SR2",
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"SR3", "SR4", "SRC",
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"SMI", "SPS", "SLN",
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"SNZ", "SS1", "SS2",
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"SS3", "SS4", "SSC",
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NULL, NULL, /* decode only */
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NULL
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};
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static const int32 opc_val[] = {
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0000000+I_NPN, 0000005+I_NPN, 0000007+I_NPN,
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0000011+I_NPN, 0000013+I_NPN, 0000021+I_NPN,
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0000041+I_NPN, 0000043+I_NPN, 0000101+I_NPN,
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0000201+I_NPN, 0000401+I_NPN, 0001001+I_NPN, 0001401+I_NPN,
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0140024+I_NPN, 0140040+I_NPN, 0140100+I_NPN,
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0140200+I_NPN, 0140320+I_NPN, 0140401+I_NPN,
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0140407+I_NPN, 0140500+I_NPN, 0140600+I_NPN,
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0141044+I_NPN, 0141050+I_NPN, 0141140+I_NPN,
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0141206+I_NPN, 0141216+I_NPN, 0141240+I_NPN, 0141340+I_NPN,
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0101000+I_NPN, 0100000+I_NPN, 0100036+I_NPN, 0101036+I_NPN,
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0002000+I_MRF, 0102000+I_MRF,
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0004000+I_MRF, 0104000+I_MRF, 0006000+I_MRF, 0106000+I_MRF,
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0010000+I_MRF, 0110000+I_MRF, 0012000+I_MRF, 0112000+I_MRF,
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0014000+I_MRF, 0114000+I_MRF, 0016000+I_MRF, 0116000+I_MRF,
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0020000+I_MRF, 0120000+I_MRF, 0022000+I_MRF, 0122000+I_MRF,
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0024000+I_MRF, 0124000+I_MRF, 0026000+I_MRF, 0126000+I_MRF,
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0034000+I_MRF, 0134000+I_MRF, 0036000+I_MRF, 0136000+I_MRF,
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0032000+I_MRX, 0132000+I_MRX, 0072000+I_MRX, 0172000+I_MRX,
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0040000+I_SHF, 0040100+I_SHF, 0040200+I_SHF,
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0040400+I_SHF, 0040500+I_SHF, 0040600+I_SHF,
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0041000+I_SHF, 0041100+I_SHF, 0041200+I_SHF,
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0041400+I_SHF, 0041500+I_SHF, 0041600+I_SHF,
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0030000+I_IOT, 0070000+I_IOT, 0130000+I_IOT, 0170000+I_IOT,
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0170000+I_IOT,
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0100400+I_SK0, 0100200+I_SK0, 0100100+I_SK0, /* encode only */
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0100040+I_SK0, 0100020+I_SK0, 0100010+I_SK0,
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0100004+I_SK0, 0100002+I_SK0, 0100001+I_SK0,
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0101400+I_SK1, 0101200+I_SK1, 0101100+I_SK1,
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0101040+I_SK1, 0101020+I_SK1, 0101010+I_SK1,
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0101004+I_SK1, 0101002+I_SK1, 0101001+I_SK1,
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0100000+I_SK0, 0101000+I_SK1, /* decode only */
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-1
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};
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/* Operate decode
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Inputs:
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*of = output stream
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inst = mask bits
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class = instruction class code
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sp = space needed?
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Outputs:
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status = space needed
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*/
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void fprint_opr (FILE *of, int32 inst, int32 class)
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{
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int32 i, j, sp;
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for (i = sp = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
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j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
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if ((j == class) && (opc_val[i] & inst)) { /* same class? */
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inst = inst & ~opc_val[i]; /* mask bit set? */
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fprintf (of, (sp? " %s": "%s"), opcode[i]);
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sp = 1;
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}
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}
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return;
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}
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/* Symbolic decode
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Inputs:
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*of = output stream
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addr = current PC
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*val = pointer to data
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*uptr = pointer to unit
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sw = switches
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Outputs:
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return = status code
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*/
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#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw)
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{
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int32 cflag, i, j, inst, disp;
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cflag = (uptr == NULL) || (uptr == &cpu_unit);
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inst = val[0];
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if (sw & SWMASK ('A')) { /* ASCII? */
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if (inst > 0377)
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return SCPE_ARG;
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK;
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}
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if (sw & SWMASK ('C')) { /* characters? */
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fprintf (of, FMTASC ((inst >> 8) & 0177));
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK;
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}
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if (!(sw & SWMASK ('M')))
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return SCPE_ARG;
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/* Instruction decode */
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for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
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j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
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if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
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switch (j) { /* case on class */
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case I_V_NPN: /* no operands */
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fprintf (of, "%s", opcode[i]); /* opcode */
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break;
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case I_V_MRF: case I_V_MRX: /* mem ref */
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disp = inst & DISP; /* displacement */
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fprintf (of, "%s ", opcode[i]); /* opcode */
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if (inst & SC) { /* current sector? */
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if (cflag)
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fprintf (of, "%-o", (addr & PAGENO) | disp);
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else fprintf (of, "C %-o", disp);
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}
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else fprintf (of, "%-o", disp); /* sector zero */
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if ((j == I_V_MRF) && (inst & IDX))
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fprintf (of, ",1");
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break;
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case I_V_IOT: /* I/O */
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disp = inst & 01777; /* pulse+dev */
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fprintf (of, "%s %o", opcode[i], disp);
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break;
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case I_V_SHF: /* shift */
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disp = -inst & SHFMASK; /* shift count */
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fprintf (of, "%s %o", opcode[i], disp);
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break;
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case I_V_SK0: case I_V_SK1: /* skips */
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fprint_opr (of, inst & 0777, j); /* print skips */
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break;
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} /* end case */
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return SCPE_OK;
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} /* end if */
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} /* end for */
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return SCPE_ARG;
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}
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/* Symbolic input
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Inputs:
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*cptr = pointer to input string
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addr = current PC
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*uptr = pointer to unit
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*val = pointer to output values
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sw = switches
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Outputs:
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status = error status
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*/
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t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
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{
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int32 cflag, d, i, j, k;
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t_stat r;
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char gbuf[CBUFSIZE];
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cflag = (uptr == NULL) || (uptr == &cpu_unit);
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while (isspace (*cptr)) cptr++; /* absorb spaces */
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if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
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if (cptr[0] == 0) /* must have 1 char */
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return SCPE_ARG;
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val[0] = (t_value) cptr[0] & 0177;
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return SCPE_OK;
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}
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if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* char string? */
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if (cptr[0] == 0) /* must have 1 char */
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return SCPE_ARG;
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val[0] = (((t_value) cptr[0] & 0177) << 8) |
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((t_value) cptr[1] & 0177);
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return SCPE_OK;
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}
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/* Instruction parse */
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cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
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for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
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if (opcode[i] == NULL)
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return SCPE_ARG;
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val[0] = opc_val[i] & DMASK; /* get value */
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j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
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switch (j) { /* case on class */
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case I_V_NPN: /* no operand */
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break;
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case I_V_IOT: /* IOT */
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cptr = get_glyph (cptr, gbuf, 0); /* get pulse+dev */
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d = get_uint (gbuf, 8, 01777, &r);
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if (r != SCPE_OK)
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return SCPE_ARG;
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val[0] = val[0] | d;
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break;
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case I_V_SHF: /* shift */
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cptr = get_glyph (cptr, gbuf, 0); /* get shift count */
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d = get_uint (gbuf, 8, SHFMASK, &r);
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if (r != SCPE_OK)
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return SCPE_ARG;
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val[0] = val[0] | (-d & SHFMASK); /* store 2's comp */
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break;
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case I_V_MRF: case I_V_MRX: /* mem ref */
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cptr = get_glyph (cptr, gbuf, ','); /* get next field */
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if ((k = (strcmp (gbuf, "C") == 0))) { /* C specified? */
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val[0] = val[0] | SC;
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cptr = get_glyph (cptr, gbuf, 0);
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}
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else if ((k = (strcmp (gbuf, "Z") == 0))) { /* Z specified? */
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cptr = get_glyph (cptr, gbuf, ',');
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}
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d = get_uint (gbuf, 8, X_AMASK, &r); /* construe as addr */
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if (r != SCPE_OK)
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return SCPE_ARG;
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if (d <= DISP) /* fits? */
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val[0] = val[0] | d;
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else if (cflag && !k && (((addr ^ d) & PAGENO) == 0))
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val[0] = val[0] | (d & DISP) | SC;
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else return SCPE_ARG;
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if ((j == I_V_MRX) || (*cptr == 0)) /* indexed? */
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break;
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cptr = get_glyph (cptr, gbuf, 0);
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d = get_uint (gbuf, 8, 1, &r); /* get tag */
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if (r != SCPE_OK)
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return SCPE_ARG;
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if (d) /* or in index */
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val[0] = val[0] | IDX;
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break;
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case I_V_SK0: case I_V_SK1: /* skips */
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for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
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cptr = get_glyph (cptr, gbuf, 0)) {
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for (i = 0; (opcode[i] != NULL) &&
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(strcmp (opcode[i], gbuf) != 0) ; i++) ;
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k = opc_val[i] & DMASK;
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if ((opcode[i] == NULL) || (((k ^ val[0]) & 0177000) != 0))
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return SCPE_ARG;
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val[0] = val[0] | k;
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}
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break;
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} /* end case */
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if (*cptr != 0) /* junk at end? */
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return SCPE_ARG;
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return SCPE_OK;
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}
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