a12e4a1c39
The source set has been extensively overhauled. For correct viewing, set Visual C++ or Emacs to have tab stops every 4 characters. 1. New Features 1.1 3.5-0 1.1.1 All Ethernet devices - Added Windows user-defined adapter names (from Timothe Litt) 1.1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors - Added support for SET <unit>n DISCONNECT 1.1.3 VAX - Added latent QDSS support - Revised autoconfigure to handle QDSS 1.1.4 PDP-11 - Revised autoconfigure to handle more cases 1.2 3.5-1 No new features 1.3 3.5-2 1.3.1 All ASCII terminals - Most ASCII terminal emulators have supported 7-bit and 8-bit operation; where required, they have also supported an upper- case only or KSR-emulation mode. This release adds a new mode, 7P, for 7-bit printing characters. In 7P mode, non-printing characters in the range 0-31 (decimal), and 127 (decimal), are automatically suppressed. This prevents printing of fill characters under Windows. The printable character set for ASCII code values 0-31 can be changed with the SET CONSOLE PCHAR command. Code value 127 (DELETE) is always suppressed. 1.3.2 VAX-11/780 - First release. The VAX-11/780 has successfully run VMS V7.2. The commercial instructions and compatability mode have not been extensively tested. The Ethernet controller is not working yet and is disabled. 2. Bugs Fixed 2.1 3.5-0 2.1.1 SCP and libraries - Trim trailing spaces on all input (for example, attach file names) - Fixed sim_sock spurious SIGPIPE error in Unix/Linux - Fixed sim_tape misallocation of TPC map array for 64b simulators 2.1.2 1401 - Fixed bug, CPU reset was clearing SSB through SSG 2.1.3 PDP-11 - Fixed bug in VH vector display routine - Fixed XU runt packet processing (found by Tim Chapman) 2.1.4 Interdata - Fixed bug in SHOW PAS CONN/STATS - Fixed potential integer overflow exception in divide 2.1.5 SDS - Fixed bug in SHOW MUX CONN/STATS 2.1.6 HP - Fixed bug in SHOW MUX CONN/STATS 2.1.7 PDP-8 - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.1.8 PDP-18b - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.1.9 Nova, Eclipse - Fixed potential integer overflow exception in divide 2.2 3.5-1 2.2.1 1401 - Changed character encodings to be compatible with Pierce 709X simulator - Added mode for old/new character encodings 2.2.2 1620 - Changed character encodings to be compatible with Pierce 709X simulator 2.2.3 PDP-10 - Changed MOVNI to eliminate GCC warning 2.2.4 VAX - Fixed bug in structure definitions with 32b compilation options - Fixed bug in autoconfiguration table 2.2.5 PDP-11 - Fixed bug in autoconfiguration table 2.3 3.5-2 2.3.1 PDP-10 - RP: fixed drive clear not to clear disk address 2.3.2 PDP-11 (VAX, VAX-11/780, for shared peripherals) - HK: fixed overlap seek interaction with drive select, drive clear, etc - RQ, TM, TQ, TS, TU: widened address display to 64b when USE_ADDR64 option selected - TU: changed default adapter from TM02 to TM03 (required by VMS) - RP: fixed drive clear not to clear disk address - RP, TU: fixed device enable/disable to enabled/disable Massbus adapter as well - XQ: fixed register access alignment bug (found by Doug Carman) 2.3.3 PDP-8 - RL: fixed IOT 61 decoding bug (found by David Gesswein) - DF, DT, RF: fixed register access alignment bug (found by Doug Carman) 2.3.4 VAX - Fixed CVTfi to trap on integer overflow if PSW<iv> is set - Fixed breakpoint detection when USE_ADDR64 option selected
724 lines
29 KiB
C
724 lines
29 KiB
C
/* pdp11_dz.c: DZ11 terminal multiplexor simulator
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Copyright (c) 2001-2005, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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dz DZ11 terminal multiplexor
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22-Nov-05 RMS Revised for new terminal processing routines
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07-Jul-05 RMS Removed extraneous externs
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15-Jun-05 RMS Revised for new autoconfigure interface
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04-Apr-04 RMS Added per-line logging
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05-Jan-04 RMS Revised for tmxr library changes
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19-May-03 RMS Revised for new conditional compilation scheme
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09-May-03 RMS Added network device flag
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22-Dec-02 RMS Added break (framing error) support
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31-Oct-02 RMS Added 8b support
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12-Oct-02 RMS Added autoconfigure support
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29-Sep-02 RMS Fixed bug in set number of lines routine
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Added variable vector support
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New data structures
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22-Apr-02 RMS Updated for changes in sim_tmxr
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28-Apr-02 RMS Fixed interrupt acknowledge, fixed SHOW DZ ADDRESS
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14-Jan-02 RMS Added multiboard support
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30-Dec-01 RMS Added show statistics, set disconnect
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Removed statistics registers
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03-Dec-01 RMS Modified for extended SET/SHOW
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09-Nov-01 RMS Added VAX support
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20-Oct-01 RMS Moved getchar from sim_tmxr, changed interrupt
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logic to use tmxr_rqln
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06-Oct-01 RMS Fixed bug in carrier detect logic
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03-Oct-01 RMS Added support for BSD-style "ringless" modems
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27-Sep-01 RMS Fixed bug in xmte initialization
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17-Sep-01 RMS Added separate autodisconnect switch
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16-Sep-01 RMS Fixed modem control bit offsets
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*/
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#if defined (VM_PDP10) /* PDP10 version */
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#include "pdp10_defs.h"
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#define RANK_DZ 0 /* no autoconfig */
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#define DZ_8B_DFLT 0
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extern int32 int_req;
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#elif defined (VM_VAX) /* VAX version */
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#include "vax_defs.h"
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#define DZ_8B_DFLT TT_MODE_8B
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extern int32 int_req[IPL_HLVL];
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#else /* PDP-11 version */
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#include "pdp11_defs.h"
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#define DZ_8B_DFLT TT_MODE_8B
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extern int32 int_req[IPL_HLVL];
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#endif
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#if !defined (DZ_MUXES)
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#define DZ_MUXES 1
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#endif
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#if !defined (DZ_LINES)
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#define DZ_LINES 8
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#endif
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#define DZ_MNOMASK (DZ_MUXES - 1) /* mask for mux no */
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#define DZ_LNOMASK (DZ_LINES - 1) /* mask for lineno */
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#define DZ_LMASK ((1 << DZ_LINES) - 1) /* mask of lines */
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#define DZ_SILO_ALM 16 /* silo alarm level */
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/* DZCSR - 160100 - control/status register */
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#define CSR_MAINT 0000010 /* maint - NI */
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#define CSR_CLR 0000020 /* clear */
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#define CSR_MSE 0000040 /* master scan enb */
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#define CSR_RIE 0000100 /* rcv int enb */
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#define CSR_RDONE 0000200 /* rcv done - RO */
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#define CSR_V_TLINE 8 /* xmit line - RO */
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#define CSR_TLINE (DZ_LNOMASK << CSR_V_TLINE)
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#define CSR_SAE 0010000 /* silo alm enb */
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#define CSR_SA 0020000 /* silo alm - RO */
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#define CSR_TIE 0040000 /* xmit int enb */
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#define CSR_TRDY 0100000 /* xmit rdy - RO */
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#define CSR_RW (CSR_MSE | CSR_RIE | CSR_SAE | CSR_TIE)
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#define CSR_MBZ (0004003 | CSR_CLR | CSR_MAINT)
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#define CSR_GETTL(x) (((x) >> CSR_V_TLINE) & DZ_LNOMASK)
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#define CSR_PUTTL(x,y) x = ((x) & ~CSR_TLINE) | (((y) & DZ_LNOMASK) << CSR_V_TLINE)
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/* DZRBUF - 160102 - receive buffer, read only */
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#define RBUF_CHAR 0000377 /* rcv char */
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#define RBUF_V_RLINE 8 /* rcv line */
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#define RBUF_PARE 0010000 /* parity err - NI */
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#define RBUF_FRME 0020000 /* frame err */
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#define RBUF_OVRE 0040000 /* overrun err - NI */
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#define RBUF_VALID 0100000 /* rcv valid */
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#define RBUF_MBZ 0004000
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/* DZLPR - 160102 - line parameter register, write only, word access only */
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#define LPR_V_LINE 0 /* line */
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#define LPR_LPAR 0007770 /* line pars - NI */
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#define LPR_RCVE 0010000 /* receive enb */
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#define LPR_GETLN(x) (((x) >> LPR_V_LINE) & DZ_LNOMASK)
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/* DZTCR - 160104 - transmission control register */
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#define TCR_V_XMTE 0 /* xmit enables */
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#define TCR_V_DTR 8 /* DTRs */
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/* DZMSR - 160106 - modem status register, read only */
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#define MSR_V_RI 0 /* ring indicators */
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#define MSR_V_CD 8 /* carrier detect */
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/* DZTDR - 160106 - transmit data, write only */
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#define TDR_CHAR 0000377 /* xmit char */
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#define TDR_V_TBR 8 /* xmit break - NI */
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extern int32 IREQ (HLVL);
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extern int32 sim_switches;
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extern FILE *sim_log;
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extern int32 tmxr_poll; /* calibrated delay */
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uint16 dz_csr[DZ_MUXES] = { 0 }; /* csr */
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uint16 dz_rbuf[DZ_MUXES] = { 0 }; /* rcv buffer */
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uint16 dz_lpr[DZ_MUXES] = { 0 }; /* line param */
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uint16 dz_tcr[DZ_MUXES] = { 0 }; /* xmit control */
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uint16 dz_msr[DZ_MUXES] = { 0 }; /* modem status */
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uint16 dz_tdr[DZ_MUXES] = { 0 }; /* xmit data */
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uint8 dz_sae[DZ_MUXES] = { 0 }; /* silo alarm enabled */
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uint32 dz_rxi = 0; /* rcv interrupts */
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uint32 dz_txi = 0; /* xmt interrupts */
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int32 dz_mctl = 0; /* modem ctrl enabled */
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int32 dz_auto = 0; /* autodiscon enabled */
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TMLN dz_ldsc[DZ_MUXES * DZ_LINES] = { 0 }; /* line descriptors */
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TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, dz_ldsc }; /* mux descriptor */
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DEVICE dz_dev;
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t_stat dz_rd (int32 *data, int32 PA, int32 access);
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t_stat dz_wr (int32 data, int32 PA, int32 access);
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int32 dz_rxinta (void);
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int32 dz_txinta (void);
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t_stat dz_svc (UNIT *uptr);
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t_stat dz_reset (DEVICE *dptr);
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t_stat dz_attach (UNIT *uptr, char *cptr);
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t_stat dz_detach (UNIT *uptr);
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t_stat dz_clear (int32 dz, t_bool flag);
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int32 dz_getc (int32 dz);
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void dz_update_rcvi (void);
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void dz_update_xmti (void);
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void dz_clr_rxint (int32 dz);
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void dz_set_rxint (int32 dz);
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void dz_clr_txint (int32 dz);
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void dz_set_txint (int32 dz);
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t_stat dz_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dz_show (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dz_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dz_setnl (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat dz_set_log (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat dz_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
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/* DZ data structures
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dz_dev DZ device descriptor
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dz_unit DZ unit list
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dz_reg DZ register list
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*/
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DIB dz_dib = {
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IOBA_DZ, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr,
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2, IVCL (DZRX), VEC_DZRX, { &dz_rxinta, &dz_txinta }
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};
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UNIT dz_unit = { UDATA (&dz_svc, UNIT_ATTABLE + DZ_8B_DFLT, 0) };
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REG dz_nlreg = { DRDATA (NLINES, dz_desc.lines, 6), PV_LEFT };
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REG dz_reg[] = {
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{ BRDATA (CSR, dz_csr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (RBUF, dz_rbuf, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (LPR, dz_lpr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (TCR, dz_tcr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (MSR, dz_msr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (TDR, dz_tdr, DEV_RDX, 16, DZ_MUXES) },
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{ BRDATA (SAENB, dz_sae, DEV_RDX, 1, DZ_MUXES) },
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{ GRDATA (RXINT, dz_rxi, DEV_RDX, DZ_MUXES, 0) },
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{ GRDATA (TXINT, dz_txi, DEV_RDX, DZ_MUXES, 0) },
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{ FLDATA (MDMCTL, dz_mctl, 0) },
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{ FLDATA (AUTODS, dz_auto, 0) },
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{ GRDATA (DEVADDR, dz_dib.ba, DEV_RDX, 32, 0), REG_HRO },
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{ GRDATA (DEVVEC, dz_dib.vec, DEV_RDX, 16, 0), REG_HRO },
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{ NULL }
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};
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MTAB dz_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &dz_desc },
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{ UNIT_ATT, UNIT_ATT, "connections", NULL, NULL, &dz_summ },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
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NULL, &dz_show, NULL },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
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NULL, &dz_show, NULL },
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{ MTAB_XTD|MTAB_VDV, 010, "ADDRESS", "ADDRESS",
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&set_addr, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
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&set_vec, &dz_show_vec, NULL },
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#if !defined (VM_PDP10)
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
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&set_addr_flt, NULL, NULL },
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#endif
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{ MTAB_XTD | MTAB_VDV | MTAB_VAL, 0, "lines", "LINES",
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&dz_setnl, NULL, &dz_nlreg },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "LOG",
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&dz_set_log, NULL, &dz_desc },
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{ MTAB_XTD | MTAB_VDV, 0, NULL, "NOLOG",
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&dz_set_nolog, NULL, &dz_desc },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "LOG", NULL,
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NULL, &dz_show_log, &dz_desc },
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{ 0 }
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};
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DEVICE dz_dev = {
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"DZ", &dz_unit, dz_reg, dz_mod,
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1, DEV_RDX, 8, 1, DEV_RDX, 8,
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&tmxr_ex, &tmxr_dep, &dz_reset,
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NULL, &dz_attach, &dz_detach,
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&dz_dib, DEV_FLTA | DEV_DISABLE | DEV_NET | DEV_UBUS | DEV_QBUS
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};
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/* IO dispatch routines, I/O addresses 177601x0 - 177601x7 */
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t_stat dz_rd (int32 *data, int32 PA, int32 access)
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{
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int32 dz = ((PA - dz_dib.ba) >> 3) & DZ_MNOMASK; /* get mux num */
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switch ((PA >> 1) & 03) { /* case on PA<2:1> */
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case 00: /* CSR */
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*data = dz_csr[dz] = dz_csr[dz] & ~CSR_MBZ;
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break;
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case 01: /* RBUF */
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dz_csr[dz] = dz_csr[dz] & ~CSR_SA; /* clr silo alarm */
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if (dz_csr[dz] & CSR_MSE) { /* scanner on? */
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dz_rbuf[dz] = dz_getc (dz); /* get top of silo */
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if (!dz_rbuf[dz]) dz_sae[dz] = 1; /* empty? re-enable */
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tmxr_poll_rx (&dz_desc); /* poll input */
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dz_update_rcvi (); /* update rx intr */
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}
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else {
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dz_rbuf[dz] = 0; /* no data */
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dz_update_rcvi (); /* no rx intr */
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}
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*data = dz_rbuf[dz];
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break;
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case 02: /* TCR */
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*data = dz_tcr[dz];
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break;
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case 03: /* MSR */
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*data = dz_msr[dz];
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break;
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}
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return SCPE_OK;
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}
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t_stat dz_wr (int32 data, int32 PA, int32 access)
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{
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int32 dz = ((PA - dz_dib.ba) >> 3) & DZ_MNOMASK; /* get mux num */
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int32 i, c, line;
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TMLN *lp;
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switch ((PA >> 1) & 03) { /* case on PA<2:1> */
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case 00: /* CSR */
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if (access == WRITEB) data = (PA & 1)? /* byte? merge */
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(dz_csr[dz] & 0377) | (data << 8):
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(dz_csr[dz] & ~0377) | data;
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if (data & CSR_CLR) dz_clear (dz, FALSE); /* clr? reset */
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if (data & CSR_MSE) sim_activate (&dz_unit, tmxr_poll);
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else dz_csr[dz] &= ~(CSR_SA | CSR_RDONE | CSR_TRDY);
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if ((data & CSR_RIE) == 0) dz_clr_rxint (dz); /* RIE = 0? */
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else if (((dz_csr[dz] & CSR_IE) == 0) && /* RIE 0->1? */
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((dz_csr[dz] & CSR_SAE)?
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(dz_csr[dz] & CSR_SA): (dz_csr[dz] & CSR_RDONE)))
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dz_set_rxint (dz);
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if ((data & CSR_TIE) == 0) dz_clr_txint (dz); /* TIE = 0? */
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else if (((dz_csr[dz] & CSR_TIE) == 0) && (dz_csr[dz] & CSR_TRDY))
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dz_set_txint (dz);
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dz_csr[dz] = (dz_csr[dz] & ~CSR_RW) | (data & CSR_RW);
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break;
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case 01: /* LPR */
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dz_lpr[dz] = data;
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line = (dz * DZ_LINES) + LPR_GETLN (data); /* get line num */
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lp = &dz_ldsc[line]; /* get line desc */
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if (dz_lpr[dz] & LPR_RCVE) lp->rcve = 1; /* rcv enb? on */
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else lp->rcve = 0; /* else line off */
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tmxr_poll_rx (&dz_desc); /* poll input */
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dz_update_rcvi (); /* update rx intr */
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break;
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case 02: /* TCR */
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if (access == WRITEB) data = (PA & 1)? /* byte? merge */
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(dz_tcr[dz] & 0377) | (data << 8):
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(dz_tcr[dz] & ~0377) | data;
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if (dz_mctl) { /* modem ctl? */
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dz_msr[dz] |= ((data & 0177400) & /* dcd |= dtr & ring */
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((dz_msr[dz] & DZ_LMASK) << MSR_V_CD));
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dz_msr[dz] &= ~(data >> TCR_V_DTR); /* ring &= ~dtr */
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if (dz_auto) { /* auto disconnect? */
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int32 drop;
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drop = (dz_tcr[dz] & ~data) >> TCR_V_DTR; /* drop = dtr & ~data */
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for (i = 0; i < DZ_LINES; i++) { /* drop hangups */
|
|
line = (dz * DZ_LINES) + i; /* get line num */
|
|
lp = &dz_ldsc[line]; /* get line desc */
|
|
if (lp->conn && (drop & (1 << i))) {
|
|
tmxr_linemsg (lp, "\r\nLine hangup\r\n");
|
|
tmxr_reset_ln (lp); /* reset line, cdet */
|
|
dz_msr[dz] &= ~(1 << (i + MSR_V_CD));
|
|
} /* end if drop */
|
|
} /* end for */
|
|
} /* end if auto */
|
|
} /* end if modem */
|
|
dz_tcr[dz] = data;
|
|
tmxr_poll_tx (&dz_desc); /* poll output */
|
|
dz_update_xmti (); /* update int */
|
|
break;
|
|
|
|
case 03: /* TDR */
|
|
if (PA & 1) { /* odd byte? */
|
|
dz_tdr[dz] = (dz_tdr[dz] & 0377) | (data << 8); /* just save */
|
|
break;
|
|
}
|
|
dz_tdr[dz] = data;
|
|
if (dz_csr[dz] & CSR_MSE) { /* enabled? */
|
|
line = (dz * DZ_LINES) + CSR_GETTL (dz_csr[dz]);
|
|
lp = &dz_ldsc[line]; /* get line desc */
|
|
c = sim_tt_outcvt (dz_tdr[dz], TT_GET_MODE (dz_unit.flags));
|
|
if (c >= 0) tmxr_putc_ln (lp, c); /* store char */
|
|
tmxr_poll_tx (&dz_desc); /* poll output */
|
|
dz_update_xmti (); /* update int */
|
|
}
|
|
break;
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Unit service routine
|
|
|
|
The DZ11 polls to see if asynchronous activity has occurred and now
|
|
needs to be processed. The polling interval is controlled by the clock
|
|
simulator, so for most environments, it is calibrated to real time.
|
|
Typical polling intervals are 50-60 times per second.
|
|
|
|
The simulator assumes that software enables all of the multiplexors,
|
|
or none of them.
|
|
*/
|
|
|
|
t_stat dz_svc (UNIT *uptr)
|
|
{
|
|
int32 dz, t, newln;
|
|
|
|
for (dz = t = 0; dz < DZ_MUXES; dz++) /* check enabled */
|
|
t = t | (dz_csr[dz] & CSR_MSE);
|
|
if (t) { /* any enabled? */
|
|
newln = tmxr_poll_conn (&dz_desc); /* poll connect */
|
|
if ((newln >= 0) && dz_mctl) { /* got a live one? */
|
|
dz = newln / DZ_LINES; /* get mux num */
|
|
if (dz_tcr[dz] & (1 << (newln + TCR_V_DTR))) /* DTR set? */
|
|
dz_msr[dz] |= (1 << (newln + MSR_V_CD)); /* set cdet */
|
|
else dz_msr[dz] |= (1 << newln); /* set ring */
|
|
}
|
|
tmxr_poll_rx (&dz_desc); /* poll input */
|
|
dz_update_rcvi (); /* upd rcv intr */
|
|
tmxr_poll_tx (&dz_desc); /* poll output */
|
|
dz_update_xmti (); /* upd xmt intr */
|
|
sim_activate (uptr, tmxr_poll); /* reactivate */
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Get first available character for mux, if any */
|
|
|
|
int32 dz_getc (int32 dz)
|
|
{
|
|
uint32 i, line, c;
|
|
|
|
for (i = c = 0; (i < DZ_LINES) && (c == 0); i++) { /* loop thru lines */
|
|
line = (dz * DZ_LINES) + i; /* get line num */
|
|
c = tmxr_getc_ln (&dz_ldsc[line]); /* test for input */
|
|
if (c & SCPE_BREAK) c = RBUF_VALID | RBUF_FRME; /* break? frame err */
|
|
if (c) c = c | (i << RBUF_V_RLINE); /* or in line # */
|
|
} /* end for */
|
|
return c;
|
|
}
|
|
|
|
/* Update receive interrupts */
|
|
|
|
void dz_update_rcvi (void)
|
|
{
|
|
int32 i, dz, line, scnt[DZ_MUXES];
|
|
TMLN *lp;
|
|
|
|
for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
|
|
scnt[dz] = 0; /* clr input count */
|
|
for (i = 0; i < DZ_LINES; i++) { /* poll lines */
|
|
line = (dz * DZ_LINES) + i; /* get line num */
|
|
lp = &dz_ldsc[line]; /* get line desc */
|
|
scnt[dz] = scnt[dz] + tmxr_rqln (lp); /* sum buffers */
|
|
if (dz_mctl && !lp->conn) /* if disconn */
|
|
dz_msr[dz] &= ~(1 << (i + MSR_V_CD)); /* reset car det */
|
|
}
|
|
}
|
|
for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
|
|
if (scnt[dz] && (dz_csr[dz] & CSR_MSE)) { /* input & enabled? */
|
|
dz_csr[dz] |= CSR_RDONE; /* set done */
|
|
if (dz_sae[dz] && (scnt[dz] >= DZ_SILO_ALM)) { /* alm enb & cnt hi? */
|
|
dz_csr[dz] |= CSR_SA; /* set status */
|
|
dz_sae[dz] = 0; /* disable alarm */
|
|
}
|
|
}
|
|
else dz_csr[dz] &= ~CSR_RDONE; /* no, clear done */
|
|
if ((dz_csr[dz] & CSR_RIE) && /* int enable */
|
|
((dz_csr[dz] & CSR_SAE)?
|
|
(dz_csr[dz] & CSR_SA): (dz_csr[dz] & CSR_RDONE)))
|
|
dz_set_rxint (dz); /* and alm/done? */
|
|
else dz_clr_rxint (dz); /* no, clear int */
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Update transmit interrupts */
|
|
|
|
void dz_update_xmti (void)
|
|
{
|
|
int32 dz, linemask, i, j, line;
|
|
|
|
for (dz = 0; dz < DZ_MUXES; dz++) { /* loop thru muxes */
|
|
linemask = dz_tcr[dz] & DZ_LMASK; /* enabled lines */
|
|
dz_csr[dz] &= ~CSR_TRDY; /* assume not rdy */
|
|
j = CSR_GETTL (dz_csr[dz]); /* start at current */
|
|
for (i = 0; i < DZ_LINES; i++) { /* loop thru lines */
|
|
j = (j + 1) & DZ_LNOMASK; /* next line */
|
|
line = (dz * DZ_LINES) + j; /* get line num */
|
|
if ((linemask & (1 << j)) && dz_ldsc[line].xmte) {
|
|
CSR_PUTTL (dz_csr[dz], j); /* put ln in csr */
|
|
dz_csr[dz] |= CSR_TRDY; /* set xmt rdy */
|
|
break;
|
|
}
|
|
}
|
|
if ((dz_csr[dz] & CSR_TIE) && (dz_csr[dz] & CSR_TRDY)) /* ready plus int? */
|
|
dz_set_txint (dz);
|
|
else dz_clr_txint (dz); /* no int req */
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Interrupt routines */
|
|
|
|
void dz_clr_rxint (int32 dz)
|
|
{
|
|
dz_rxi = dz_rxi & ~(1 << dz); /* clr mux rcv int */
|
|
if (dz_rxi == 0) CLR_INT (DZRX); /* all clr? */
|
|
else SET_INT (DZRX); /* no, set intr */
|
|
return;
|
|
}
|
|
|
|
void dz_set_rxint (int32 dz)
|
|
{
|
|
dz_rxi = dz_rxi | (1 << dz); /* set mux rcv int */
|
|
SET_INT (DZRX); /* set master intr */
|
|
return;
|
|
}
|
|
|
|
int32 dz_rxinta (void)
|
|
{
|
|
int32 dz;
|
|
|
|
for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */
|
|
if (dz_rxi & (1 << dz)) {
|
|
dz_clr_rxint (dz); /* clear intr */
|
|
return (dz_dib.vec + (dz * 010)); /* return vector */
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void dz_clr_txint (int32 dz)
|
|
{
|
|
dz_txi = dz_txi & ~(1 << dz); /* clr mux xmt int */
|
|
if (dz_txi == 0) CLR_INT (DZTX); /* all clr? */
|
|
else SET_INT (DZTX); /* no, set intr */
|
|
return;
|
|
}
|
|
|
|
void dz_set_txint (int32 dz)
|
|
{
|
|
dz_txi = dz_txi | (1 << dz); /* set mux xmt int */
|
|
SET_INT (DZTX); /* set master intr */
|
|
return;
|
|
}
|
|
|
|
int32 dz_txinta (void)
|
|
{
|
|
int32 dz;
|
|
|
|
for (dz = 0; dz < DZ_MUXES; dz++) { /* find 1st mux */
|
|
if (dz_txi & (1 << dz)) {
|
|
dz_clr_txint (dz); /* clear intr */
|
|
return (dz_dib.vec + 4 + (dz * 010)); /* return vector */
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Device reset */
|
|
|
|
t_stat dz_clear (int32 dz, t_bool flag)
|
|
{
|
|
int32 i, line;
|
|
|
|
dz_csr[dz] = 0; /* clear CSR */
|
|
dz_rbuf[dz] = 0; /* silo empty */
|
|
dz_lpr[dz] = 0; /* no params */
|
|
if (flag) dz_tcr[dz] = 0; /* INIT? clr all */
|
|
else dz_tcr[dz] &= ~0377; /* else save dtr */
|
|
dz_tdr[dz] = 0;
|
|
dz_sae[dz] = 1; /* alarm on */
|
|
dz_clr_rxint (dz); /* clear int */
|
|
dz_clr_txint (dz);
|
|
for (i = 0; i < DZ_LINES; i++) { /* loop thru lines */
|
|
line = (dz * DZ_LINES) + i;
|
|
if (!dz_ldsc[line].conn) dz_ldsc[line].xmte = 1; /* set xmt enb */
|
|
dz_ldsc[line].rcve = 0; /* clr rcv enb */
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat dz_reset (DEVICE *dptr)
|
|
{
|
|
int32 i, ndev;
|
|
|
|
for (i = 0; i < DZ_MUXES; i++) dz_clear (i, TRUE); /* init muxes */
|
|
dz_rxi = dz_txi = 0; /* clr master int */
|
|
CLR_INT (DZRX);
|
|
CLR_INT (DZTX);
|
|
sim_cancel (&dz_unit); /* stop poll */
|
|
ndev = ((dptr->flags & DEV_DIS)? 0: (dz_desc.lines / DZ_LINES));
|
|
return auto_config (dptr->name, ndev); /* auto config */
|
|
}
|
|
|
|
/* Attach */
|
|
|
|
t_stat dz_attach (UNIT *uptr, char *cptr)
|
|
{
|
|
t_stat r;
|
|
extern int32 sim_switches;
|
|
|
|
dz_mctl = dz_auto = 0; /* modem ctl off */
|
|
r = tmxr_attach (&dz_desc, uptr, cptr); /* attach mux */
|
|
if (r != SCPE_OK) return r; /* error? */
|
|
if (sim_switches & SWMASK ('M')) { /* modem control? */
|
|
dz_mctl = 1;
|
|
printf ("Modem control activated\n");
|
|
if (sim_log) fprintf (sim_log, "Modem control activated\n");
|
|
if (sim_switches & SWMASK ('A')) { /* autodisconnect? */
|
|
dz_auto = 1;
|
|
printf ("Auto disconnect activated\n");
|
|
if (sim_log) fprintf (sim_log, "Auto disconnect activated\n");
|
|
}
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Detach */
|
|
|
|
t_stat dz_detach (UNIT *uptr)
|
|
{
|
|
return tmxr_detach (&dz_desc, uptr);
|
|
}
|
|
|
|
/* Show summary processor */
|
|
|
|
t_stat dz_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
int32 i, t;
|
|
|
|
for (i = t = 0; i < dz_desc.lines; i++) { /* get num conn */
|
|
if (dz_ldsc[i].conn) t = t + 1;
|
|
}
|
|
if (t == 1) fprintf (st, "1 connection");
|
|
else fprintf (st, "%d connections", t);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* SHOW CONN/STAT processor */
|
|
|
|
t_stat dz_show (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
int32 i, t;
|
|
|
|
for (i = t = 0; i < dz_desc.lines; i++) { /* loop thru conn */
|
|
if (dz_ldsc[i].conn) {
|
|
t = 1;
|
|
if (val) tmxr_fconns (st, &dz_ldsc[i], i);
|
|
else tmxr_fstats (st, &dz_ldsc[i], i);
|
|
}
|
|
}
|
|
if (t == 0) fprintf (st, "all disconnected\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* SET LINES processor */
|
|
|
|
t_stat dz_setnl (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
int32 newln, i, t, ndev;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL) return SCPE_ARG;
|
|
newln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r);
|
|
if ((r != SCPE_OK) || (newln == dz_desc.lines)) return r;
|
|
if ((newln == 0) || (newln % DZ_LINES)) return SCPE_ARG;
|
|
if (newln < dz_desc.lines) {
|
|
for (i = newln, t = 0; i < dz_desc.lines; i++) t = t | dz_ldsc[i].conn;
|
|
if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))
|
|
return SCPE_OK;
|
|
for (i = newln; i < dz_desc.lines; i++) {
|
|
if (dz_ldsc[i].conn) {
|
|
tmxr_linemsg (&dz_ldsc[i], "\r\nOperator disconnected line\r\n");
|
|
tmxr_reset_ln (&dz_ldsc[i]); /* reset line */
|
|
}
|
|
if ((i % DZ_LINES) == (DZ_LINES - 1))
|
|
dz_clear (i / DZ_LINES, TRUE); /* reset mux */
|
|
}
|
|
}
|
|
dz_dib.lnt = (newln / DZ_LINES) * IOLN_DZ; /* set length */
|
|
dz_desc.lines = newln;
|
|
ndev = ((dz_dev.flags & DEV_DIS)? 0: (dz_desc.lines / DZ_LINES));
|
|
return auto_config (dz_dev.name, ndev); /* auto config */
|
|
}
|
|
|
|
/* SHOW VECTOR processor */
|
|
|
|
t_stat dz_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
return show_vec (st, uptr, ((dz_desc.lines * 2) / DZ_LINES), desc);
|
|
}
|
|
|
|
/* SET LOG processor */
|
|
|
|
t_stat dz_set_log (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
char *tptr;
|
|
t_stat r;
|
|
int32 ln;
|
|
|
|
if (cptr == NULL) return SCPE_ARG;
|
|
tptr = strchr (cptr, '=');
|
|
if ((tptr == NULL) || (*tptr == 0)) return SCPE_ARG;
|
|
*tptr++ = 0;
|
|
ln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r);
|
|
if ((r != SCPE_OK) || (ln >= dz_desc.lines)) return SCPE_ARG;
|
|
return tmxr_set_log (NULL, ln, tptr, desc);
|
|
}
|
|
|
|
/* SET NOLOG processor */
|
|
|
|
t_stat dz_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
t_stat r;
|
|
int32 ln;
|
|
|
|
if (cptr == NULL) return SCPE_ARG;
|
|
ln = (int32) get_uint (cptr, 10, (DZ_MUXES * DZ_LINES), &r);
|
|
if ((r != SCPE_OK) || (ln >= dz_desc.lines)) return SCPE_ARG;
|
|
return tmxr_set_nolog (NULL, ln, NULL, desc);
|
|
}
|
|
|
|
/* SHOW LOG processor */
|
|
|
|
t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
int32 i;
|
|
|
|
for (i = 0; i < dz_desc.lines; i++) {
|
|
fprintf (st, "line %d: ", i);
|
|
tmxr_show_log (st, NULL, i, desc);
|
|
fprintf (st, "\n");
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
|
|
|