126 lines
4.6 KiB
C
126 lines
4.6 KiB
C
/* pdp1_clk.c: PDP-1D clock simulator
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Copyright (c) 2006-2008, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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bused in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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clk PDP-1D clock
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Note that the clock is run at 1/8 of real speed (125Hz instead of 1Khz), to
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provide for eventual implementation of idling.
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*/
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#include "pdp1_defs.h"
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#define CLK_HWRE_TPS 1000 /* hardware freq */
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#define CLK_TPS 125 /* sim freq */
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#define CLK_CNTS (CLK_HWRE_TPS / CLK_TPS) /* counts per tick */
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#define CLK_C1MIN (1000 * 60) /* counts per min */
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#define CLK_C32MS 32 /* counts per 32ms */
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int32 clk32ms_sbs = 0; /* 32ms SBS level */
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int32 clk1min_sbs = 0; /* 1min SBS level */
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int32 clk_cntr = 0;
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int32 tmxr_poll = 5000;
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extern int32 stop_inst;
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t_stat clk_svc (UNIT *uptr);
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t_stat clk_reset (DEVICE *dptr);
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit
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clk_reg CLK register list
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*/
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UNIT clk_unit = {
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UDATA (&clk_svc, 0, 0), 5000
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};
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REG clk_reg[] = {
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{ ORDATA (CNTR, clk_cntr, 16) },
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{ DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },
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{ DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "SBS32MSLVL", "SBS32MSLVL",
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&dev_set_sbs, &dev_show_sbs, (void *) &clk32ms_sbs },
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{ MTAB_XTD|MTAB_VDV, 0, "SBS1MINLVL", "SBS1MINLVL",
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&dev_set_sbs, &dev_show_sbs, (void *) &clk1min_sbs },
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{ 0 }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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NULL, DEV_DISABLE | DEV_DIS
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};
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/* Clock IOT routine */
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int32 clk (int32 inst, int32 dev, int32 dat)
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{
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int32 used, incr;
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if (clk_dev.flags & DEV_DIS) /* disabled? */
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return (stop_inst << IOT_V_REASON) | dat; /* illegal inst */
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used = tmxr_poll - (sim_activate_time (&clk_unit) - 1);
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incr = (used * CLK_CNTS) / tmxr_poll;
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return clk_cntr + incr;
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}
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/* Unit service, generate appropriate interrupts */
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t_stat clk_svc (UNIT *uptr)
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{
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if (clk_dev.flags & DEV_DIS) /* disabled? */
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return SCPE_OK;
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tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK); /* calibrate clock */
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sim_activate (&clk_unit, tmxr_poll); /* reactivate unit */
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clk_cntr = clk_cntr + CLK_CNTS; /* incr counter */
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if ((clk_cntr % CLK_C32MS) == 0) /* 32ms interval? */
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dev_req_int (clk32ms_sbs); /* req intr */
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if (clk_cntr >= CLK_C1MIN) { /* 1min interval? */
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dev_req_int (clk1min_sbs); /* req intr */
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clk_cntr = 0; /* reset counter */
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat clk_reset (DEVICE *dptr)
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{
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if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit); /* disabled? */
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else {
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tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);
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sim_activate_abs (&clk_unit, tmxr_poll); /* activate unit */
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}
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clk_cntr = 0; /* clear counter */
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return SCPE_OK;
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}
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