1186 lines
36 KiB
C
1186 lines
36 KiB
C
/* altair_cpu.c: MITS Altair Intel 8080 CPU simulator
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Copyright (c) 1997-2012, Charles E. Owen
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Charles E. Owen shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Charles E. Owen.
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cpu 8080 CPU
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19-Mar-12 RMS Fixed data type for breakpoint variables
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08-Oct-02 RMS Tied off spurious compiler warnings
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The register state for the 8080 CPU is:
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A<0:7> Accumulator
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BC<0:15> BC Register Pair
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DE<0:15> DE Register Pair
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HL<0:15> HL Register Pair
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C carry flag
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Z zero flag
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S Sign bit
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AC Aux carry
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P Parity bit
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PC<0:15> program counter
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SP<0:15> Stack Pointer
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The 8080 is an 8-bit CPU, which uses 16-bit registers to address
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up to 64KB of memory.
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The 78 basic instructions come in 1, 2, and 3-byte flavors.
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This routine is the instruction decode routine for the 8080.
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It is called from the simulator control program to execute
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instructions in simulated memory, starting at the simulated PC.
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It runs until 'reason' is set non-zero.
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General notes:
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1. Reasons to stop. The simulator can be stopped by:
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HALT instruction
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I/O error in I/O simulator
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Invalid OP code (if ITRAP is set on CPU)
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2. Interrupts.
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There are 8 possible levels of interrupt, and in effect they
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do a hardware CALL instruction to one of 8 possible low
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memory addresses.
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3. Non-existent memory. On the 8080, reads to non-existent memory
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return 0377, and writes are ignored. In the simulator, the
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largest possible memory is instantiated and initialized to zero.
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Thus, only writes need be checked against actual memory size.
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4. Adding I/O devices. These modules must be modified:
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altair_cpu.c add I/O service routines to dev_table
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altair_sys.c add pointer to data structures in sim_devices
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*/
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#include <stdio.h>
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#include "altair_defs.h"
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#define UNIT_V_OPSTOP (UNIT_V_UF) /* Stop on Invalid OP? */
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#define UNIT_OPSTOP (1 << UNIT_V_OPSTOP)
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#define UNIT_V_CHIP (UNIT_V_UF+1) /* 8080 or Z80 */
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#define UNIT_CHIP (1 << UNIT_V_CHIP)
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#define UNIT_V_MSIZE (UNIT_V_UF+2) /* Memory Size */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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unsigned char M[MAXMEMSIZE]; /* memory */
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int32 A = 0; /* accumulator */
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int32 BC = 0; /* BC register pair */
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int32 DE = 0; /* DE register pair */
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int32 HL = 0; /* HL register pair */
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int32 SP = 0; /* Stack pointer */
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int32 C = 0; /* carry flag */
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int32 Z = 0; /* Zero flag */
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int32 AC = 0; /* Aux carry */
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int32 S = 0; /* sign flag */
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int32 P = 0; /* parity flag */
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int32 saved_PC = 0; /* program counter */
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int32 SR = 0; /* switch register */
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int32 INTE = 0; /* Interrupt Enable */
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int32 int_req = 0; /* Interrupt request */
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int32 chip = 0; /* 0 = 8080 chip, 1 = z80 chip */
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int32 PCX; /* External view of PC */
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/* function prototypes */
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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void setarith(int32 reg);
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void setlogical(int32 reg);
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void setinc(int32 reg);
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int32 getreg(int32 reg);
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void putreg(int32 reg, int32 val);
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int32 getpair(int32 reg);
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int32 getpush(int32 reg);
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void putpush(int32 reg, int32 data);
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void putpair(int32 reg, int32 val);
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void parity(int32 reg);
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int32 cond(int32 con);
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extern int32 sio0s(int32 io, int32 data);
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extern int32 sio0d(int32 io, int32 data);
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extern int32 sio1s(int32 io, int32 data);
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extern int32 sio1d(int32 io, int32 data);
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extern int32 dsk10(int32 io, int32 data);
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extern int32 dsk11(int32 io, int32 data);
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extern int32 dsk12(int32 io, int32 data);
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int32 nulldev(int32 io, int32 data);
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/* This is the I/O configuration table. There are 255 possible
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device addresses, if a device is plugged to a port it's routine
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address is here, 'nulldev' means no device is available
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*/
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struct idev {
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int32 (*routine)(int32, int32);
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};
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struct idev dev_table[256] = {
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004 */
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{&dsk10}, {&dsk11}, {&dsk12}, {&nulldev}, /* 010 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014 */
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{&sio0s}, {&sio0d}, {&sio1s}, {&sio1d}, /* 020 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 100 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 104 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 110 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 114 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 120 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 124 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 130 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 134 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 140 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 144 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 150 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 154 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 160 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 164 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 170 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 174 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 200 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 204 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 210 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 214 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 220 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 224 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 230 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 234 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 240 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 244 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 250 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 254 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 260 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 264 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 270 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 274 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 300 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 304 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 310 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 314 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 320 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 324 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 330 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 334 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 340 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 344 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 350 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 354 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 360 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 364 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 370 */
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{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 374 */
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};
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/* Altair MITS standard BOOT EPROM, fits in upper 256K of memory */
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int32 bootrom[256] = {
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0041, 0000, 0114, 0021, 0030, 0377, 0016, 0346,
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0032, 0167, 0023, 0043, 0015, 0302, 0010, 0377,
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0303, 0000, 0114, 0000, 0000, 0000, 0000, 0000,
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0363, 0061, 0142, 0115, 0257, 0323, 0010, 0076, /* 46000 */
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0004, 0323, 0011, 0303, 0031, 0114, 0333, 0010, /* 46010 */
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0346, 0002, 0302, 0016, 0114, 0076, 0002, 0323, /* 46020 */
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0011, 0333, 0010, 0346, 0100, 0302, 0016, 0114,
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0021, 0000, 0000, 0006, 0000, 0333, 0010, 0346,
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0004, 0302, 0045, 0114, 0076, 0020, 0365, 0325,
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0305, 0325, 0021, 0206, 0200, 0041, 0324, 0114,
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0333, 0011, 0037, 0332, 0070, 0114, 0346, 0037,
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0270, 0302, 0070, 0114, 0333, 0010, 0267, 0372,
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0104, 0114, 0333, 0012, 0167, 0043, 0035, 0312,
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0132, 0114, 0035, 0333, 0012, 0167, 0043, 0302,
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0104, 0114, 0341, 0021, 0327, 0114, 0001, 0200,
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0000, 0032, 0167, 0276, 0302, 0301, 0114, 0200,
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0107, 0023, 0043, 0015, 0302, 0141, 0114, 0032,
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0376, 0377, 0302, 0170, 0114, 0023, 0032, 0270,
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0301, 0353, 0302, 0265, 0114, 0361, 0361, 0052,
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0325, 0114, 0325, 0021, 0000, 0377, 0315, 0316,
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0114, 0321, 0332, 0276, 0114, 0315, 0316, 0114,
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0322, 0256, 0114, 0004, 0004, 0170, 0376, 0040,
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0332, 0054, 0114, 0006, 0001, 0312, 0054, 0114,
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0333, 0010, 0346, 0002, 0302, 0240, 0114, 0076,
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0001, 0323, 0011, 0303, 0043, 0114, 0076, 0200,
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0323, 0010, 0303, 0000, 0000, 0321, 0361, 0075,
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0302, 0056, 0114, 0076, 0103, 0001, 0076, 0117,
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0001, 0076, 0115, 0107, 0076, 0200, 0323, 0010,
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0170, 0323, 0001, 0303, 0311, 0114, 0172, 0274,
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0300, 0173, 0275, 0311, 0204, 0000, 0114, 0044,
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0026, 0126, 0026, 0000, 0000, 0000, 0000, 0000
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};
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/* CPU data structures
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cpu_dev CPU device descriptor
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cpu_unit CPU unit descriptor
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cpu_reg CPU register list
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cpu_mod CPU modifiers list
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*/
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UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
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REG cpu_reg[] = {
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{ ORDATA (PC, saved_PC, 16) },
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{ ORDATA (A, A, 8) },
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{ ORDATA (BC, BC, 16) },
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{ ORDATA (DE, DE, 16) },
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{ ORDATA (HL, HL, 16) },
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{ ORDATA (SP, SP, 16) },
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{ FLDATA (C, C, 16) },
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{ FLDATA (Z, Z, 16) },
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{ FLDATA (AC, AC, 16) },
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{ FLDATA (S, S, 16) },
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{ FLDATA (P, P, 16) },
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{ FLDATA (INTE, INTE, 16) },
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{ ORDATA (SR, SR, 16) },
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{ ORDATA (WRU, sim_int_char, 8) },
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{ NULL }
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};
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MTAB cpu_mod[] = {
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{ UNIT_CHIP, UNIT_CHIP, "Z80", "Z80", NULL },
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{ UNIT_CHIP, 0, "8080", "8080", NULL },
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{ UNIT_OPSTOP, UNIT_OPSTOP, "ITRAP", "ITRAP", NULL },
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{ UNIT_OPSTOP, 0, "NOITRAP", "NOITRAP", NULL },
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{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
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{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
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{ UNIT_MSIZE, 12288, NULL, "12K", &cpu_set_size },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
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{ UNIT_MSIZE, 20480, NULL, "20K", &cpu_set_size },
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{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
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{ UNIT_MSIZE, 28672, NULL, "28K", &cpu_set_size },
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
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{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size },
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{ UNIT_MSIZE, 65535, NULL, "64K", &cpu_set_size },
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{ 0 }
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};
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DEVICE cpu_dev = {
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"CPU", &cpu_unit, cpu_reg, cpu_mod,
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1, 8, 16, 1, 8, 8,
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&cpu_ex, &cpu_dep, &cpu_reset,
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NULL, NULL, NULL
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};
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t_stat sim_instr (void)
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{
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int32 PC, IR, OP, DAR, reason, hi, lo, carry, i;
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PC = saved_PC & ADDRMASK; /* load local PC */
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C = C & 0200000;
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reason = 0;
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/* Main instruction fetch/decode loop */
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while (reason == 0) { /* loop until halted */
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if (sim_interval <= 0) { /* check clock queue */
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if ((reason = sim_process_event ())) break;
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}
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if (int_req > 0) { /* interrupt? */
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/* 8080 interrupts not implemented yet. None were used,
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on a standard Altair 8800. All I/O is programmed. */
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} /* end interrupt */
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if (sim_brk_summ &&
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sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
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reason = STOP_IBKPT; /* stop simulation */
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break;
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}
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if (PC == 0177400) { /* BOOT PROM address */
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for (i = 0; i < 250; i++) {
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M[i + 0177400] = bootrom[i] & 0xFF;
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}
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}
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PCX = PC;
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IR = OP = M[PC]; /* fetch instruction */
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PC = (PC + 1) & ADDRMASK; /* increment PC */
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sim_interval--;
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if (OP == 0166) { /* HLT Instruction*/
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reason = STOP_HALT;
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PC--;
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continue;
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}
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/* Handle below all operations which refer to registers or
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register pairs. After that, a large switch statement
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takes care of all other opcodes */
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if ((OP & 0xC0) == 0x40) { /* MOV */
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DAR = getreg(OP & 0x07);
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putreg((OP >> 3) & 0x07, DAR);
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continue;
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}
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if ((OP & 0xC7) == 0x06) { /* MVI */
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putreg((OP >> 3) & 0x07, M[PC]);
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PC++;
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continue;
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}
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if ((OP & 0xCF) == 0x01) { /* LXI */
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DAR = M[PC] & 0x00ff;
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PC++;
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DAR = DAR | ((M[PC] <<8) & 0xFF00);
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putpair((OP >> 4) & 0x03, DAR);
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PC++;
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continue;
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}
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if ((OP & 0xEF) == 0x0A) { /* LDAX */
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DAR = getpair((OP >> 4) & 0x03);
|
|
putreg(7, M[DAR]);
|
|
continue;
|
|
}
|
|
if ((OP & 0xEF) == 0x02) { /* STAX */
|
|
DAR = getpair((OP >> 4) & 0x03);
|
|
M[DAR] = getreg(7);
|
|
continue;
|
|
}
|
|
|
|
if ((OP & 0xF8) == 0xB8) { /* CMP */
|
|
DAR = A & 0xFF;
|
|
DAR -= getreg(OP & 0x07);
|
|
setarith(DAR);
|
|
continue;
|
|
}
|
|
if ((OP & 0xC7) == 0xC2) { /* JMP <condition> */
|
|
if (cond((OP >> 3) & 0x07) == 1) {
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
PC = (hi << 8) + lo;
|
|
} else {
|
|
PC += 2;
|
|
}
|
|
continue;
|
|
}
|
|
if ((OP & 0xC7) == 0xC4) { /* CALL <condition> */
|
|
if (cond((OP >> 3) & 0x07) == 1) {
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
SP--;
|
|
M[SP] = (PC >> 8) & 0xff;
|
|
SP--;
|
|
M[SP] = PC & 0xff;
|
|
PC = (hi << 8) + lo;
|
|
} else {
|
|
PC += 2;
|
|
}
|
|
continue;
|
|
}
|
|
if ((OP & 0xC7) == 0xC0) { /* RET <condition> */
|
|
if (cond((OP >> 3) & 0x07) == 1) {
|
|
PC = M[SP];
|
|
SP++;
|
|
PC |= (M[SP] << 8) & 0xff00;
|
|
SP++;
|
|
}
|
|
continue;
|
|
}
|
|
if ((OP & 0xC7) == 0xC7) { /* RST */
|
|
SP--;
|
|
M[SP] = (PC >> 8) & 0xff;
|
|
SP--;
|
|
M[SP] = PC & 0xff;
|
|
PC = OP & 0x38;
|
|
continue;
|
|
}
|
|
|
|
if ((OP & 0xCF) == 0xC5) { /* PUSH */
|
|
DAR = getpush((OP >> 4) & 0x03);
|
|
SP--;
|
|
M[SP] = (DAR >> 8) & 0xff;
|
|
SP--;
|
|
M[SP] = DAR & 0xff;
|
|
continue;
|
|
}
|
|
if ((OP & 0xCF) == 0xC1) { /*POP */
|
|
DAR = M[SP];
|
|
SP++;
|
|
DAR |= M[SP] << 8;
|
|
SP++;
|
|
putpush((OP >> 4) & 0x03, DAR);
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0x80) { /* ADD */
|
|
A += getreg(OP & 0x07);
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0x88) { /* ADC */
|
|
carry = 0;
|
|
if (C) carry = 1;
|
|
A += getreg(OP & 0x07);
|
|
A += carry;
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0x90) { /* SUB */
|
|
A -= getreg(OP & 0x07);
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0x98) { /* SBB */
|
|
carry = 0;
|
|
if (C) carry = 1;
|
|
A -= (getreg(OP & 0x07)) + carry ;
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xC7) == 0x04) { /* INR */
|
|
DAR = getreg((OP >> 3) & 0x07);
|
|
DAR++;
|
|
setinc(DAR);
|
|
DAR = DAR & 0xFF;
|
|
putreg((OP >> 3) & 0x07, DAR);
|
|
continue;
|
|
}
|
|
if ((OP & 0xC7) == 0x05) { /* DCR */
|
|
DAR = getreg((OP >> 3) & 0x07);
|
|
DAR--;
|
|
setinc(DAR);
|
|
DAR = DAR & 0xFF;
|
|
putreg((OP >> 3) & 0x07, DAR);
|
|
continue;
|
|
}
|
|
if ((OP & 0xCF) == 0x03) { /* INX */
|
|
DAR = getpair((OP >> 4) & 0x03);
|
|
DAR++;
|
|
DAR = DAR & 0xFFFF;
|
|
putpair((OP >> 4) & 0x03, DAR);
|
|
continue;
|
|
}
|
|
if ((OP & 0xCF) == 0x0B) { /* DCX */
|
|
DAR = getpair((OP >> 4) & 0x03);
|
|
DAR--;
|
|
DAR = DAR & 0xFFFF;
|
|
putpair((OP >> 4) & 0x03, DAR);
|
|
continue;
|
|
}
|
|
if ((OP & 0xCF) == 0x09) { /* DAD */
|
|
HL += getpair((OP >> 4) & 0x03);
|
|
C = 0;
|
|
if (HL & 0x10000)
|
|
C = 0200000;
|
|
HL = HL & 0xFFFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0xA0) { /* ANA */
|
|
A &= getreg(OP & 0x07);
|
|
C = 0;
|
|
setlogical(A);
|
|
A &= 0xFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0xA8) { /* XRA */
|
|
A ^= getreg(OP & 0x07);
|
|
C = 0;
|
|
setlogical(A);
|
|
A &= 0xFF;
|
|
continue;
|
|
}
|
|
if ((OP & 0xF8) == 0xB0) { /* ORA */
|
|
A |= getreg(OP & 0x07);
|
|
C = 0;
|
|
setlogical(A);
|
|
A &= 0xFF;
|
|
continue;
|
|
}
|
|
|
|
|
|
|
|
/* The Big Instruction Decode Switch */
|
|
|
|
switch (IR) {
|
|
|
|
/* Logical instructions */
|
|
|
|
case 0376: { /* CPI */
|
|
DAR = A & 0xFF;
|
|
DAR -= M[PC];
|
|
PC++;
|
|
setarith(DAR);
|
|
break;
|
|
}
|
|
case 0346: { /* ANI */
|
|
A &= M[PC];
|
|
PC++;
|
|
C = AC = 0;
|
|
setlogical(A);
|
|
A &= 0xFF;
|
|
break;
|
|
}
|
|
case 0356: { /* XRI */
|
|
A ^= M[PC];
|
|
PC++;
|
|
C = AC = 0;
|
|
setlogical(A);
|
|
A &= 0xFF;
|
|
break;
|
|
}
|
|
case 0366: { /* ORI */
|
|
A |= M[PC];
|
|
PC++;
|
|
C = AC = 0;
|
|
setlogical(A);
|
|
A &= 0xFF;
|
|
break;
|
|
}
|
|
|
|
/* Jump instructions */
|
|
|
|
case 0303: { /* JMP */
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
PC = (hi << 8) + lo;
|
|
break;
|
|
}
|
|
case 0351: { /* PCHL */
|
|
PC = HL;
|
|
break;
|
|
}
|
|
case 0315: { /* CALL */
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
SP--;
|
|
M[SP] = (PC >> 8) & 0xff;
|
|
SP--;
|
|
M[SP] = PC & 0xff;
|
|
PC = (hi << 8) + lo;
|
|
break;
|
|
}
|
|
case 0311: { /* RET */
|
|
PC = M[SP];
|
|
SP++;
|
|
PC |= (M[SP] << 8) & 0xff00;
|
|
SP++;
|
|
break;
|
|
}
|
|
|
|
/* Data Transfer Group */
|
|
|
|
case 062: { /* STA */
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
DAR = (hi << 8) + lo;
|
|
M[DAR] = A;
|
|
break;
|
|
}
|
|
case 072: { /* LDA */
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
DAR = (hi << 8) + lo;
|
|
A = M[DAR];
|
|
break;
|
|
}
|
|
case 042: { /* SHLD */
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
DAR = (hi << 8) + lo;
|
|
M[DAR] = HL;
|
|
DAR++;
|
|
M[DAR] = (HL >>8) & 0x00ff;
|
|
break;
|
|
}
|
|
case 052: { /* LHLD */
|
|
lo = M[PC];
|
|
PC++;
|
|
hi = M[PC];
|
|
PC++;
|
|
DAR = (hi << 8) + lo;
|
|
HL = M[DAR];
|
|
DAR++;
|
|
HL = HL | (M[DAR] <<8);
|
|
break;
|
|
}
|
|
case 0353: { /* XCHG */
|
|
DAR = HL;
|
|
HL = DE;
|
|
DE = DAR;
|
|
break;
|
|
}
|
|
|
|
/* Arithmetic Group */
|
|
|
|
case 0306: { /* ADI */
|
|
A += M[PC];
|
|
PC++;
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
break;
|
|
}
|
|
case 0316: { /* ACI */
|
|
carry = 0;
|
|
if (C) carry = 1;
|
|
A += M[PC];
|
|
A += carry;
|
|
PC++;
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
break;
|
|
}
|
|
case 0326: { /* SUI */
|
|
A -= M[PC];
|
|
PC++;
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
break;
|
|
}
|
|
case 0336: { /* SBI */
|
|
carry = 0;
|
|
if (C) carry = 1;
|
|
A -= (M[PC] + carry);
|
|
PC++;
|
|
setarith(A);
|
|
A = A & 0xFF;
|
|
break;
|
|
}
|
|
case 047: { /* DAA */
|
|
DAR = A & 0x0F;
|
|
if (DAR > 9 || AC > 0) {
|
|
DAR += 6;
|
|
A &= 0xF0;
|
|
A |= DAR & 0x0F;
|
|
if (DAR & 0x10)
|
|
AC = 0200000;
|
|
else
|
|
AC = 0;
|
|
}
|
|
DAR = (A >> 4) & 0x0F;
|
|
if (DAR > 9 || AC > 0) {
|
|
DAR += 6;
|
|
if (AC) DAR++;
|
|
A &= 0x0F;
|
|
A |= (DAR << 4);
|
|
}
|
|
if ((DAR << 4) & 0x100)
|
|
C = 0200000;
|
|
else
|
|
C = 0;
|
|
if (A & 0x80) {
|
|
S = 0200000;
|
|
} else {
|
|
S = 0;
|
|
}
|
|
if ((A & 0xff) == 0)
|
|
Z = 0200000;
|
|
else
|
|
Z = 0;
|
|
parity(A);
|
|
A = A & 0xFF;
|
|
break;
|
|
}
|
|
case 07: { /* RLC */
|
|
C = 0;
|
|
C = (A << 9) & 0200000;
|
|
A = (A << 1) & 0xFF;
|
|
if (C)
|
|
A |= 0x01;
|
|
break;
|
|
}
|
|
case 017: { /* RRC */
|
|
C = 0;
|
|
if ((A & 0x01) == 1)
|
|
C |= 0200000;
|
|
A = (A >> 1) & 0xFF;
|
|
if (C)
|
|
A |= 0x80;
|
|
break;
|
|
}
|
|
case 027: { /* RAL */
|
|
DAR = C;
|
|
C = 0;
|
|
C = (A << 9) & 0200000;
|
|
A = (A << 1) & 0xFF;
|
|
if (DAR)
|
|
A |= 1;
|
|
else
|
|
A &= 0xFE;
|
|
break;
|
|
}
|
|
case 037: { /* RAR */
|
|
DAR = C;
|
|
C = 0;
|
|
if ((A & 0x01) == 1)
|
|
C |= 0200000;
|
|
A = (A >> 1) & 0xFF;
|
|
if (DAR)
|
|
A |= 0x80;
|
|
else
|
|
A &= 0x7F;
|
|
break;
|
|
}
|
|
case 057: { /* CMA */
|
|
A = ~ A;
|
|
A &= 0xFF;
|
|
break;
|
|
}
|
|
case 077: { /* CMC */
|
|
C = ~ C;
|
|
C &= 0200000;
|
|
break;
|
|
}
|
|
case 067: { /* STC */
|
|
C = 0200000;
|
|
break;
|
|
}
|
|
|
|
/* Stack, I/O & Machine Control Group */
|
|
|
|
case 0: { /* NOP */
|
|
break;
|
|
}
|
|
case 0343: { /* XTHL */
|
|
lo = M[SP];
|
|
hi = M[SP + 1];
|
|
M[SP] = HL & 0xFF;
|
|
M[SP + 1] = (HL >> 8) & 0xFF;
|
|
HL = (hi << 8) + lo;
|
|
break;
|
|
}
|
|
case 0371: { /* SPHL */
|
|
SP = HL;
|
|
break;
|
|
}
|
|
case 0373: { /* EI */
|
|
INTE = 0200000;
|
|
break;
|
|
}
|
|
case 0363: { /* DI */
|
|
INTE = 0;
|
|
break;
|
|
}
|
|
case 0333: { /* IN */
|
|
DAR = M[PC] & 0xFF;
|
|
PC++;
|
|
if (DAR == 0xFF) {
|
|
A = (SR >> 8) & 0xFF;
|
|
} else {
|
|
A = dev_table[DAR].routine(0, 0);
|
|
}
|
|
break;
|
|
}
|
|
case 0323: { /* OUT */
|
|
DAR = M[PC] & 0xFF;
|
|
PC++;
|
|
dev_table[DAR].routine(1, A);
|
|
break;
|
|
}
|
|
|
|
default: {
|
|
if (cpu_unit.flags & UNIT_OPSTOP) {
|
|
reason = STOP_OPCODE;
|
|
PC--;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Simulation halted */
|
|
|
|
saved_PC = PC;
|
|
return reason;
|
|
}
|
|
|
|
/* Test an 8080 flag condition and return 1 if true, 0 if false */
|
|
int32 cond(int32 con)
|
|
{
|
|
switch (con) {
|
|
case 0:
|
|
if (Z == 0) return (1);
|
|
break;
|
|
case 1:
|
|
if (Z != 0) return (1);
|
|
break;
|
|
case 2:
|
|
if (C == 0) return (1);
|
|
break;
|
|
case 3:
|
|
if (C != 0) return (1);
|
|
break;
|
|
case 4:
|
|
if (P == 0) return (1);
|
|
break;
|
|
case 5:
|
|
if (P != 0) return (1);
|
|
break;
|
|
case 6:
|
|
if (S == 0) return (1);
|
|
break;
|
|
case 7:
|
|
if (S != 0) return (1);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
/* Set the <C>arry, <S>ign, <Z>ero and <P>arity flags following
|
|
an arithmetic operation on 'reg'.
|
|
*/
|
|
|
|
void setarith(int32 reg)
|
|
{
|
|
int32 bc = 0;
|
|
|
|
if (reg & 0x100)
|
|
C = 0200000;
|
|
else
|
|
C = 0;
|
|
if (reg & 0x80) {
|
|
bc++;
|
|
S = 0200000;
|
|
} else {
|
|
S = 0;
|
|
}
|
|
if ((reg & 0xff) == 0)
|
|
Z = 0200000;
|
|
else
|
|
Z = 0;
|
|
AC = 0;
|
|
if (cpu_unit.flags & UNIT_CHIP) {
|
|
P = 0; /* parity is zero for *all* arith ops on Z80 */
|
|
} else {
|
|
parity(reg);
|
|
}
|
|
}
|
|
|
|
/* Set the <C>arry, <S>ign, <Z>ero amd <P>arity flags following
|
|
a logical (bitwise) operation on 'reg'.
|
|
*/
|
|
|
|
void setlogical(int32 reg)
|
|
{
|
|
C = 0;
|
|
if (reg & 0x80) {
|
|
S = 0200000;
|
|
} else {
|
|
S = 0;
|
|
}
|
|
if ((reg & 0xff) == 0)
|
|
Z = 0200000;
|
|
else
|
|
Z = 0;
|
|
AC = 0;
|
|
parity(reg);
|
|
}
|
|
|
|
/* Set the Parity (P) flag based on parity of 'reg', i.e., number
|
|
of bits on even: P=0200000, else P=0
|
|
*/
|
|
|
|
void parity(int32 reg)
|
|
{
|
|
int32 bc = 0;
|
|
|
|
if (reg & 0x01) bc++;
|
|
if (reg & 0x02) bc++;
|
|
if (reg & 0x04) bc++;
|
|
if (reg & 0x08) bc++;
|
|
if (reg & 0x10) bc++;
|
|
if (reg & 0x20) bc++;
|
|
if (reg & 0x40) bc++;
|
|
if (reg & 0x80) bc++;
|
|
P = ~(bc << 16);
|
|
P &= 0200000;
|
|
}
|
|
|
|
/* Set the <S>ign, <Z>ero amd <P>arity flags following
|
|
an INR/DCR operation on 'reg'.
|
|
*/
|
|
|
|
void setinc(int32 reg)
|
|
{
|
|
int32 bc = 0;
|
|
|
|
if (reg & 0x80) {
|
|
bc++;
|
|
S = 0200000;
|
|
} else {
|
|
S = 0;
|
|
}
|
|
if ((reg & 0xff) == 0)
|
|
Z = 0200000;
|
|
else
|
|
Z = 0;
|
|
if (cpu_unit.flags & UNIT_CHIP) {
|
|
P = 0; /* parity is zero for *all* arith ops on Z80 */
|
|
} else {
|
|
parity(reg);
|
|
}
|
|
}
|
|
|
|
/* Get an 8080 register and return it */
|
|
int32 getreg(int32 reg)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
return ((BC >>8) & 0x00ff);
|
|
case 1:
|
|
return (BC & 0x00FF);
|
|
case 2:
|
|
return ((DE >>8) & 0x00ff);
|
|
case 3:
|
|
return (DE & 0x00ff);
|
|
case 4:
|
|
return ((HL >>8) & 0x00ff);
|
|
case 5:
|
|
return (HL & 0x00ff);
|
|
case 6:
|
|
return (M[HL]);
|
|
case 7:
|
|
return (A);
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Put a value into an 8080 register from memory */
|
|
void putreg(int32 reg, int32 val)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
BC = BC & 0x00FF;
|
|
BC = BC | (val <<8);
|
|
break;
|
|
case 1:
|
|
BC = BC & 0xFF00;
|
|
BC = BC | val;
|
|
break;
|
|
case 2:
|
|
DE = DE & 0x00FF;
|
|
DE = DE | (val <<8);
|
|
break;
|
|
case 3:
|
|
DE = DE & 0xFF00;
|
|
DE = DE | val;
|
|
break;
|
|
case 4:
|
|
HL = HL & 0x00FF;
|
|
HL = HL | (val <<8);
|
|
break;
|
|
case 5:
|
|
HL = HL & 0xFF00;
|
|
HL = HL | val;
|
|
break;
|
|
case 6:
|
|
M[HL] = val & 0xff;
|
|
break;
|
|
case 7:
|
|
A = val & 0xff;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Return the value of a selected register pair */
|
|
int32 getpair(int32 reg)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
return (BC);
|
|
case 1:
|
|
return (DE);
|
|
case 2:
|
|
return (HL);
|
|
case 3:
|
|
return (SP);
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Return the value of a selected register pair, in PUSH
|
|
format where 3 means A& flags, not SP */
|
|
int32 getpush(int32 reg)
|
|
{
|
|
int32 stat;
|
|
|
|
switch (reg) {
|
|
case 0:
|
|
return (BC);
|
|
case 1:
|
|
return (DE);
|
|
case 2:
|
|
return (HL);
|
|
case 3:
|
|
stat = A << 8;
|
|
if (S) stat |= 0x80;
|
|
if (Z) stat |= 0x40;
|
|
if (AC) stat |= 0x10;
|
|
if (P) stat |= 0x04;
|
|
stat |= 0x02;
|
|
if (C) stat |= 0x01;
|
|
return (stat);
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* Place data into the indicated register pair, in PUSH
|
|
format where 3 means A& flags, not SP */
|
|
void putpush(int32 reg, int32 data)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
BC = data;
|
|
break;
|
|
case 1:
|
|
DE = data;
|
|
break;
|
|
case 2:
|
|
HL = data;
|
|
break;
|
|
case 3:
|
|
A = (data >> 8) & 0xff;
|
|
S = Z = AC = P = C = 0;
|
|
if (data & 0x80) S = 0200000;
|
|
if (data & 0x40) Z = 0200000;
|
|
if (data & 0x10) AC = 0200000;
|
|
if (data & 0x04) P = 0200000;
|
|
if (data & 0x01) C = 0200000;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/* Put a value into an 8080 register pair */
|
|
void putpair(int32 reg, int32 val)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
BC = val;
|
|
break;
|
|
case 1:
|
|
DE = val;
|
|
break;
|
|
case 2:
|
|
HL = val;
|
|
break;
|
|
case 3:
|
|
SP = val;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat cpu_reset (DEVICE *dptr)
|
|
{
|
|
C = 0;
|
|
Z = 0;
|
|
saved_PC = 0;
|
|
int_req = 0;
|
|
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory examine */
|
|
|
|
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
if (addr >= MEMSIZE) return SCPE_NXM;
|
|
if (vptr != NULL) *vptr = M[addr] & 0377;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Memory deposit */
|
|
|
|
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
|
{
|
|
if (addr >= MEMSIZE) return SCPE_NXM;
|
|
M[addr] = val & 0377;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
int32 mc = 0;
|
|
uint32 i;
|
|
|
|
if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
|
|
return SCPE_ARG;
|
|
for (i = val; i < MEMSIZE; i++) mc = mc | M[i];
|
|
if ((mc != 0) && (!get_yn ("Really truncate memory [N]?", FALSE)))
|
|
return SCPE_OK;
|
|
MEMSIZE = val;
|
|
for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
int32 nulldev(int32 flag, int32 data)
|
|
{
|
|
if (flag == 0)
|
|
return (0377);
|
|
return 0;
|
|
}
|
|
|