333 lines
11 KiB
C
333 lines
11 KiB
C
/* pdp11_defs.h: PDP-11 simulator definitions
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Copyright (c) 1993-2001, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
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and John Wilson in resolving questions about the PDP-11
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01-Jun-01 RMS Added DZ11 support
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23-Apr-01 RMS Added RK611 support
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05-Apr-01 RMS Added TS11/TSV05 support
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10-Feb-01 RMS Added DECtape support
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*/
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#include "sim_defs.h" /* simulator defns */
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#include <setjmp.h>
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/* Architectural constants */
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#define STKLIM 0400 /* stack limit */
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#define VASIZE 0200000 /* 2**16 */
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#define VAMASK (VASIZE - 1) /* 2**16 - 1 */
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#define INIMEMSIZE 001000000 /* 2**18 */
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#define IOPAGEBASE 017760000 /* 2**22 - 2**13 */
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#define MAXMEMSIZE 020000000 /* 2**22 */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((t_addr) (x)) < MEMSIZE)
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#define DMASK 0177777
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/* Protection modes */
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#define KERNEL 0
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#define SUPER 1
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#define UNUSED 2
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#define USER 3
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/* I/O access modes */
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#define READ 0
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#define READC 1 /* read console */
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#define WRITE 2
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#define WRITEC 3 /* write console */
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#define WRITEB 4
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/* PSW */
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#define PSW_V_C 0 /* condition codes */
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#define PSW_V_V 1
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#define PSW_V_Z 2
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#define PSW_V_N 3
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#define PSW_V_TBIT 4 /* trace trap */
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#define PSW_V_IPL 5 /* int priority */
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#define PSW_V_RS 11 /* register set */
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#define PSW_V_PM 12 /* previous mode */
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#define PSW_V_CM 14 /* current mode */
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#define PSW_RW 0174357 /* read/write bits */
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/* FPS */
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#define FPS_V_C 0 /* condition codes */
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#define FPS_V_V 1
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#define FPS_V_Z 2
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#define FPS_V_N 3
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#define FPS_V_T 5 /* truncate */
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#define FPS_V_L 6 /* long */
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#define FPS_V_D 7 /* double */
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#define FPS_V_IC 8 /* ic err int */
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#define FPS_V_IV 9 /* overflo err int */
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#define FPS_V_IU 10 /* underflo err int */
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#define FPS_V_IUV 11 /* undef var err int */
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#define FPS_V_ID 14 /* int disable */
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#define FPS_V_ER 15 /* error */
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/* PIRQ */
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#define PIRQ_PIR1 0001000
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#define PIRQ_PIR2 0002000
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#define PIRQ_PIR3 0004000
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#define PIRQ_PIR4 0010000
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#define PIRQ_PIR5 0020000
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#define PIRQ_PIR6 0040000
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#define PIRQ_PIR7 0100000
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#define PIRQ_IMP 0177356 /* implemented bits */
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#define PIRQ_RW 0177000 /* read/write bits */
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/* MMR0 */
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#define MMR0_MME 0000001 /* mem mgt enable */
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#define MMR0_V_PAGE 1 /* offset to pageno */
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#define MMR0_RO 0020000 /* read only error */
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#define MMR0_PL 0040000 /* page lnt error */
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#define MMR0_NR 0100000 /* no access error */
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#define MMR0_FREEZE 0160000 /* if set, no update */
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#define MMR0_IMP 0160177 /* implemented bits */
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#define MMR0_RW 0160001 /* read/write bits */
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/* MMR3 */
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#define MMR3_UDS 001 /* user dspace enbl */
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#define MMR3_SDS 002 /* super dspace enbl */
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#define MMR3_KDS 004 /* krnl dspace enbl */
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#define MMR3_CSM 010 /* CSM enable */
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#define MMR3_M22E 020 /* 22b mem mgt enbl */
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#define MMR3_BME 040 /* DMA bus map enbl */
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#define MMR3_IMP 077 /* implemented bits */
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#define MMR3_RW 077 /* read/write bits */
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/* PDR */
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#define PDR_NR 0000002 /* non-resident ACF */
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#define PDR_ED 0000010 /* expansion dir */
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#define PDR_W 0000100 /* written flag */
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#define PDR_PLF 0077400 /* page lnt field */
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#define PDR_IMP 0177516 /* implemented bits */
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#define PDR_RW 0177416 /* read/write bits */
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/* Virtual address */
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#define VA_DF 0017777 /* displacement */
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#define VA_BN 0017700 /* block number */
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#define VA_V_APF 13 /* offset to APF */
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#define VA_V_DS 16 /* offset to space */
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#define VA_V_MODE 17 /* offset to mode */
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#define VA_DS (1u << VA_V_DS) /* data space flag */
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/* CPUERR */
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#define CPUE_RED 0004 /* red stack */
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#define CPUE_YEL 0010 /* yellow stack */
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#define CPUE_TMO 0020 /* IO page nxm */
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#define CPUE_NXM 0040 /* memory nxm */
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#define CPUE_ODD 0100 /* odd address */
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#define CPUE_HALT 0200 /* HALT not kernel */
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#define CPUE_IMP 0374 /* implemented bits */
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/* Floating point accumulators */
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struct fpac {
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unsigned int32 l; /* low 32b */
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unsigned int32 h; /* high 32b */
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};
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typedef struct fpac fpac_t;
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/* Device CSRs */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Trap masks, descending priority order, following J-11
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An interrupt summary bit is kept with traps, to minimize overhead
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*/
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#define TRAP_V_RED 0 /* red stk abort 4 */
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#define TRAP_V_ODD 1 /* odd address 4 */
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#define TRAP_V_MME 2 /* mem mgt 250 */
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#define TRAP_V_NXM 3 /* nx memory 4 */
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#define TRAP_V_PAR 4 /* parity err 114 */
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#define TRAP_V_PRV 5 /* priv inst 4 */
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#define TRAP_V_ILL 6 /* illegal inst 10 */
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#define TRAP_V_BPT 7 /* BPT 14 */
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#define TRAP_V_IOT 8 /* IOT 20 */
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#define TRAP_V_EMT 9 /* EMT 30 */
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#define TRAP_V_TRAP 10 /* TRAP 34 */
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#define TRAP_V_TRC 11 /* T bit 14 */
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#define TRAP_V_YEL 12 /* stack 4 */
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#define TRAP_V_PWRFL 13 /* power fail 24 */
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#define TRAP_V_FPE 14 /* fpe 244 */
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#define TRAP_V_MAX 15 /* intr = max trp # */
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#define TRAP_RED (1u << TRAP_V_RED)
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#define TRAP_ODD (1u << TRAP_V_ODD)
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#define TRAP_MME (1u << TRAP_V_MME)
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#define TRAP_NXM (1u << TRAP_V_NXM)
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#define TRAP_PAR (1u << TRAP_V_PAR)
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#define TRAP_PRV (1u << TRAP_V_PRV)
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#define TRAP_ILL (1u << TRAP_V_ILL)
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#define TRAP_BPT (1u << TRAP_V_BPT)
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#define TRAP_IOT (1u << TRAP_V_IOT)
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#define TRAP_EMT (1u << TRAP_V_EMT)
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#define TRAP_TRAP (1u << TRAP_V_TRAP)
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#define TRAP_TRC (1u << TRAP_V_TRC)
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#define TRAP_YEL (1u << TRAP_V_YEL)
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#define TRAP_PWRFL (1u << TRAP_V_PWRFL)
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#define TRAP_FPE (1u << TRAP_V_FPE)
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#define TRAP_INT (1u << TRAP_V_MAX)
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#define TRAP_ALL ((1u << TRAP_V_MAX) - 1) /* all traps */
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#define VEC_RED 0004 /* trap vectors */
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#define VEC_ODD 0004
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#define VEC_MME 0250
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#define VEC_NXM 0004
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#define VEC_PAR 0114
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#define VEC_PRV 0004
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#define VEC_ILL 0010
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#define VEC_BPT 0014
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#define VEC_IOT 0020
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#define VEC_EMT 0030
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#define VEC_TRAP 0034
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#define VEC_TRC 0014
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#define VEC_YEL 0004
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#define VEC_PWRFL 0024
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#define VEC_FPE 0244
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/* Simulator stop codes; codes 1:TRAP_V_MAX correspond to traps 0:TRAPMAX-1 */
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#define STOP_HALT TRAP_V_MAX + 1 /* HALT instruction */
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#define STOP_IBKPT TRAP_V_MAX + 2 /* instruction bkpt */
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#define STOP_WAIT TRAP_V_MAX + 3 /* wait, no events */
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#define STOP_VECABORT TRAP_V_MAX + 4 /* abort vector read */
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#define STOP_SPABORT TRAP_V_MAX + 5 /* abort trap push */
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* Interrupt assignments, priority is right to left
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<3:0> = BR7, <3> = PIR7
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<7:4> = BR6, <7> = PIR6
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<19:8> = BR5, <19> = PIR5
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<28:20> = BR4, <28> = PIR4
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<29> = PIR3
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<30> = PIR2
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<31> = PIR1
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*/
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#define INT_V_PIR7 3
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#define INT_V_CLK 4
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#define INT_V_DTA 5
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#define INT_V_PIR6 7
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#define INT_V_RK 8
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#define INT_V_RL 9
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#define INT_V_RX 10
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#define INT_V_TM 11
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#define INT_V_RP 12
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#define INT_V_TS 13
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#define INT_V_HK 14
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#define INT_V_DZ0RX 16
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#define INT_V_DZ0TX 17
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#define INT_V_PIR5 19
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#define INT_V_TTI 20
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#define INT_V_TTO 21
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#define INT_V_PTR 22
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#define INT_V_PTP 23
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#define INT_V_LPT 24
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#define INT_V_PIR4 28
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#define INT_V_PIR3 29
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#define INT_V_PIR2 30
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#define INT_V_PIR1 31
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#define INT_PIR7 (1u << INT_V_PIR7)
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_DTA (1u << INT_V_DTA)
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#define INT_PIR6 (1u << INT_V_PIR6)
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#define INT_RK (1u << INT_V_RK)
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#define INT_RL (1u << INT_V_RL)
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#define INT_RX (1u << INT_V_RX)
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#define INT_TM (1u << INT_V_TM)
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#define INT_RP (1u << INT_V_RP)
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#define INT_TS (1u << INT_V_TS)
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#define INT_HK (1u << INT_V_HK)
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#define INT_DZ0RX (1u << INT_V_DZ0RX)
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#define INT_DZ0TX (1u << INT_V_DZ0TX)
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#define INT_PIR5 (1u << INT_V_PIR5)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_TTI (1u << INT_V_TTI)
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#define INT_TTO (1u << INT_V_TTO)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_PIR4 (1u << INT_V_PIR4)
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#define INT_PIR3 (1u << INT_V_PIR3)
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#define INT_PIR2 (1u << INT_V_PIR2)
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#define INT_PIR1 (1u << INT_V_PIR1)
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#define INT_IPL7 0x00000000 /* int level masks */
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#define INT_IPL6 0x0000000F
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#define INT_IPL5 0x000000FF
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#define INT_IPL4 0x000FFFFF
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#define INT_IPL3 0x1FFFFFFF
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#define INT_IPL2 0x3FFFFFFF
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#define INT_IPL1 0x7FFFFFFF
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#define INT_IPL0 0xFFFFFFFF
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#define VEC_PIRQ 0240 /* interrupt vectors */
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#define VEC_TTI 0060
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#define VEC_TTO 0064
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#define VEC_PTR 0070
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#define VEC_PTP 0074
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#define VEC_CLK 0100
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#define VEC_LPT 0200
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#define VEC_HK 0210
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#define VEC_RK 0220
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#define VEC_RL 0160
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#define VEC_DTA 0214
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#define VEC_TM 0224
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#define VEC_TS 0224
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#define VEC_RP 0254
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#define VEC_RX 0264
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#define VEC_DZ0RX 0310
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#define VEC_DZ0TX 0314
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/* CPU and FPU macros */
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#define update_MM ((MMR0 & (MMR0_FREEZE + MMR0_MME)) == MMR0_MME)
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#define setTRAP(name) trap_req = trap_req | (name)
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#define setCPUERR(name) CPUERR = CPUERR | (name)
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#define ABORT(val) longjmp (save_env, (val))
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#define SP R[6]
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#define PC R[7]
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