316 lines
10 KiB
C
316 lines
10 KiB
C
/* pdp8_rf.c: RF08 fixed head disk simulator
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Copyright (c) 1993-2001, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rf RF08 fixed head disk
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25-Apr-01 RMS Added device enable/disable support
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19-Mar-01 RMS Added disk monitor bootstrap, fixed IOT decoding
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15-Feb-01 RMS Fixed 3 cycle data break sequence
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14-Apr-99 RMS Changed t_addr to unsigned
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30-Mar-98 RMS Fixed bug in RF bootstrap
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The RF08 is a head-per-track disk. It uses the three cycle data break
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facility. To minimize overhead, the entire RF08 is buffered in memory.
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Two timing parameters are provided:
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rf_time Interword timing, must be non-zero
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rf_burst Burst mode, if 0, DMA occurs cycle by cycle; otherwise,
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DMA occurs in a burst
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*/
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#include "pdp8_defs.h"
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#include <math.h>
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/* Constants */
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#define RF_NUMWD 2048 /* words/track */
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#define RF_NUMTR 128 /* tracks/disk */
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#define RF_NUMDK 4 /* disks/controller */
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#define RF_SIZE (RF_NUMDK * RF_NUMTR * RF_NUMWD) /* words/drive */
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#define RF_WC 07750 /* word count */
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#define RF_MA 07751 /* mem address */
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#define RF_WMASK (RF_NUMWD - 1) /* word mask */
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/* Parameters in the unit descriptor */
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#define FUNC u4 /* function */
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#define RF_READ 2 /* read */
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#define RF_WRITE 4 /* write */
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/* Status register */
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#define RFS_PCA 04000 /* photocell status */
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#define RFS_DRE 02000 /* data req enable */
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#define RFS_WLS 01000 /* write lock status */
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#define RFS_EIE 00400 /* error int enable */
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#define RFS_PIE 00200 /* photocell int enb */
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#define RFS_CIE 00100 /* done int enable */
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#define RFS_MEX 00070 /* memory extension */
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#define RFS_DRL 00004 /* data late error */
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#define RFS_NXD 00002 /* non-existent disk */
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#define RFS_PER 00001 /* parity error */
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#define RFS_ERR (RFS_WLS + RFS_DRL + RFS_NXD + RFS_PER)
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#define RFS_V_MEX 3
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#define GET_MEX(x) (((x) & RFS_MEX) << (12 - RFS_V_MEX))
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) RF_NUMWD)))
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#define UPDATE_PCELL if (GET_POS(rf_time) < 6) rf_sta = rf_sta | RFS_PCA; \
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else rf_sta = rf_sta & ~RFS_PCA
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#define RF_INT_UPDATE if ((rf_done && (rf_sta & RFS_CIE)) || \
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((rf_sta & RFS_ERR) && (rf_sta & RFS_EIE)) || \
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((rf_sta & RFS_PCA) && (rf_sta & RFS_PIE))) \
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int_req = int_req | INT_RF; \
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else int_req = int_req & ~INT_RF
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extern uint16 M[];
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extern int32 int_req, dev_enb, stop_inst;
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extern UNIT cpu_unit;
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extern int32 df_devenb;
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int32 rf_sta = 0; /* status register */
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int32 rf_da = 0; /* disk address */
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int32 rf_done = 0; /* done flag */
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int32 rf_wlk = 0; /* write lock */
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int32 rf_time = 10; /* inter-word time */
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int32 rf_burst = 1; /* burst mode flag */
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int32 rf_stopioe = 1; /* stop on error */
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t_stat rf_svc (UNIT *uptr);
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t_stat pcell_svc (UNIT *uptr);
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t_stat rf_reset (DEVICE *dptr);
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t_stat rf_boot (int32 unitno);
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/* RF08 data structures
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rf_dev RF device descriptor
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rf_unit RF unit descriptor
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pcell_unit photocell timing unit (orphan)
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rf_reg RF register list
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*/
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UNIT rf_unit =
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{ UDATA (&rf_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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RF_SIZE) };
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UNIT pcell_unit = { UDATA (&pcell_svc, 0, 0) };
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REG rf_reg[] = {
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{ ORDATA (STA, rf_sta, 12) },
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{ ORDATA (DA, rf_da, 20) },
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{ ORDATA (WC, M[RF_WC], 12) },
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{ ORDATA (MA, M[RF_MA], 12) },
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{ FLDATA (DONE, rf_done, 0) },
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{ FLDATA (INT, int_req, INT_V_RF) },
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{ ORDATA (WLK, rf_wlk, 32) },
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{ DRDATA (TIME, rf_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (BURST, rf_burst, 0) },
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{ FLDATA (STOP_IOE, rf_stopioe, 0) },
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{ FLDATA (*DEVENB, dev_enb, INT_V_RF), REG_HRO },
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{ NULL } };
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DEVICE rf_dev = {
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"RF", &rf_unit, rf_reg, NULL,
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1, 8, 20, 1, 8, 12,
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NULL, NULL, &rf_reset,
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&rf_boot, NULL, NULL };
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/* IOT routines */
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int32 rf60 (int32 pulse, int32 AC)
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{
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int32 t;
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UPDATE_PCELL; /* update photocell */
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if (pulse & 1) { /* DCMA */
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rf_da = rf_da & ~07777; /* clear DAR<8:19> */
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rf_done = 0; /* clear done */
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rf_sta = rf_sta & ~RFS_ERR; /* clear errors */
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RF_INT_UPDATE; } /* update int req */
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if (pulse & 6) { /* DMAR, DMAW */
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rf_da = rf_da | AC; /* DAR<8:19> |= AC */
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rf_unit.FUNC = pulse & ~1; /* save function */
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t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new loc */
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if (t < 0) t = t + RF_NUMWD; /* wrap around? */
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sim_activate (&rf_unit, t * rf_time); /* schedule op */
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AC = 0; } /* clear AC */
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return AC;
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}
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int32 rf61 (int32 pulse, int32 AC)
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{
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UPDATE_PCELL; /* update photocell */
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* DCIM */
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rf_sta = rf_sta & 07007; /* clear STA<3:8> */
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int_req = int_req & ~INT_RF; /* clear int req */
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sim_cancel (&pcell_unit); /* cancel photocell */
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return AC;
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case 2: /* DSAC */
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return ((rf_da & RF_WMASK) == GET_POS (rf_time))? IOT_SKP + AC: AC;
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case 5: /* DIML */
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rf_sta = (rf_sta & 07007) | (AC & 0770); /* STA<3:8> <- AC */
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if (rf_sta & RFS_PIE) /* photocell int? */
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sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
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rf_time);
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else sim_cancel (&pcell_unit);
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RF_INT_UPDATE; /* update int req */
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return 0; /* clear AC */
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case 6: /* DIMA */
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return rf_sta; } /* AC <- STA<0:11> */
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return AC;
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}
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/* IOT's, continued */
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int32 rf62 (int32 pulse, int32 AC)
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{
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UPDATE_PCELL; /* update photocell */
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if (pulse & 1) { /* DFSE */
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if (rf_sta & RFS_ERR) AC = AC | IOT_SKP; }
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if (pulse & 2) { /* DFSC */
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if (pulse & 4) AC = AC & ~07777; /* for DMAC */
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else if (rf_done) AC = AC | IOT_SKP; }
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if (pulse & 4) AC = AC | (rf_da & 07777); /* DMAC */
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return AC;
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}
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int32 rf64 (int32 pulse, int32 AC)
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{
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UPDATE_PCELL; /* update photocell */
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* DCXA */
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rf_da = rf_da & 07777; /* clear DAR<0:7> */
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return AC;
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case 3: /* DXAL */
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rf_da = (rf_da & 07777) | ((AC & 0377) << 12); /* DAR<0:7> <- AC */
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return 0; /* clear AC */
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case 5: /* DXAC */
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return ((rf_da >> 12) & 0377); /* AC <- DAR<0:7> */
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default:
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return (stop_inst << IOT_V_REASON) + AC; } /* end switch */
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}
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/* Unit service
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Note that for reads and writes, memory addresses wrap around in the
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current field. This code assumes the entire disk is buffered.
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*/
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t_stat rf_svc (UNIT *uptr)
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{
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int32 pa, t, mex;
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UPDATE_PCELL; /* update photocell */
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if ((uptr -> flags & UNIT_BUF) == 0) { /* not buf? abort */
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rf_sta = rf_sta | RFS_NXD;
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rf_done = 1;
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RF_INT_UPDATE; /* update int req */
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return IORETURN (rf_stopioe, SCPE_UNATT); }
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mex = GET_MEX (rf_sta);
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do { M[RF_WC] = (M[RF_WC] + 1) & 07777; /* incr word count */
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M[RF_MA] = (M[RF_MA] + 1) & 07777; /* incr mem addr */
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pa = mex | M[RF_MA]; /* add extension */
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if (uptr -> FUNC == RF_READ) {
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if (MEM_ADDR_OK (pa)) /* read, check nxm */
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M[pa] = *(((int16 *) uptr -> filebuf) + rf_da); }
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else { t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
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if ((rf_wlk >> t) & 1) rf_sta = rf_sta | RFS_WLS;
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else { *(((int16 *) uptr -> filebuf) + rf_da) = M[pa];
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if (((t_addr) rf_da) >= uptr -> hwmark)
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uptr -> hwmark = rf_da + 1; } }
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rf_da = (rf_da + 1) & 03777777; } /* incr disk addr */
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while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */
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if (M[RF_WC] != 0) /* more to do? */
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sim_activate (&rf_unit, rf_time); /* sched next */
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else { rf_done = 1; /* done */
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RF_INT_UPDATE; } /* update int req */
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return SCPE_OK;
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}
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/* Photocell unit service */
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t_stat pcell_svc (UNIT *uptr)
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{
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rf_sta = rf_sta | RFS_PCA; /* set photocell */
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if (rf_sta & RFS_PIE) { /* int enable? */
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sim_activate (&pcell_unit, RF_NUMWD * rf_time);
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int_req = int_req | INT_RF; }
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat rf_reset (DEVICE *dptr)
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{
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if (dev_enb & INT_RF) dev_enb = dev_enb & ~INT_DF; /* either DF or RF */
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rf_sta = rf_da = 0;
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rf_done = 1;
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int_req = int_req & ~INT_RF; /* clear interrupt */
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sim_cancel (&rf_unit);
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sim_cancel (&pcell_unit);
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return SCPE_OK;
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}
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/* Bootstrap routine */
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#define OS8_START 07750
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#define OS8_LEN (sizeof (os8_rom) / sizeof (int32))
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#define DM4_START 00200
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#define DM4_LEN (sizeof (dm4_rom) / sizeof (int32))
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static const int32 os8_rom[] = {
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07600, /* 7750, CLA CLL ; also word count */
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06603, /* 7751, DMAR ; also address */
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06622, /* 7752, DFSC ; done? */
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05352, /* 7753, JMP .-1 ; no */
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05752 /* 7754, JMP @.-2 ; enter boot */
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};
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static const int32 dm4_rom[] = {
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00200, 07600, /* 0200, CLA CLL */
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00201, 06603, /* 0201, DMAR ; read */
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00202, 06622, /* 0202, DFSC ; done? */
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00203, 05202, /* 0203, JMP .-1 ; no */
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00204, 05600, /* 0204, JMP @.-4 ; enter boot */
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07750, 07576, /* 7750, 7576 ; word count */
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07751, 07576 /* 7751, 7576 ; address */
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};
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t_stat rf_boot (int32 unitno)
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{
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int32 i;
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extern int32 sim_switches, saved_PC;
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if (sim_switches & SWMASK ('D')) {
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for (i = 0; i < DM4_LEN; i = i + 2)
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M[dm4_rom[i]] = dm4_rom[i + 1];
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saved_PC = DM4_START; }
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else { for (i = 0; i < OS8_LEN; i++)
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M[OS8_START + i] = os8_rom[i];
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saved_PC = OS8_START; }
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return SCPE_OK;
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}
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