a9fd3dd518
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 1.3 3.8-2 1.3.1 SCP and libraries - Added line history capability for *nix hosts. - Added "SHOW SHOW" and "SHOW <dev> SHOW" commands. 1.3.2 1401 - Added "no rewind" option to magtape boot. 1.3.3 PDP-11 - Added RD32 support to RQ - Added debug support to RL 1.3.4 PDP-8 - Added FPP support (many thanks to Rick Murphy for debugging the code) 1.3.5 VAX-11/780 - Added AUTORESTART switch support, and VMS REBOOT command support 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
486 lines
24 KiB
C
486 lines
24 KiB
C
/* id_defs.h: Interdata 16b/32b simulator definitions
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Copyright (c) 2000-2010, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The author gratefully acknowledges the help of Carl Friend and Al Kossow,
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who provided key documents about the Interdata product line.
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22-May-10 RMS Added check for 64b definitions
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09-Mar-06 RMS Increased register sets to architectural limit
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25-Jan-04 RMS Removed local logging support
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22-Sep-03 RMS Added additional instruction decode types
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21-Jun-03 RMS Changed subroutine argument for ARM compiler conflict
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25-Apr-03 RMS Revised for extended file support
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28-Feb-03 RMS Changed magtape device default to 0x85
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*/
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#ifndef _ID_DEFS_H_
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#define _ID_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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#if defined(USE_INT64) || defined(USE_ADDR64)
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#error "Interdata 16/32 does not support 64b values!"
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#endif
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/* Simulator stop codes */
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#define STOP_RSRV 1 /* undef instr */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_WAIT 4 /* wait */
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#define STOP_VFU 5 /* runaway VFU */
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/* Memory */
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#define PAWIDTH16 16
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#define PAWIDTH16E 18
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#define PAWIDTH32 20
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#define MAXMEMSIZE16 (1u << PAWIDTH16) /* max mem size, 16b */
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#define MAXMEMSIZE16E (1u << PAWIDTH16E) /* max mem size, 16b E */
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#define MAXMEMSIZE32 (1u << PAWIDTH32) /* max mem size, 32b */
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#define PAMASK16 (MAXMEMSIZE16 - 1) /* phys mem mask */
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#define PAMASK16E (MAXMEMSIZE16E - 1)
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#define PAMASK32 (MAXMEMSIZE32 - 1)
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#define MEMSIZE (cpu_unit.capac) /* act memory size */
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#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
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/* Single precision floating point registers */
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#if defined (IFP_IN_MEM)
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#define ReadFReg(r) (fp_in_hwre? \
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F[(r) >> 1]: ReadF (((r) << 1) & ~3, P))
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#define WriteFReg(r,v) if (fp_in_hwre) F[(r) >> 1] = (v); \
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else WriteF (((r) << 1) & ~3, (v), P)
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#else
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#define ReadFReg(r) (F[(r) >> 1])
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#define WriteFReg(r,v) F[(r) >> 1] = (v)
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#endif
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/* Double precision floating point registers */
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typedef struct {
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uint32 h; /* high 32b */
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uint32 l; /* low 32b */
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} dpr_t;
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/* Architectural constants */
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#define VAMASK16 (0xFFFF) /* 16b virt addr */
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#define VAMASK32 (0x000FFFFF) /* 32b virt addr */
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#define SIGN8 0x80 /* 8b sign bit */
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#define DMASK8 0xFF /* 8b data mask */
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#define MMASK8 0x7F /* 8b magnitude mask */
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#define SIGN16 0x8000 /* 16b sign bit */
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#define DMASK16 0xFFFF /* 16b data mask */
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#define MMASK16 0x7FFF /* 16b magnitude mask */
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#define SIGN32 0x80000000 /* 32b sign bit */
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#define DMASK32 0xFFFFFFFF /* 32b data mask */
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#define MMASK32 0x7FFFFFFF /* 32b magn mask */
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#define CC_C 0x8 /* carry */
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#define CC_V 0x4 /* overflow */
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#define CC_G 0x2 /* greater than */
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#define CC_L 0x1 /* less than */
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#define CC_MASK (CC_C | CC_V | CC_G | CC_L)
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#define PSW_WAIT 0x8000 /* wait */
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#define PSW_EXI 0x4000 /* ext intr enable */
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#define PSW_MCI 0x2000 /* machine check enable */
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#define PSW_AFI 0x1000 /* arith fault enb */
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#define PSW_AIO 0x0800 /* auto I/O int enable */
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#define PSW_FPF 0x0400 /* flt fault enb, 16b */
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#define PSW_REL 0x0400 /* reloc enb, 32b */
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#define PSW_SQI 0x0200 /* sys q int enable */
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#define PSW_PRO 0x0100 /* protect mode */
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#define PSW_V_MAP 4 /* mem map, 16b */
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#define PSW_M_MAP 0xF
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#define PSW_MAP (PSW_M_MAP << PSW_V_MAP)
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#define PSW_V_REG 4 /* reg set, 32b */
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#define PSW_M_REG 0xF
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#define PSW_ID4 0xF40F /* I3, I4 PSW */
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#define PSW_x16 0xFF0F /* 7/16, 8/16 PSW */
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#define PSW_816E 0xFFFF /* 8/16E PSW */
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#define PSW_x32 0xFFFF /* 7/32, 8/32 PSW */
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#define MCKOPSW 0x20 /* mchk old PSW, 32b */
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#define FPFPSW 0x28 /* flt fault PSW, 16b */
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#define ILOPSW 0x30 /* ill op PSW */
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#define MCKPSW 0x38 /* mach chk PSW */
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#define EXIPSW 0x40 /* ext intr PSW, 16b */
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#define AFIPSW 0x48 /* arith flt PSW */
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#define SQP 0x80 /* system queue ptr */
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#define SQIPSW 0x82 /* sys q int PSW, 16b */
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#define SQOP 0x8A /* sys q ovf ptr, 16b */
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#define SQVPSW 0x8C /* sys q ovf PSW, 16b */
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#define SQTPSW 0x88 /* sys q int PSW, 32b */
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#define MPRPSW 0x90 /* mprot int PSW, 32b */
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#define SVCAP 0x94 /* svc arg ptr, 16b */
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#define SVOPS 0x96 /* svc old PS, 16b */
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#define SVOPC 0x98 /* svc old PC, 16b */
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#define SVNPS32 0x98 /* svc new PS, 32b */
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#define SVNPS 0x9A /* svc new PS, 16b */
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#define SVNPC 0x9C /* svc new PC */
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#define INTSVT 0xD0 /* int service table */
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#define AL_DEV 0x78 /* autoload: dev */
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#define AL_IOC 0x79 /* command */
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#define AL_DSKU 0x7A /* disk unit */
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#define AL_DSKT 0x7B /* disk type */
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#define AL_DSKC 0x7C /* disk ctrl */
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#define AL_SCH 0x7D /* sel chan */
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#define AL_EXT 0x7E /* OS extension */
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#define AL_BUF 0x80 /* buffer start */
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#define Q16_SLT 0 /* list: # slots */
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#define Q16_USD 1 /* # in use */
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#define Q16_TOP 2 /* current top */
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#define Q16_BOT 3 /* next bottom */
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#define Q16_BASE 4 /* base of q */
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#define Q16_SLNT 2 /* slot length */
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#define Q32_SLT 0 /* list: # slots */
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#define Q32_USD 2 /* # in use */
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#define Q32_TOP 4 /* current top */
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#define Q32_BOT 6 /* next bottom */
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#define Q32_BASE 8 /* base of q */
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#define Q32_SLNT 4 /* slot length */
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/* CPU event flags */
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#define EV_MAC 0x01 /* MAC interrupt */
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#define EV_BLK 0x02 /* block I/O in prog */
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#define EV_INT 0x04 /* interrupt pending */
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#define EV_WAIT 0x08 /* wait state pending */
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/* Block I/O state */
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struct BlockIO {
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uint32 dfl; /* devno, flags */
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uint32 cur; /* current addr */
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uint32 end; /* end addr */
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};
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#define BL_RD 0x8000 /* block read */
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#define BL_LZ 0x4000 /* skip 0's */
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/* Instruction decode ROM, for all, 16b, 32b */
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#define OP_UNDEF 0x0000 /* undefined */
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#define OP_NO 0x0001 /* all: short or fp rr */
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#define OP_RR 0x0002 /* all: reg-reg */
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#define OP_RS 0x0003 /* 16b: reg-storage */
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#define OP_RI1 0x0003 /* 32b: reg-imm 16b */
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#define OP_RX 0x0004 /* all: reg-mem */
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#define OP_RXB 0x0005 /* all: reg-mem, rd BY */
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#define OP_RXH 0x0006 /* all: reg-mem, rd HW */
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#define OP_RXF 0x0007 /* 32b: reg-mem, rd FW */
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#define OP_RI2 0x0008 /* 32b: reg-imm 32b */
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#define OP_MASK 0x000F
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#define OP_ID4 0x0010 /* 16b: ID4 */
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#define OP_716 0x0020 /* 16b: 7/16 */
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#define OP_816 0x0040 /* 16b: 8/16 */
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#define OP_816E 0x0080 /* 16b: 8/16E */
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#define OP_DPF 0x4000 /* all: hwre FP */
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#define OP_PRV 0x8000 /* all: privileged */
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#define OP_TYPE(x) (decrom[(x)] & OP_MASK)
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#define OP_DPFP(x) (decrom[(x)] & OP_DPF)
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/* Device information block */
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typedef struct {
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uint32 dno; /* device number */
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int32 sch; /* sch */
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uint32 irq; /* interrupt */
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uint8 *tplte; /* template */
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uint32 (*iot)(uint32 d, uint32 o, uint32 dat);
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void (*ini)(t_bool f);
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} DIB;
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#define TPL_END 0xFF /* template end */
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/* Device select return codes */
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#define BY 0 /* 8b only */
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#define HW 1 /* 8b/16b */
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/* I/O operations */
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#define IO_ADR 0x0 /* address select */
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#define IO_RD 0x1 /* read byte */
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#define IO_RH 0x2 /* read halfword */
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#define IO_WD 0x3 /* write byte */
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#define IO_WH 0x4 /* write halfword */
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#define IO_OC 0x5 /* output command */
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#define IO_SS 0x6 /* sense status */
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/* Device command byte */
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#define CMD_V_INT 6 /* interrupt control */
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#define CMD_M_INT 0x3
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#define CMD_IENB 1 /* enable */
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#define CMD_IDIS 2 /* disable */
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#define CMD_IDSA 3 /* disarm */
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#define CMD_GETINT(x) (((x) >> CMD_V_INT) & CMD_M_INT)
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/* Device status byte */
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#define STA_BSY 0x8 /* busy */
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#define STA_EX 0x4 /* examine status */
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#define STA_EOM 0x2 /* end of medium */
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#define STA_DU 0x1 /* device unavailable */
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/* Default device numbers */
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#define DEV_LOW 0x01 /* lowest intr dev */
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#define DEV_MAX 0xFF /* highest intr dev */
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#define DEVNO (DEV_MAX + 1) /* number of devices */
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#define d_DS 0x01 /* display, switches */
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#define d_TT 0x02 /* teletype */
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#define d_PT 0x03 /* reader */
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#define d_CD 0x04 /* card reader */
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#define d_TTP 0x10 /* PAS as console */
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#define d_PAS 0x10 /* first PAS */
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#define o_PASX 0x01 /* offset to xmt */
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#define d_LPT 0x62 /* line printer */
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#define d_PIC 0x6C /* interval timer */
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#define d_LFC 0x6D /* line freq clk */
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#define d_MT 0x85 /* magtape */
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#define o_MT0 0x10
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#define d_DPC 0xB6 /* disk controller */
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#define o_DP0 0x10
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#define o_DPF 0x01 /* offset to fixed */
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#define d_FD 0xC1 /* floppy disk */
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#define d_SCH 0xF0 /* selector chan */
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#define d_IDC 0xFB /* MSM disk ctrl */
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#define o_ID0 0x01
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/* Interrupts
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To make interrupt flags independent of device numbers, each device is
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assigned an interrupt flag in one of four interrupt words
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word 0 DMA devices
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word 1 programmed I/O devices
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word 2-3 PAS devices
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Devices are identified by a level and a bit within a level. Priorities
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run low to high in the array, right to left within words
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*/
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#define INTSZ 4 /* interrupt words */
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#define SCH_NUMCH 4 /* #channels */
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#define ID_NUMDR 4 /* # MSM drives */
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#define DP_NUMDR 4 /* # DPC drives */
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#define MT_NUMDR 4 /* # MT drives */
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/* Word 0, DMA devices */
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#define i_SCH 0 /* highest priority */
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#define i_IDC (i_SCH + SCH_NUMCH) /* MSM disk ctrl */
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#define i_DPC (i_IDC + ID_NUMDR + 1) /* cartridge disk ctrl */
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#define i_MT (i_DPC + DP_NUMDR + 1) /* magtape */
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#define l_SCH 0
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#define l_IDC 0
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#define l_DPC 0
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#define l_MT 0
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#define v_SCH (l_SCH * 32) + i_SCH
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#define v_IDC (l_IDC * 32) + i_IDC
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#define v_DPC (l_DPC * 32) + i_DPC
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#define v_MT (l_MT * 32) + i_MT
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/* Word 1, programmed I/O devices */
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#define i_PIC 0 /* precision clock */
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#define i_LFC 1 /* line clock */
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#define i_FD 2 /* floppy disk */
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#define i_CD 3 /* card reader */
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#define i_LPT 4 /* line printer */
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#define i_PT 5 /* paper tape */
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#define i_TT 6 /* teletype */
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#define i_DS 7 /* display */
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#define i_TTP 10 /* PAS console */
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#define l_PIC 1
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#define l_LFC 1
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#define l_FD 1
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#define l_CD 1
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#define l_LPT 1
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#define l_PT 1
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#define l_TT 1
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#define l_DS 1
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#define l_TTP 1
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#define v_PIC (l_PIC * 32) + i_PIC
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#define v_LFC (l_LFC * 32) + i_LFC
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#define v_FD (l_FD * 32) + i_FD
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#define v_CD (l_CD * 32) + i_CD
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#define v_LPT (l_LPT * 32) + i_LPT
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#define v_PT (l_PT * 32) + i_PT
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#define v_TT (l_TT * 32) + i_TT
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#define v_DS (l_DS * 32) + i_DS
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#define v_TTP (l_TTP * 32) + i_TTP
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/* Word 2-3, PAS devices */
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#define i_PAS 0
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#define l_PAS 2
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#define v_PAS (l_PAS * 32) + i_PAS
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#define v_PASX (v_PAS + 1) /* offset to xmt */
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/* I/O macros */
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#define SET_INT(v) int_req[(v) >> 5] = int_req[(v) >> 5] | (1u << ((v) & 0x1F))
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#define CLR_INT(v) int_req[(v) >> 5] = int_req[(v) >> 5] & ~(1u << ((v) & 0x1F))
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#define SET_ENB(v) int_enb[(v) >> 5] = int_enb[(v) >> 5] | (1u << ((v) & 0x1F))
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#define CLR_ENB(v) int_enb[(v) >> 5] = int_enb[(v) >> 5] & ~(1u << ((v) & 0x1F))
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
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/* Device accessible macro */
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#define DEV_ACC(d) (dev_tab[d] && !sch_blk (d))
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/* Automatic I/O channel programs, 16b */
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#define CCB16_CHN -4 /* chain */
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#define CCB16_DEV -2 /* dev no */
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#define CCB16_STS -1 /* status */
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#define CCB16_CCW 0 /* cmd wd */
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#define CCB16_STR 2 /* start */
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#define CCB16_END 4 /* end */
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#define CCB16_IOC 6 /* OC byte */
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#define CCB16_TRM 7 /* term byte */
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#define CCW16_INIT 0x8000 /* init */
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#define CCW16_NOP 0x4000 /* nop */
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#define CCW16_V_FNC 12 /* function */
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#define CCW16_M_FNC 0x3
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#define CCW16_FNC(x) (((x) >> CCW16_V_FNC) & CCW16_M_FNC)
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#define CCW16_RD 0 /* read */
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#define CCW16_WR 1 /* write */
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#define CCW16_DMT 2 /* dec mem */
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#define CCW16_NUL 3 /* null */
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#define CCW16_TRM 0x0400 /* term char */
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#define CCW16_Q 0x0200 /* queue */
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#define CCW16_HI 0x0100 /* queue hi */
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#define CCW16_OC 0x0080 /* OC */
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#define CCW16_CHN 0x0020 /* chain */
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#define CCW16_CON 0x0010 /* continue */
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#define CCW16_V_BPI 0 /* bytes per int */
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#define CCW16_M_BPI 0xF
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#define CCW16_BPI(x) (((x) >> CCW16_V_BPI) & CCW16_M_BPI)
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/* Automatic I/O channel programs, 32b */
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#define CCB32_CCW 0 /* cmd wd */
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#define CCB32_B0C 2 /* buf 0 cnt */
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#define CCB32_B0E 4 /* buf 0 end */
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#define CCB32_CHK 8 /* check word */
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#define CCB32_B1C 10 /* buf 1 cnt */
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#define CCB32_B1E 12 /* buf 1 end */
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#define CCB32_TAB 16 /* trans table */
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#define CCB32_SUB 20 /* subroutine */
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#define CCW32_V_STA 8 /* status */
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#define CCW32_M_STA 0xFF
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#define CCW32_STA(x) (((x) >> CCW32_V_STA) & CCW32_M_STA)
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#define CCW32_EXE 0x80 /* execute */
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#define CCW32_CRC 0x10
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#define CCW32_B1 0x08 /* buffer 1 */
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#define CCW32_WR 0x04 /* write */
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#define CCW32_TL 0x02 /* translate */
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#define CCW32_FST 0x01 /* fast mode */
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/* MAC, 32b */
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#define P 0 /* physical */
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#define VE 1 /* virtual inst */
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#define VR 2 /* virtual read */
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#define VW 3 /* virtual write */
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#define MAC_BASE 0x300 /* MAC base */
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#define MAC_STA 0x340 /* MAC status */
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#define MAC_LNT 16
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#define VA_V_OFF 0 /* offset */
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#define VA_M_OFF 0xFFFF
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#define VA_GETOFF(x) (((x) >> VA_V_OFF) & VA_M_OFF)
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#define VA_V_SEG 16 /* segment */
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#define VA_M_SEG 0xF
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#define VA_GETSEG(x) (((x) >> VA_V_SEG) & VA_M_SEG)
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#define SRF_MASK 0x000FFF00 /* base mask */
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#define SRL_MASK 0x0FF00000 /* limit mask */
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#define GET_SRL(x) ((((x) & SRL_MASK) >> 12) + 0x100)
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#define SR_EXP 0x80 /* execute prot */
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#define SR_WPI 0x40 /* wr prot int */
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#define SR_WRP 0x20 /* wr prot */
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#define SR_PRS 0x10 /* present */
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#define SR_MASK (SRF_MASK|SRL_MASK|SR_EXP|SR_WPI|SR_WRP|SR_PRS)
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#define MACS_L 0x10 /* limit viol */
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#define MACS_NP 0x08 /* not present */
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#define MACS_WP 0x04 /* write prot */
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#define MACS_WI 0x02 /* write int */
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#define MACS_EX 0x01 /* exec prot */
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/* Miscellaneous */
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|
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#define TMR_LFC 0 /* LFC = timer 0 */
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#define TMR_PIC 1 /* PIC = timer 1 */
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#define LPT_WIDTH 132
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#define VFU_LNT 132
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#define MIN(x,y) (((x) < (y))? (x): (y))
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#define MAX(x,y) (((x) > (y))? (x): (y))
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/* Function prototypes */
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int32 int_chg (uint32 irq, int32 dat, int32 armdis);
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int32 io_2b (int32 val, int32 pos, int32 old);
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uint32 IOReadB (uint32 loc);
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void IOWriteB (uint32 loc, uint32 val);
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uint32 IOReadH (uint32 loc);
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|
void IOWriteH (uint32 loc, uint32 val);
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|
uint32 ReadF (uint32 loc, uint32 rel);
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void WriteF (uint32 loc, uint32 val, uint32 rel);
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uint32 IOReadBlk (uint32 loc, uint32 cnt, uint8 *buf);
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uint32 IOWriteBlk (uint32 loc, uint32 cnt, uint8 *buf);
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void sch_adr (uint32 ch, uint32 dev);
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|
t_bool sch_actv (uint32 sch, uint32 devno);
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|
void sch_stop (uint32 sch);
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|
uint32 sch_wrmem (uint32 sch, uint8 *buf, uint32 cnt);
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|
uint32 sch_rdmem (uint32 sch, uint8 *buf, uint32 cnt);
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|
t_stat set_sch (UNIT *uptr, int32 val, char *cptr, void *desc);
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|
t_stat set_dev (UNIT *uptr, int32 val, char *cptr, void *desc);
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|
t_stat show_sch (FILE *st, UNIT *uptr, int32 val, void *desc);
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|
t_stat show_dev (FILE *st, UNIT *uptr, int32 val, void *desc);
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#endif
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