a9fd3dd518
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 1.3 3.8-2 1.3.1 SCP and libraries - Added line history capability for *nix hosts. - Added "SHOW SHOW" and "SHOW <dev> SHOW" commands. 1.3.2 1401 - Added "no rewind" option to magtape boot. 1.3.3 PDP-11 - Added RD32 support to RQ - Added debug support to RL 1.3.4 PDP-8 - Added FPP support (many thanks to Rick Murphy for debugging the code) 1.3.5 VAX-11/780 - Added AUTORESTART switch support, and VMS REBOOT command support 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
450 lines
20 KiB
C
450 lines
20 KiB
C
/* vax780_defs.h: VAX 780 model-specific definitions file
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Copyright (c) 2004-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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19-Nov-08 RMS Moved I/O support routines to I/O library
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29-Apr-07 RMS Modified model-specific reserved operand check macros
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to reflect 780 microcode patches (found by Naoki Hamada)
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29-Oct-06 RMS Added clock coscheduler function
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17-May-06 RMS Added CR11/CD11 support (from John Dundas)
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10-May-06 RMS Added model-specific reserved operand check macros
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This file covers the VAX 11/780, the first VAX.
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System memory map
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0000 0000 - 1FFF FFFF main memory
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2000 0000 - 2001 FFFF nexus register space
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2002 0000 - 200F FFFF reserved
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2010 0000 - 2013 FFFF Unibus address space, Unibus 0
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2014 0000 - 2017 FFFF Unibus address space, Unibus 1
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2018 0000 - 201B FFFF Unibus address space, Unibus 2
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201C 0000 - 201F FFFF Unibus address space, Unibus 3
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2020 0000 - 3FFF FFFF reserved
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*/
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#ifndef FULL_VAX
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#define FULL_VAX 1
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#endif
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#ifndef _VAX_780_DEFS_H_
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#define _VAX_780_DEFS_H_ 1
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/* Microcode constructs */
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#define VAX780_SID (1 << 24) /* system ID */
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#define VAX780_ECO (7 << 19) /* ucode revision */
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#define VAX780_PLANT (0 << 12) /* plant (Salem NH) */
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#define VAX780_SN (1234)
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define MCHK_RD_F 0x00 /* read fault */
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#define MCHK_RD_A 0xF4 /* read abort */
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#define MCHK_IBUF 0x0D /* read istream */
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#define VER_FPLA 0x0C /* FPLA version */
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#define VER_WCSP (VER_FPLA) /* WCS primary version */
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#define VER_WCSS 0x12 /* WCS secondary version */
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#define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */
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/* Interrupts */
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#define IPL_HMAX 0x17 /* highest hwre level */
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#define IPL_HMIN 0x14 /* lowest hwre level */
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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/* Nexus constants */
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#define NEXUS_NUM 16 /* number of nexus */
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#define MCTL_NUM 2 /* number of mem ctrl */
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#define MBA_NUM 2 /* number of MBA's */
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#define TR_MCTL0 1 /* nexus assignments */
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#define TR_MCTL1 2
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#define TR_UBA 3
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#define TR_MBA0 8
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#define TR_MBA1 9
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#define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1)
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#define SCB_NEXUS 0x100 /* nexus intr base */
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#define SBI_FAULTS 0xFC000000 /* SBI fault flags */
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/* Internal I/O interrupts - relative except for clock and console */
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#define IPL_CLKINT 0x18 /* clock IPL */
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#define IPL_TTINT 0x14 /* console IPL */
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#define IPL_MCTL0 (0x15 - IPL_HMIN)
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#define IPL_MCTL1 (0x15 - IPL_HMIN)
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#define IPL_UBA (0x15 - IPL_HMIN)
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#define IPL_MBA0 (0x15 - IPL_HMIN)
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#define IPL_MBA1 (0x15 - IPL_HMIN)
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/* Nexus interrupt macros */
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#define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv)
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#define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv)
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/* Machine specific IPRs */
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#define MT_ACCS 40 /* FPA control */
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#define MT_ACCR 41 /* FPA maint */
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#define MT_WCSA 44 /* WCS address */
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#define MT_WCSD 45 /* WCS data */
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#define MT_SBIFS 48 /* SBI fault status */
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#define MT_SBIS 49 /* SBI silo */
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#define MT_SBISC 50 /* SBI silo comparator */
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#define MT_SBIMT 51 /* SBI maint */
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#define MT_SBIER 52 /* SBI error */
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#define MT_SBITA 53 /* SBI timeout addr */
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#define MT_SBIQC 54 /* SBI timeout clear */
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#define MT_MBRK 60 /* microbreak */
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/* Machine specific reserved operand tests */
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/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
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#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
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/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
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#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
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((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
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#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT
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/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */
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#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
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#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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/* Memory */
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#define MAXMEMWIDTH 23 /* max mem, MS780C */
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#define MAXMEMSIZE (1 << MAXMEMWIDTH)
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#define MAXMEMWIDTH_X 27 /* max mem, MS780E */
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#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
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#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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/* Unibus I/O registers */
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#define UBADDRWIDTH 18 /* Unibus addr width */
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#define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */
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#define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */
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#define IOPAGEAWIDTH 13 /* IO addr width */
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#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */
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#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */
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#define UBADDRBASE 0x20100000 /* Unibus addr base */
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#define IOPAGEBASE 0x2013E000 /* IO page base */
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#define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \
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(((uint32) (x)) < (UBADDRBASE + UBADDRSIZE)))
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#define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE)
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/* Nexus register space */
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#define REGAWIDTH 17 /* REG addr width */
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#define REG_V_NEXUS 13 /* nexus number */
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#define REG_M_NEXUS 0xF
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#define REG_V_OFS 2 /* register number */
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#define REG_M_OFS 0x7FF
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#define REGSIZE (1u << REGAWIDTH) /* REG length */
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#define REGBASE 0x20000000 /* REG addr base */
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#define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \
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(((uint32) (x)) < (REGBASE + REGSIZE)))
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#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS)
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#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS)
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/* ROM address space in memory controllers */
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#define ROMAWIDTH 12 /* ROM addr width */
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#define ROMSIZE (1u << ROMAWIDTH) /* ROM size */
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#define ROM0BASE (REGBASE + (TR_MCTL0 << REG_V_NEXUS) + 0x1000)
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#define ROM1BASE (REGBASE + (TR_MCTL1 << REG_V_NEXUS) + 0x1000)
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#define ADDR_IS_ROM0(x) ((((uint32) (x)) >= ROM0BASE) && \
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(((uint32) (x)) < (ROM0BASE + ROMSIZE)))
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#define ADDR_IS_ROM1(x) ((((uint32) (x)) >= ROM1BASE) && \
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(((uint32) (x)) < (ROM1BASE + ROMSIZE)))
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#define ADDR_IS_ROM(x) (ADDR_IS_ROM0 (x) || ADDR_IS_ROM1 (x))
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/* Other address spaces */
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#define ADDR_IS_CDG(x) (0)
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#define ADDR_IS_NVR(x) (0)
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/* Unibus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define WRITE (L_WORD)
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#define WRITEB (L_BYTE)
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/* Common CSI flags */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Timers */
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#define TMR_CLK 0 /* 100Hz clock */
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/* I/O system definitions */
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#define DZ_MUXES 4 /* max # of DZV muxes */
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#define DZ_LINES 8 /* lines per DZV mux */
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#define VH_MUXES 4 /* max # of DHQ muxes */
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#define DLX_LINES 16 /* max # of KL11/DL11's */
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#define DCX_LINES 16 /* max # of DC11's */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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#define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */
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#define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */
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#define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */
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#define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */
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#define DEV_UBUS (1u << DEV_V_UBUS)
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#define DEV_MBUS (1u << DEV_V_MBUS)
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#define DEV_NEXUS (1u << DEV_V_NEXUS)
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#define DEV_FLTA (1u << DEV_V_FLTA)
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#define DEV_QBUS (0)
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#define DEV_Q18 (0)
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#define UNIBUS TRUE /* Unibus only */
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#define DEV_RDX 16 /* default device radix */
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/* Device information block
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For Massbus devices,
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ba = Massbus number
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lnt = Massbus ctrl type
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ack[0] = abort routine
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For Nexus devices,
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ba = Nexus number
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lnt = number of consecutive nexi */
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#define VEC_DEVMAX 4 /* max device vec */
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typedef struct {
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uint32 ba; /* base addr */
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uint32 lnt; /* length */
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t_stat (*rd)(int32 *dat, int32 ad, int32 md);
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t_stat (*wr)(int32 dat, int32 ad, int32 md);
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int32 vnum; /* vectors: number */
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int32 vloc; /* locator */
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int32 vec; /* value */
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int32 (*ack[VEC_DEVMAX])(void); /* ack routine */
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} DIB;
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/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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#define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */
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#define IOLN_DZ 010
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#define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
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#define IOLN_XUB 010
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#define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))
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#define IOLN_RQB 004
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#define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
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#define IOLN_RQC 004
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#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
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#define IOLN_RQD 004
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#define IOBA_RQ (IOPAGEBASE + 012150) /* UDA50 */
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#define IOLN_RQ 004
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#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */
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#define IOLN_TS 004
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#define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */
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#define IOLN_RL 012
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#define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */
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#define IOLN_XQ 020
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#define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */
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#define IOLN_XQB 020
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#define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */
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#define IOLN_TQ 004
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#define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */
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#define IOLN_XU 010
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#define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */
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#define IOLN_CR 010
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#define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */
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#define IOLN_RX 004
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#define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */
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#define IOLN_RY 004
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#define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */
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#define IOLN_QDSS 002
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#define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */
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#define IOLN_HK 040
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#define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */
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#define IOLN_LPT 004
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#define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */
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#define IOLN_PTR 004
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#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
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#define IOLN_PTP 004
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/* Interrupt assignments; within each level, priority is right to left */
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#define INT_V_DZRX 0 /* BR5 */
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#define INT_V_DZTX 1
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#define INT_V_HK 2
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#define INT_V_RL 3
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#define INT_V_RQ 4
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#define INT_V_TQ 5
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#define INT_V_TS 6
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#define INT_V_RY 7
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#define INT_V_XU 8
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#define INT_V_LPT 0 /* BR4 */
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#define INT_V_PTR 1
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#define INT_V_PTP 2
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#define INT_V_CR 3
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_HK (1u << INT_V_HK)
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#define INT_RL (1u << INT_V_RL)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_TS (1u << INT_V_TS)
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#define INT_RY (1u << INT_V_RY)
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#define INT_XU (1u << INT_V_XU)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_CR (1u << INT_V_CR)
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#define IPL_DZRX (0x15 - IPL_HMIN)
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#define IPL_DZTX (0x15 - IPL_HMIN)
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#define IPL_HK (0x15 - IPL_HMIN)
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#define IPL_RL (0x15 - IPL_HMIN)
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#define IPL_RQ (0x15 - IPL_HMIN)
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#define IPL_TQ (0x15 - IPL_HMIN)
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#define IPL_TS (0x15 - IPL_HMIN)
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#define IPL_RY (0x15 - IPL_HMIN)
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#define IPL_XU (0x15 - IPL_HMIN)
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#define IPL_LPT (0x14 - IPL_HMIN)
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#define IPL_PTR (0x14 - IPL_HMIN)
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#define IPL_PTP (0x14 - IPL_HMIN)
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#define IPL_CR (0x14 - IPL_HMIN)
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/* Device vectors */
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#define VEC_Q 0000
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#define VEC_PTR 0070
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#define VEC_PTP 0074
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#define VEC_XQ 0120
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#define VEC_XU 0120
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#define VEC_RQ 0154
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#define VEC_RL 0160
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#define VEC_LPT 0200
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#define VEC_HK 0210
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#define VEC_TS 0224
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#define VEC_CR 0230
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#define VEC_TQ 0260
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#define VEC_RX 0264
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#define VEC_RY 0264
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#define VEC_DZRX 0300
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#define VEC_DZTX 0304
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/* Interrupt macros */
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#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
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#define NVCL(dv) ((IPL_##dv * 32) + TR_##dv)
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#define IREQ(dv) int_req[IPL_##dv]
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#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
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#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* Logging */
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#define LOG_CPU_I 0x1 /* intexc */
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#define LOG_CPU_R 0x2 /* REI */
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#define LOG_CPU_P 0x4 /* context */
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/* Massbus definitions */
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#define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */
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#define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */
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#define MBA_RMASK 0x1F /* max 32 reg */
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#define MBE_NXD 1 /* nx drive */
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#define MBE_NXR 2 /* nx reg */
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#define MBE_GOE 3 /* err on GO */
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/* Boot definitions */
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#define BOOT_MB 0 /* device codes */
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#define BOOT_HK 1 /* for VMB */
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#define BOOT_RL 2
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#define BOOT_UDA 17
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#define BOOT_TK 18
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/* Function prototypes for virtual memory interface */
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int32 Read (uint32 va, int32 lnt, int32 acc);
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void Write (uint32 va, int32 val, int32 lnt, int32 acc);
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/* Function prototypes for physical memory interface (inlined) */
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SIM_INLINE int32 ReadB (uint32 pa);
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SIM_INLINE int32 ReadW (uint32 pa);
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SIM_INLINE int32 ReadL (uint32 pa);
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SIM_INLINE int32 ReadLP (uint32 pa);
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SIM_INLINE void WriteB (uint32 pa, int32 val);
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SIM_INLINE void WriteW (uint32 pa, int32 val);
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SIM_INLINE void WriteL (uint32 pa, int32 val);
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void WriteLP (uint32 pa, int32 val);
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/* Function prototypes for I/O */
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
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int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
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int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf);
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int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf);
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int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf);
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int32 mba_get_bc (uint32 mbus);
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void mba_upd_ata (uint32 mbus, uint32 val);
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void mba_set_exc (uint32 mbus);
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void mba_set_don (uint32 mbus);
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void mba_set_enbdis (uint32 mbus, t_bool dis);
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t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
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void sbi_set_errcnf (void);
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int32 clk_cosched (int32 wait);
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#include "pdp11_io_lib.h"
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#endif
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