9d849283a4
- This change introduces a full refactor of the interrupt subsystem
for the system board (SBD) and the I/O bus (CIO). Interrupt decode
should now be significantly faster, and not require an expensive
calculation on every step.
- The TIMER device has been split into Rev 2 and Rev 3
implementations.
- The optional 3B2/400 Debug Monitor ROMs can now be booted by passing
the "DEMON" argument to the 3B2/400 simulator BOOT command. Any
of the following will cause the Debug Monitor ROM to be booted
instead of the standard 3B2/400 ROM:
sim> BOOT DEMON
sim> BOOT CPU DEMON
sim> BOOT DEMON CPU
506 lines
17 KiB
C
506 lines
17 KiB
C
/* 3b2_rev3_timer.c: 82C54 Interval Timer.
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Copyright (c) 2021, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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/*
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* 82C54 Timer.
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*
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* 82C54 (Rev3) Timer IC has three interval timers, which we treat
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* here as three units.
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*
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* In the 3B2, the three timers are assigned specific purposes:
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*
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* - Timer 0: SYSTEM SANITY TIMER. This timer is normally loaded with
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* a short timeout and allowed to run. If it times out, it
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* will generate an interrupt and cause a system
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* error. Software resets the timer regularly to ensure
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* that it does not time out. It is fed by a 10 kHz
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* clock, so each single counting step of this timer is
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* 100 microseconds.
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*
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* - Timer 1: UNIX INTERVAL TIMER. This is the main timer that drives
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* process switching in Unix. It operates at a fixed rate,
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* and the counter is set up by Unix to generate an
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* interrupt once every 10 milliseconds. The timer is fed
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* by a 100 kHz clock, so each single counting step of
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* this timer is 10 microseconds.
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*
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* - Timer 2: BUS TIMEOUT TIMER. This timer is reset every time the
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* IO bus is accessed, and then stopped when the IO bus
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* responds. It is mainly used to determine when the IO
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* bus is hung (e.g., no card is installed in a given
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* slot, so nothing can respond). When it times out, it
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* generates an interrupt. It is fed by a 500 kHz clock,
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* so each single counting step of this timer is 2
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* microseconds.
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*
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*
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* Implementaiton Notes
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* ====================
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*
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* In general, no attempt has been made to create an accurate
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* emulation of the 82C54 timer. This implementation is truly built
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* for the 3B2, and even more specifically for System V Unix, which is
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* the only operating system ever to have been ported to the 3B2.
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*
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* - The Bus Timeout Timer is not implemented other than a stub that
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* is designed to pass hardware diagnostics. The simulator IO
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* subsystem always sets the correct interrupt directly if the bus
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* will not respond.
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*
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* - The System Sanity Timer is also not implemented other than a
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* stub to pass diagnostics.
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*
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* - The main Unix Interval Timer is implemented as a true SIMH clock
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* when set up for the correct mode. In other modes, it likewise
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* implements a stub designed to pass diagnostics.
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*/
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#include "3b2_cpu.h"
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#include "3b2_csr.h"
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#include "3b2_defs.h"
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#include "3b2_timer.h"
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struct timer_ctr TIMERS[3];
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int32 tmxr_poll = 16667;
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UNIT timer_unit[] = {
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{ UDATA(&timer0_svc, 0, 0) },
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{ UDATA(&timer1_svc, UNIT_IDLE, 0) },
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{ UDATA(&timer2_svc, 0, 0) },
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{ NULL }
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};
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UNIT *timer_clk_unit = &timer_unit[1];
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REG timer_reg[] = {
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{ HRDATAD(DIV0, TIMERS[0].divider, 16, "Divider (0)") },
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{ HRDATAD(COUNT0, TIMERS[0].val, 16, "Count (0)") },
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{ HRDATAD(CTRL0, TIMERS[0].ctrl, 8, "Control (0)") },
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{ HRDATAD(DIV1, TIMERS[1].divider, 16, "Divider (1)") },
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{ HRDATAD(COUNT1, TIMERS[1].val, 16, "Count (1)") },
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{ HRDATAD(CTRL1, TIMERS[1].ctrl, 8, "Control (1)") },
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{ HRDATAD(DIV2, TIMERS[2].divider, 16, "Divider (2)") },
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{ HRDATAD(COUNT2, TIMERS[2].val, 16, "Count (2)") },
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{ HRDATAD(CTRL2, TIMERS[2].ctrl, 8, "Control (2)") },
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{ NULL }
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};
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DEVICE timer_dev = {
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"TIMER", timer_unit, timer_reg, NULL,
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1, 16, 8, 4, 16, 32,
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NULL, NULL, &timer_reset,
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NULL, NULL, NULL, NULL,
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DEV_DEBUG, 0, sys_deb_tab
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};
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t_stat timer_reset(DEVICE *dptr) {
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int32 i;
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memset(&TIMERS, 0, sizeof(struct timer_ctr) * 3);
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for (i = 0; i < 3; i++) {
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timer_unit[i].tmrnum = i;
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timer_unit[i].tmr = (void *)&TIMERS[i];
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}
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/* TODO: I don't think this is right. Verify. */
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/*
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if (!sim_is_running) {
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t = sim_rtcn_init_unit(timer_clk_unit, TPS_CLK, TMR_CLK);
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sim_activate_after_abs(timer_clk_unit, 1000000 / t);
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}
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*/
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return SCPE_OK;
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}
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static void timer_activate(uint8 ctrnum)
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{
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struct timer_ctr *ctr;
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ctr = &TIMERS[ctrnum];
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switch (ctrnum) {
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case TIMER_SANITY:
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if ((csr_data & CSRISTIM) == 0) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] SANITY TIMER: Activating after %d steps\n",
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R[NUM_PC], ctr->val);
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sim_activate_abs(&timer_unit[ctrnum], ctr->val);
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ctr->val--;
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} else {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] SANITY TIMER: Currently disabled, not starting\n",
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R[NUM_PC]);
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}
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break;
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case TIMER_INTERVAL:
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if ((csr_data & CSRITIM) == 0) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] INTERVAL TIMER: Activating after %d ms\n",
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R[NUM_PC], ctr->val);
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sim_activate_after_abs(&timer_unit[ctrnum], ctr->val);
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ctr->val--;
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} else {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] INTERVAL TIMER: Currently disabled, not starting\n",
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R[NUM_PC]);
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}
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break;
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case TIMER_BUS:
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if ((csr_data & CSRITIMO) == 0) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] BUS TIMER: Activating after %d steps\n",
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R[NUM_PC], ctr->val);
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sim_activate_abs(&timer_unit[ctrnum], (ctr->val - 2));
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ctr->val -= 2;
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} else {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] BUS TIMER: Currently disabled, not starting\n",
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R[NUM_PC]);
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}
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break;
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default:
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break;
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}
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}
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void timer_enable(uint8 ctrnum)
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{
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] Enabling timer %d\n",
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R[NUM_PC], ctrnum);
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timer_activate(ctrnum);
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}
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void timer_disable(uint8 ctrnum)
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{
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] Disabling timer %d\n",
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R[NUM_PC], ctrnum);
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sim_cancel(&timer_unit[ctrnum]);
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}
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/*
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* Sanity Timer
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*/
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t_stat timer0_svc(UNIT *uptr)
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{
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struct timer_ctr *ctr;
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ctr = (struct timer_ctr *)uptr->tmr;
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if (ctr->enabled) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] TIMER 0 COMPLETION.\n",
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R[NUM_PC]);
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if (!(csr_data & CSRISTIM)) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] TIMER 0 NMI IRQ.\n",
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R[NUM_PC]);
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ctr->val = 0xffff;
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cpu_nmi = TRUE;
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CSRBIT(CSRSTIMO, TRUE);
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CPU_SET_INT(INT_BUS_TMO);
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}
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}
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return SCPE_OK;
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}
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/*
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* Interval Timer
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*/
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t_stat timer1_svc(UNIT *uptr)
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{
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struct timer_ctr *ctr;
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int32 t;
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ctr = (struct timer_ctr *)uptr->tmr;
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if (ctr->enabled && !(csr_data & CSRITIM)) {
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/* Fire the IPL 15 clock interrupt */
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CSRBIT(CSRCLK, TRUE);
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CPU_SET_INT(INT_CLOCK);
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}
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t = sim_rtcn_calb(TPS_CLK, TMR_CLK);
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sim_activate_after_abs(uptr, 1000000/TPS_CLK);
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tmxr_poll = t;
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return SCPE_OK;
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}
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/*
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* Bus Timeout Timer
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*/
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t_stat timer2_svc(UNIT *uptr)
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{
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struct timer_ctr *ctr;
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ctr = (struct timer_ctr *)uptr->tmr;
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if (ctr->enabled && TIMER_RW(ctr) == CLK_LSB) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] TIMER 2 COMPLETION.\n",
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R[NUM_PC]);
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if (!(csr_data & CSRITIMO)) {
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sim_debug(EXECUTE_MSG, &timer_dev,
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"[%08x] TIMER 2 IRQ.\n",
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R[NUM_PC]);
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ctr->val = 0xffff;
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CSRBIT(CSRTIMO, TRUE);
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CPU_SET_INT(INT_BUS_TMO);
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/* Also trigger a bus abort */
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cpu_abort(NORMAL_EXCEPTION, EXTERNAL_MEMORY_FAULT);
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}
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}
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return SCPE_OK;
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}
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uint32 timer_read(uint32 pa, size_t size)
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{
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uint32 reg;
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uint16 ctr_val;
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uint8 ctrnum, retval;
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struct timer_ctr *ctr;
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reg = pa - TIMERBASE;
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ctrnum = (reg >> 2) & 0x3;
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ctr = &TIMERS[ctrnum];
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switch (reg) {
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case TIMER_REG_DIVA:
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case TIMER_REG_DIVB:
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case TIMER_REG_DIVC:
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ctr_val = ctr->val;
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switch (TIMER_RW(ctr)) {
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case CLK_LSB:
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retval = ctr_val & 0xff;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [LSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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break;
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case CLK_MSB:
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retval = (ctr_val & 0xff00) >> 8;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [MSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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break;
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case CLK_LMB:
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if (ctr->r_ctrl_latch) {
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ctr->r_ctrl_latch = FALSE;
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retval = ctr->ctrl_latch;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [LATCH CTRL] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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} else if (ctr->r_cnt_latch) {
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if (ctr->r_lmb) {
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ctr->r_lmb = FALSE;
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retval = (ctr->cnt_latch & 0xff00) >> 8;
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ctr->r_cnt_latch = FALSE;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [LATCH DATA MSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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} else {
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ctr->r_lmb = TRUE;
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retval = ctr->cnt_latch & 0xff;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [LATCH DATA LSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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}
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} else if (ctr->r_lmb) {
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ctr->r_lmb = FALSE;
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retval = (ctr_val & 0xff00) >> 8;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [LMB - MSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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} else {
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ctr->r_lmb = TRUE;
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retval = ctr_val & 0xff;
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] [%d] [LMB - LSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, retval, retval);
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}
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break;
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default:
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retval = 0;
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}
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return retval;
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case TIMER_REG_CTRL:
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return ctr->ctrl;
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case TIMER_CLR_LATCH:
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/* Clearing the timer latch has a side-effect
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of also clearing pending interrupts */
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CSRBIT(CSRCLK, FALSE);
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CPU_CLR_INT(INT_CLOCK);
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return 0;
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default:
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/* Unhandled */
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sim_debug(READ_MSG, &timer_dev,
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"[%08x] UNHANDLED TIMER READ. ADDR=%08x\n",
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R[NUM_PC], pa);
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return 0;
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}
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}
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void handle_timer_write(uint8 ctrnum, uint32 val)
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{
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struct timer_ctr *ctr;
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UNIT *unit = &timer_unit[ctrnum];
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ctr = &TIMERS[ctrnum];
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ctr->enabled = TRUE;
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switch(TIMER_RW(ctr)) {
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case CLK_LSB:
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ctr->divider = val & 0xff;
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ctr->val = ctr->divider;
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sim_debug(WRITE_MSG, &timer_dev,
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"[%08x] [%d] [LSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, val & 0xff, val & 0xff);
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timer_activate(ctrnum);
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break;
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case CLK_MSB:
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ctr->divider = (val & 0xff) << 8;
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ctr->val = ctr->divider;
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sim_debug(WRITE_MSG, &timer_dev,
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"[%08x] [%d] [MSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, val & 0xff, val & 0xff);
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timer_activate(ctrnum);
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break;
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case CLK_LMB:
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if (ctr->w_lmb) {
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ctr->w_lmb = FALSE;
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ctr->divider = (uint16) ((ctr->divider & 0x00ff) | ((val & 0xff) << 8));
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ctr->val = ctr->divider;
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sim_debug(WRITE_MSG, &timer_dev,
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"[%08x] [%d] [LMB - MSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, val & 0xff, val & 0xff);
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timer_activate(ctrnum);
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} else {
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ctr->w_lmb = TRUE;
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ctr->divider = (ctr->divider & 0xff00) | (val & 0xff);
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ctr->val = ctr->divider;
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sim_debug(WRITE_MSG, &timer_dev,
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"[%08x] [%d] [LMB - LSB] val=%d (0x%x)\n",
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R[NUM_PC], ctrnum, val & 0xff, val & 0xff);
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}
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break;
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default:
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break;
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}
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}
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void timer_write(uint32 pa, uint32 val, size_t size)
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{
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uint8 reg, ctrnum;
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struct timer_ctr *ctr;
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reg = (uint8) (pa - TIMERBASE);
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switch(reg) {
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case TIMER_REG_DIVA:
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handle_timer_write(0, val);
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break;
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case TIMER_REG_DIVB:
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handle_timer_write(1, val);
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break;
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case TIMER_REG_DIVC:
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handle_timer_write(2, val);
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break;
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case TIMER_REG_CTRL:
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ctrnum = (val >> 6) & 3;
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if (ctrnum == 3) {
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sim_debug(WRITE_MSG, &timer_dev,
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"[%08x] READ BACK COMMAND. DATA=%02x\n",
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R[NUM_PC], val);
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if (val & 2) {
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ctr = &TIMERS[0];
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if ((val & 0x20) == 0) {
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ctr->ctrl_latch = (uint16) TIMERS[2].ctrl;
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ctr->r_ctrl_latch = TRUE;
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}
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if ((val & 0x20) == 0) {
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ctr->cnt_latch = ctr->val;
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ctr->r_cnt_latch = TRUE;
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}
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}
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if (val & 4) {
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ctr = &TIMERS[1];
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if ((val & 0x10) == 0) {
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ctr->ctrl_latch = (uint16) TIMERS[2].ctrl;
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ctr->r_ctrl_latch = TRUE;
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}
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if ((val & 0x20) == 0) {
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ctr->cnt_latch = ctr->val;
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ctr->r_cnt_latch = TRUE;
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}
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}
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if (val & 8) {
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ctr = &TIMERS[2];
|
|
if ((val & 0x10) == 0) {
|
|
ctr->ctrl_latch = (uint16) TIMERS[2].ctrl;
|
|
ctr->r_ctrl_latch = TRUE;
|
|
}
|
|
if ((val & 0x20) == 0) {
|
|
ctr->cnt_latch = ctr->val;
|
|
ctr->r_cnt_latch = TRUE;
|
|
}
|
|
}
|
|
} else {
|
|
sim_debug(WRITE_MSG, &timer_dev,
|
|
"[%08x] Timer Control Write: timer %d => %02x\n",
|
|
R[NUM_PC], ctrnum, val & 0xff);
|
|
ctr = &TIMERS[ctrnum];
|
|
ctr->ctrl = (uint8) val;
|
|
ctr->enabled = FALSE;
|
|
ctr->w_lmb = FALSE;
|
|
ctr->r_lmb = FALSE;
|
|
ctr->val = 0xffff;
|
|
ctr->divider = 0xffff;
|
|
}
|
|
break;
|
|
case TIMER_CLR_LATCH:
|
|
sim_debug(WRITE_MSG, &timer_dev,
|
|
"[%08x] unexpected write to clear timer latch\n",
|
|
R[NUM_PC]);
|
|
break;
|
|
default:
|
|
sim_debug(WRITE_MSG, &timer_dev,
|
|
"[%08x] unknown timer register: %d\n",
|
|
R[NUM_PC], reg);
|
|
}
|
|
}
|