5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
504 lines
23 KiB
C
504 lines
23 KiB
C
/* i7094_defs.h: IBM 7094 simulator definitions
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Copyright (c) 2003-2011, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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This simulator incorporates prior work by Paul Pierce, Dave Pitts, and Rob
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Storey. Tom Van Vleck, Stan Dunten, Jerry Saltzer, and other CTSS veterans
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helped to reconstruct the CTSS hardware RPQ's. Dave Pitts gets special
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thanks for patiently coaching me through IBSYS debug.
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25-Mar-11 RMS Updated SDC mask based on 7230 documentation
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22-May-10 RMS Added check for 64b addresses
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*/
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#ifndef I7094_DEFS_H_
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#define I7094_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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/* Rename of global PC variable to avoid namespace conflicts on some platforms */
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#define PC PC_Global
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#if defined(USE_ADDR64)
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#error "7094 does not support 64b addresses!"
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#endif
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/* Simulator stop codes */
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#define STOP_HALT 1 /* halted */
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#define STOP_IBKPT 2 /* breakpoint */
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#define STOP_ILLEG 3 /* illegal instr */
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#define STOP_DIVCHK 4 /* divide check */
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#define STOP_XEC 5 /* XCT loop */
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#define STOP_ASTOP 6 /* address stop */
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#define STOP_NXCHN 7 /* nx channel */
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#define STOP_7909 8 /* ill inst to 7909 */
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#define STOP_NT7909 9 /* ill inst to !7909 */
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#define STOP_NXDEV 10 /* nx device */
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#define STOP_ILLCHI 11 /* illegal channel op */
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#define STOP_WRP 12 /* write protect */
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#define STOP_ILLIOP 13 /* illegal I/O op */
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#define STOP_INVFMT 14 /* invalid disk format */
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#define STOP_NOIFREE 15 /* 7750: no buf for inp */
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#define STOP_NOOFREE 16 /* 7750: no buf for out */
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#define STOP_INVLIN 17 /* 7750: invalid line# */
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#define STOP_INVMSG 18 /* 7750: invalid message */
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#define STOP_CHBKPT 19 /* channel breakpoint */
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/* Simulator error codes */
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#define ERR_STALL 40 /* stall */
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#define ERR_ENDRC 41 /* end rec */
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#define ERR_NRCF 42 /* no record found */
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/* Instruction history - flags in left half of pc entry */
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#define HIST_PC 0x04000000 /* CPU */
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#define HIST_V_CH 28 /* chan + 1 */
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#define HIST_M_CH 0xF
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#define HIST_CH(x) (((x) >> HIST_V_CH) & HIST_M_CH)
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typedef struct {
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uint32 pc;
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uint32 ea;
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uint32 rpt;
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t_uint64 ir;
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t_uint64 ac;
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t_uint64 mq;
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t_uint64 si;
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t_uint64 opnd;
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} InstHistory;
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/* Architectural constants */
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#define A704_SIZE 14 /* addr width, 704 mode */
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#define ASIZE 15 /* inst addr width */
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#define PASIZE 16 /* phys addr width */
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#define STDMEMSIZE (1u << ASIZE) /* standard memory */
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#define MAXMEMSIZE (1u << PASIZE) /* maximum memory */
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#define A704_MASK ((1u << A704_SIZE) - 1)
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#define PAMASK ((1u << PASIZE) - 1)
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#define MEMSIZE (cpu_unit.capac)
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#define BCORE_V (ASIZE) /* (CTSS) A/B core sel */
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#define BCORE_BASE (1u << BCORE_V) /* (CTSS) B core base */
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/* Traps */
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#define TRAP_STD_SAV 000000 /* trap save location */
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#define TRAP_TRA_PC 000001 /* trap PC: transfer */
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#define TRAP_STR_PC 000002 /* trap PC: STR */
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#define TRAP_FP_PC 000010 /* trap PC: flt point */
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#define TRAP_PROT_SAV 000032 /* protection trap save */
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#define TRAP_PROT_PC 000033 /* protection trap PC */
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#define TRAP_704_SAV 040000 /* 704 compat trap */
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#define TRAP_SEL_PC 040001 /* 704 trap PC: select */
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#define TRAP_CPY_PC 040002 /* 704 trap PC: copy */
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#define TRAP_F_MQ 000001 /* MQ error */
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#define TRAP_F_AC 000002 /* AC error */
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#define TRAP_F_OVF 000004 /* overflow */
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#define TRAP_F_SGL 000010 /* single precision */
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#define TRAP_F_DVC 000020 /* fake: divide check */
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#define TRAP_F_ODD 000040 /* odd address */
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#define TRAP_F_BDATA 020000 /* (CTSS) data B core */
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#define TRAP_F_BINST 040000 /* (CTSS) inst B core */
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/* Integer */
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#define DMASK INT64_C(0777777777777) /* data mask */
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#define SIGN INT64_C(0400000000000) /* sign */
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#define MMASK INT64_C(0377777777777) /* magnitude mask */
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#define LMASK INT64_C(0777777000000) /* left mask */
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#define RMASK INT64_C(0000000777777) /* right mask */
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#define PMASK INT64_C(0700000000000) /* prefix */
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#define XMASK INT64_C(0077777000000) /* decrement */
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#define TMASK INT64_C(0000000700000) /* tag */
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#define AMASK INT64_C(0000000077777) /* address */
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#define SCMASK INT64_C(0000000000377) /* shift count mask */
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#define B1 INT64_C(0200000000000) /* bit 1 */
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#define B9 INT64_C(0000400000000) /* bit 9 */
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/* Accumulator is actually 38b wide */
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#define AC_S INT64_C(02000000000000) /* sign */
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#define AC_Q INT64_C(01000000000000) /* Q */
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#define AC_P INT64_C(00400000000000) /* P */
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#define AC_MMASK INT64_C(01777777777777) /* Q+P+magnitude */
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/* Floating point */
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#define FP_N_FR 27 /* fraction bits */
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#define FP_FMASK ((1u << FP_N_FR) - 1)
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#define FP_N_DFR 54 /* double fraction bits */
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#define FP_DFMASK ((((t_uint64) 1) << FP_N_DFR) - 1)
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#define FP_FNORM (((t_uint64) 1u) << (FP_N_DFR - 1)) /* normalized bit */
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#define FP_FCRY (((t_uint64) 1u) << FP_N_DFR) /* fraction carry */
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#define FP_BIAS 0200 /* exponent bias */
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#define FP_V_CH (FP_N_FR) /* exponent */
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#define FP_M_CH 0377 /* SR char mask */
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#define FP_M_ACCH 01777 /* AC char mask incl Q,P */
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/* Instruction format */
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#define INST_T_DEC INT64_C(0300000000000) /* if nz, takes decr */
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#define INST_T_CXR1 INT64_C(0000000100000) /* if nz, update XR1 */
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#define INST_V_OPD 33 /* decrement opcode */
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#define INST_M_OPD 07
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#define INST_V_DEC 18 /* decrement */
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#define INST_M_DEC 077777
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#define INST_V_OPC 24 /* normal opcode */
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#define INST_M_OPC 0777
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#define INST_V_IND 22 /* indirect */
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#define INST_IND (3 << INST_V_IND)
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#define INST_V_CCNT 18 /* convert count */
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#define INST_M_CCNT 0377
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#define INST_V_VCNT 18 /* vlm/vdh count */
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#define INST_M_VCNT 077
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#define INST_V_TAG 15 /* index */
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#define INST_M_TAG 07
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#define INST_V_ADDR 0
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#define INST_M_ADDR 077777
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#define INST_V_4B 0
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#define INST_M_4B 017
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#define GET_OPD(x) ((uint32) (((x) >> INST_V_OPD) & INST_M_OPD))
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#define GET_DEC(x) ((uint32) (((x) >> INST_V_DEC) & INST_M_DEC))
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#define GET_OPC(x) (((uint32) (((x) >> INST_V_OPC) & INST_M_OPC)) | \
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(((x) & SIGN)? 01000: 0))
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#define TST_IND(x) (((x) & INST_IND) == INST_IND)
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#define GET_CCNT(x) ((uint32) (((x) >> INST_V_CCNT) & INST_M_CCNT))
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#define GET_VCNT(x) ((uint32) (((x) >> INST_V_VCNT) & INST_M_VCNT))
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#define GET_TAG(x) ((uint32) (((x) >> INST_V_TAG) & INST_M_TAG))
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/* Instruction decode flags */
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#define I_4X 0x01 /* 7040, 7044 */
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#define I_9X 0x02 /* 7090, 7094, CTSS */
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#define I_94 0x04 /* 7094, CTSS */
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#define I_CT 0x08 /* CTSS */
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#define I_MODEL 0x0F /* option mask */
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#define I_X 0x10 /* indexed */
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#define I_N 0x20 /* indirect */
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#define I_R 0x40 /* read */
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#define I_D 0x80 /* double read */
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#define I_XN (I_X|I_N)
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#define I_XNR (I_X|I_N|I_R)
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#define I_XND (I_X|I_N|I_D)
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/* Memory protection (CTSS) */
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#define VA_V_OFF 0 /* offset in block */
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#define VA_N_OFF 8 /* width of offset */
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#define VA_M_OFF ((1u << VA_N_OFF) - 1)
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#define VA_OFF (VA_M_OFF << VA_V_OFF)
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#define VA_V_BLK (VA_N_OFF) /* block */
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#define VA_N_BLK (ASIZE - VA_N_OFF) /* width of block */
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#define VA_M_BLK ((1u << VA_N_BLK) - 1)
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#define VA_BLK (VA_M_BLK << VA_V_BLK)
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/* Unsigned operations */
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#define NEG(x) (~(x) + 1)
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#define BIT_TST(w,b) (((w) >> (b)) & 1)
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/* Device information block */
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typedef struct {
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t_stat (*chsel)(uint32 ch, uint32 sel, uint32 u);
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t_stat (*write)(uint32 ch, t_uint64 val, uint32 flags);
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} DIB;
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/* BCD digits */
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#define BCD_MASK 017
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#define BCD_ZERO 012
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#define BCD_ONE 001
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#define BCD_TWO 002
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#define BCD_AT 014
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/* Channels */
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#define NUM_CHAN 8 /* # channels */
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#define CH_A 0 /* channel A */
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#define CH_B 1
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#define CH_C 2
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#define CH_D 3
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#define CH_E 4
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#define CH_F 5
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#define CH_G 6
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#define CH_H 7
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#define REQ_CH(x) (1u << (x))
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/* All channel commands */
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#define CHI_IND 0000000400000 /* ch inst indirect */
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/* Channel selects - all channels */
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#define CHSL_RDS 0001 /* data selects */
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#define CHSL_WRS 0002
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#define CHSL_SNS 0003
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#define CHSL_CTL 0004
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#define CHSL_FMT 0005
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#define CHSL_WEF 0010 /* non-data selects */
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#define CHSL_WBT 0011 /* 704X only */
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#define CHSL_BSR 0012
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#define CHSL_BSF 0013
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#define CHSL_REW 0014
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#define CHSL_RUN 0015
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#define CHSL_SDN 0016
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#define CHSL_2ND 0020 /* second state */
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#define CHSL_3RD 0040 /* etc */
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#define CHSL_4TH 0060
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#define CHSL_5TH 0100
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#define CHSL_NDS 0010 /* non-data sel flag */
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#define CHSL_NUM 16
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/* Channel commands - 7607/7289 - S12'19 */
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#define CH6I_NST 0000000200000 /* ch inst no store */
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#define CH6_IOCD 000
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#define CH6_TCH 002
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#define CH6_IORP 004
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#define CH6_IORT 006
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#define CH6_IOCP 010
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#define CH6_IOCT 012
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#define CH6_IOSP 014
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#define CH6_IOST 016
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#define CH6_OPMASK 016 /* without nostore */
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#define TCH_LIMIT 5 /* TCH autoresolve limit */
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/* Channel data flags - 7607 */
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#define CH6DF_EOR 1 /* end of record */
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#define CH6DF_VLD 2 /* input valid */
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/* Channel commands - 7909 - S123'19 */
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#define CH9_WTR 000
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#define CH9_XMT 001
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#define CH9_TCH 004
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#define CH9_LIPT 005
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#define CH9_CTL 010
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#define CH9_CTLR 011
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#define CH9_CTLW 012
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#define CH9_SNS 013
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#define CH9_LAR 014
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#define CH9_SAR 015
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#define CH9_TWT 016
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#define CH9_CPYP 020
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#define CH9_CPYD 024
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#define CH9_TCM 025
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#define CH9_LIP 031
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#define CH9_TDC 032
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#define CH9_LCC 033
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#define CH9_SMS 034
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#define CH9_ICC 035
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#define CH9_ICCA 037 /* ignores bit <3> */
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#define CH9_OPMASK 037
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/* Channel data flags - 7909 */
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#define CH9DF_STOP 1 /* stop */
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#define CH9DF_VLD 2 /* input valid */
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/* Extended parts of the command come from the decrement, stored in ch_wc */
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#define CH9D_V_MASK 0 /* condition mask */
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#define CH9D_M_MASK 077
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#define CH9D_V_COND 12 /* condition select */
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#define CH9D_M_COND 07
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#define CH9D_MASK(x) (((x) >> CH9D_V_MASK) & CH9D_M_MASK)
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#define CH9D_COND(x) (((x) >> CH9D_V_COND) & CH9D_M_COND)
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#define CH9D_NST 020000 /* no store */
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#define CH9D_B11 000100
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/* Or from the effective address, stored in ch_ca */
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#define CH9A_V_LCC 0 /* counter */
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#define CH9A_M_LCC 077
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#define CH9A_V_SMS 0 /* system mask */
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#define CH9A_M_SMS 0177
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#define CH9A_LCC(x) (((x) >> CH9A_V_LCC) & CH9A_M_LCC)
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#define CH9A_SMS(x) (((x) >> CH9A_V_SMS) & CH9A_M_SMS)
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/* Channel states - common */
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#define CHXS_IDLE 0 /* idle */
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#define CHXS_DSX 1 /* executing */
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/* Channel states - 7607/7289 */
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#define CH6S_PNDS 2 /* polling NDS */
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#define CH6S_PDS 3 /* polling DS */
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#define CH6S_NDS 4 /* nds, executing */
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#define CH6S_DSW 5 /* ds, chan wait */
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/* Channel traps - 7909 has only CMD (== TWT) */
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#define CHTR_V_CME 0 /* cmd/eof enable */
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#define CHTR_V_CLK 17 /* clock */
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#define CHTR_V_TRC 18 /* tape check */
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#define CHTR_V_TWT (CHTR_V_CME)
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#define CHTR_CLK_SAV 006 /* clock */
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#define CHTR_CHA_SAV 012 /* start of chan block */
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#define CHTR_F_CMD 1 /* CMD flag (in decr) */
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#define CHTR_F_TRC 2 /* TRC flag (in decr) */
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#define CHTR_F_EOF 4 /* EOF flag (in decr) */
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/* Channel interrupts - 7909 only */
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#define CHINT_CHA_SAV 042 /* start of chan block */
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/* Channel interrupt conditions - 7909 only */
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#define CHINT_ADPC 001 /* adapter check */
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#define CHINT_ATN2 002 /* attention 2 - ni */
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#define CHINT_ATN1 004 /* attention 1 */
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#define CHINT_UEND 010 /* unusual end */
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#define CHINT_SEQC 020 /* sequence check */
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#define CHINT_IOC 040 /* IO check */
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/* Channel SMS flags - 7909 only */
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#define CHSMS_SEL2 0001 /* select 2nd - ni */
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#define CHSMS_IATN2 0002 /* inhibit atn2 - ni */
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#define CHSMS_IATN1 0004 /* inhibit atn1 */
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#define CHSMS_IUEND 0010 /* inhibit uend */
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#define CHSMS_BCD 0020 /* BCD conversion - ni */
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#define CHSMS_RBCK 0040 /* read backwards - ni */
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#define CHSMS_ENCI 0100 /* enable noncon - ni */
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/* Channel flags (7607 in right half, 7909 in left half) */
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#define CHF_CMD 00000000001 /* cmd done */
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#define CHF_TWT (CHF_CMD)
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#define CHF_TRC 00000000002 /* tape check */
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#define CHF_EOF 00000000004 /* end of file */
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#define CHF_BOT 00000000010 /* beginning of tape */
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#define CHF_EOT 00000000020 /* end of tape */
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#define CHF_LDW 00000000040 /* LCH waiting */
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#define CHF_EOR 00000000100 /* end of record */
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#define CHF_IRQ 00001000000 /* intr request */
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#define CHF_INT 00002000000 /* intr in prog */
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#define CHF_WRS 00004000000 /* write */
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#define CHF_RDS 00010000000 /* read */
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#define CHF_PWR 00020000000 /* prepare to write */
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#define CHF_PRD 00040000000 /* prepare to read */
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#define CHF_V_COND 24 /* cond register */
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#define CHF_M_COND 077
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#define CHF_ADPC (CHINT_ADPC << CHF_V_COND) /* adapter check */
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#define CHF_ATN2 (CHINT_ATN2 << CHF_V_COND) /* attention 2 */
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#define CHF_ATN1 (CHINT_ATN1 << CHF_V_COND) /* attention 1 */
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#define CHF_UEND (CHINT_UEND << CHF_V_COND) /* unusual end */
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#define CHF_SEQC (CHINT_SEQC << CHF_V_COND) /* sequence check */
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#define CHF_IOC (CHINT_IOC << CHF_V_COND) /* IO check */
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#define CHF_V_LCC 30 /* loop ctrl counter */
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#define CHF_M_LCC 077
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#define CHF_CLR_7909 INT64_C(07775000177) /* 7909 clear flags */
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#define CHF_SDC_7909 INT64_C(07777600000) /* 7909 SDC flags */
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/* Channel characteristics (in dev.flags) */
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#define DEV_7909 (1u << (DEV_V_UF + 0))
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#define DEV_7289 (1u << (DEV_V_UF + 1))
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#define DEV_CDLP (1u << (DEV_V_UF + 2))
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#define DEV_7750 (1u << (DEV_V_UF + 3))
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#define DEV_7631 (1u << (DEV_V_UF + 4))
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/* Unit addresses - 7607/7289 only */
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#define U_V_CH 9 /* channel number */
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#define U_M_CH 077
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#define U_V_UNIT 0
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#define U_M_UNIT 0777
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#define GET_U_CH(x) (((((uint32) (x)) >> U_V_CH) & U_M_CH) - 1)
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#define GET_U_UNIT(x) ((((uint32) (x)) >> U_V_UNIT) & U_M_UNIT)
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#define U_MTBCD 0201 /* BCD tape */
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#define U_MTBIN 0221 /* binary tape */
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#define U_CDR 0321 /* card reader */
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#define U_CDP 0341 /* card punch */
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#define U_LPBCD 0361 /* BCD print */
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#define U_LPBIN 0362 /* binary print */
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#define U_DRM 0330 /* 7320A drum */
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#define MT_NUMDR 10
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/* CTSS Chronolog clock */
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#define CHRONO_CH (CH_A) /* channel A */
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#define CHRONO_UNIT (7) /* unit 7 */
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/* Interval timer */
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#define CLK_CTR 05 /* counter */
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#define CLK_TPS 60 /* 60Hz */
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#define TMR_CLK 0 /* use timer 0 */
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#define TMR_COM 1 /* 7750 timer */
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/* Function prototypes and macros */
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#define ReadP(p) M[p]
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#define WriteP(p,d) M[p] = d
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void cpu_ent_hist (uint32 pc, uint32 ea, t_uint64 ir, t_uint64 opnd);
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t_stat ch_show_chan (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat ch6_end_nds (uint32 ch);
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uint32 ch6_set_flags (uint32 ch, uint32 unit, uint32 flags);
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t_stat ch6_err_disc (uint32 ch, uint32 unit, uint32 flags);
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t_stat ch6_req_rd (uint32 ch, uint32 unit, t_uint64 val, uint32 flags);
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t_stat ch6_req_wr (uint32 ch, uint32 unit);
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t_bool ch6_qconn (uint32 ch, uint32 unit);
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t_stat ch9_req_rd (uint32 ch, t_uint64 val);
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void ch9_set_atn (uint32 ch);
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void ch9_set_ioc (uint32 ch);
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void ch9_set_end (uint32 ch, uint32 ireq);
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t_bool ch9_qconn (uint32 ch);
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void ch_set_map (void);
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t_bool ch_qidle (void);
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extern const uint32 col_masks[12];
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extern const t_uint64 bit_masks[36];
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extern const char nine_to_ascii_a[64];
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extern const char nine_to_ascii_h[64];
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extern const char ascii_to_nine[128];
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extern const char ascii_to_bcd[128];
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extern const char bcd_to_ascii_a[64];
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extern const char bcd_to_ascii_h[64];
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extern const char bcd_to_pca[64];
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extern const char bcd_to_pch[64];
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extern const uint32 bcd_to_colbin[64];
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extern uint32 PC;
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extern uint32 ind_ioc;
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#endif
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