5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
430 lines
20 KiB
C
430 lines
20 KiB
C
/* sds_defs.h: SDS 940 simulator definitions
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Copyright (c) 2001-2010, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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22-May-10 RMS Added check for 64b definitions
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25-Apr-03 RMS Revised for extended file support
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*/
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#ifndef SDS_DEFS_H_
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#define SDS_DEFS_H_ 0
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#include "sim_defs.h" /* simulator defns */
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#if defined(USE_INT64) || defined(USE_ADDR64)
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#error "SDS 940 does not support 64b values!"
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#endif
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/* Simulator stop codes */
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#define STOP_IONRDY 1 /* I/O dev not ready */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_INVDEV 4 /* invalid dev */
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#define STOP_INVINS 5 /* invalid instr */
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#define STOP_INVIOP 6 /* invalid I/O op */
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#define STOP_INDLIM 7 /* indirect limit */
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#define STOP_EXULIM 8 /* EXU limit */
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#define STOP_MMINT 9 /* mm in intr */
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#define STOP_MMTRP 10 /* mm in trap */
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#define STOP_TRPINS 11 /* trap inst not BRM or BRU */
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#define STOP_RTCINS 12 /* rtc inst not MIN or SKR */
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#define STOP_ILLVEC 13 /* zero vector */
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#define STOP_CCT 14 /* runaway CCT */
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#define STOP_MBKPT 15 /* monitor-mode breakpoint */
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#define STOP_NBKPT 16 /* normal-mode breakpoint */
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#define STOP_UBKPT 17 /* user-mode breakpoint */
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#define STOP_DBKPT 18 /* step-over (dynamic) breakpoint */
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/* Trap codes */
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#define MM_PRVINS -040 /* privileged */
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#define MM_NOACC -041 /* no access */
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#define MM_WRITE -043 /* write protect */
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#define MM_MONUSR -044 /* mon to user */
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/* Conditional error returns */
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#define CRETINS return ((stop_invins)? STOP_INVINS: SCPE_OK)
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#define CRETDEV return ((stop_invdev)? STOP_INVDEV: SCPE_OK)
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#define CRETIOP return ((stop_inviop)? STOP_INVIOP: SCPE_OK)
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#define CRETIOE(f,c) return ((f)? c: SCPE_OK)
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/* Architectural constants */
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#define SIGN 040000000 /* sign */
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#define DMASK 077777777 /* data mask */
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#define EXPS 0400 /* exp sign */
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#define EXPMASK 0777 /* exp mask */
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#define SXT(x) ((int32) (((x) & SIGN)? ((x) | ~DMASK): \
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((x) & DMASK)))
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#define SXT_EXP(x) ((int32) (((x) & EXPS)? ((x) | ~EXPMASK): \
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((x) & EXPMASK)))
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/* CPU modes */
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#define NML_MODE 0
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#define MON_MODE 1
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#define USR_MODE 2
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#define BAD_MODE 3
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/* Memory */
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#define MAXMEMSIZE (1 << 16) /* max memory size */
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#define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
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#define ReadP(x) M[x]
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#define WriteP(x,y) if (MEM_ADDR_OK (x)) M[x] = y
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/* Virtual addressing */
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#define VA_SIZE (1 << 14) /* virtual addr size */
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#define VA_MASK (VA_SIZE - 1) /* virtual addr mask */
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#define VA_V_PN 11 /* page number */
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#define VA_M_PN 07
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#define VA_GETPN(x) (((x) >> VA_V_PN) & VA_M_PN)
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#define VA_POFF ((1 << VA_V_PN) - 1) /* offset */
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#define VA_USR (I_USR) /* user flag in addr */
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#define XVA_MASK (VA_USR | VA_MASK)
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/* Arithmetic */
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#define TSTS(x) ((x) & SIGN)
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#define NEG(x) (-((int32) (x)) & DMASK)
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#define ABS(x) (TSTS (x)? NEG(x): (x))
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/* Memory map */
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#define MAP_PROT (040 << VA_V_PN) /* protected */
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#define MAP_PAGE (037 << VA_V_PN) /* phys page number */
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/* Instruction format */
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#define I_USR (1 << 23) /* user */
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#define I_IDX (1 << 22) /* indexed */
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#define I_POP (1 << 21) /* programmed op */
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#define I_V_TAG 21 /* tag */
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#define I_V_OP 15 /* opcode */
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#define I_M_OP 077
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#define I_GETOP(x) (((x) >> I_V_OP) & I_M_OP)
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#define I_IND (1 << 14) /* indirect */
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#define I_V_SHFOP 11 /* shift op */
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#define I_M_SHFOP 07
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#define I_GETSHFOP(x) (((x) >> I_V_SHFOP) & I_M_SHFOP)
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#define I_SHFMSK 0777 /* shift count */
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#define I_V_IOMD 12 /* IO inst mode */
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#define I_M_IOMD 03
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#define I_GETIOMD(x) (((x) >> I_V_IOMD) & I_M_IOMD)
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#define I_V_SKCND 7 /* SKS skip cond */
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#define I_M_SKCND 037
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#define I_GETSKCND(x) (((x) >> I_V_SKCND) & I_M_SKCND)
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#define I_EOB2 000400000 /* chan# bit 2 */
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#define I_SKB2 000040000 /* skschan# bit 2 */
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#define I_EOB1 020000000 /* chan# bit 1 */
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#define I_EOB0 000000100 /* chan# bit 0 */
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#define I_GETEOCH(x) ((((x) & I_EOB2)? 4: 0) | \
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(((x) & I_EOB1)? 2: 0) | \
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(((x) & I_EOB0)? 1: 0))
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#define I_SETEOCH(x) ((((x) & 4)? I_EOB2: 0) | \
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(((x) & 2)? I_EOB1: 0) | \
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(((x) & 1)? I_EOB0: 0))
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#define I_GETSKCH(x) ((((x) & I_SKB2)? 4: 0) | \
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(((x) & I_EOB1)? 2: 0) | \
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(((x) & I_EOB0)? 1: 0))
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#define I_SETSKCH(x) ((((x) & 4)? I_SKB2: 0) | \
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(((x) & 2)? I_EOB1: 0) | \
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(((x) & 1)? I_EOB0: 0))
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/* Globally visible flags */
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#define UNIT_V_GENIE (UNIT_V_UF + 0)
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#define UNIT_GENIE (1 << UNIT_V_GENIE)
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/* Timers */
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#define TMR_RTC 0 /* clock */
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#define TMR_MUX 1 /* mux */
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/* I/O routine functions */
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#define IO_CONN 0 /* connect */
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#define IO_EOM1 1 /* EOM mode 1 */
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#define IO_DISC 2 /* disconnect */
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#define IO_READ 3 /* read */
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#define IO_WRITE 4 /* write */
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#define IO_WREOR 5 /* write eor */
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#define IO_SKS 6 /* skip signal */
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/* Dispatch template */
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struct sdsdspt {
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uint32 num; /* # entries */
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uint32 off; /* offset from base */
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};
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typedef struct sdsdspt DSPT;
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/* Device information block */
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struct sdsdib {
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int32 chan; /* channel */
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int32 dev; /* base dev no */
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int32 xfr; /* xfer flag */
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DSPT *tplt; /* dispatch templates */
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t_stat (*iop) (uint32 fnc, uint32 dev, uint32 *dat);
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};
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typedef struct sdsdib DIB;
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/* Channels */
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#define NUM_CHAN 8 /* max num chan */
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#define CHAN_W 0 /* TMCC */
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#define CHAN_Y 1
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#define CHAN_C 2
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#define CHAN_D 3
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#define CHAN_E 4 /* DACC */
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#define CHAN_F 5
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#define CHAN_G 6
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#define CHAN_H 7
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/* I/O control EOM */
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#define CHC_REV 04000 /* reverse */
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#define CHC_NLDR 02000 /* no leader */
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#define CHC_BIN 01000 /* binary */
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#define CHC_V_CPW 7 /* char/word */
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#define CHC_M_CPW 03
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#define CHC_GETCPW(x) (((x) >> CHC_V_CPW) & CHC_M_CPW)
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/* Buffer control (extended) EOM */
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#define CHM_CE 04000 /* compat/ext */
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#define CHM_ER 02000 /* end rec int */
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#define CHM_ZC 01000 /* zero wc int */
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#define CHM_V_FNC 7 /* term func */
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#define CHM_M_FNC 03
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#define CHM_GETFNC(x) (((x) & CHM_CE)? (((x) >> CHM_V_FNC) & CHM_M_FNC): CHM_COMP)
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#define CHM_IORD 0 /* record, disc */
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#define CHM_IOSD 1 /* signal, disc */
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#define CHM_IORP 2 /* record, proc */
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#define CHM_IOSP 3 /* signal, proc */
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#define CHM_COMP 5 /* compatible */
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#define CHM_SGNL 1 /* signal bit */
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#define CHM_PROC 2 /* proceed bit */
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#define CHM_V_HMA 5 /* hi mem addr */
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#define CHM_M_HMA 03
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#define CHM_GETHMA(x) (((x) >> CHM_V_HMA) & CHM_M_HMA)
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#define CHM_V_HWC 0 /* hi word count */
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#define CHM_M_HWC 037
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#define CHM_GETHWC(x) (((x) >> CHM_V_HWC) & CHM_M_HWC)
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/* Channel flags word */
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#define CHF_ERR 00001 /* error */
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#define CHF_IREC 00002 /* interrecord */
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#define CHF_ILCE 00004 /* interlace */
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#define CHF_DCHN 00010 /* data chain */
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#define CHF_EOR 00020 /* end of record */
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#define CHF_12B 00040 /* 12 bit mode */
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#define CHF_24B 00100 /* 24 bit mode */
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#define CHF_OWAK 00200 /* output wake */
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#define CHF_SCAN 00400 /* scan */
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#define CHF_TOP 01000 /* TOP pending */
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#define CHF_N_FLG 9 /* <= 16 */
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/* Interrupts and vectors (0 is reserved), highest bit is highest priority */
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#define INT_V_PWRO 31 /* power on */
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#define INT_V_PWRF 30 /* power off */
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#define INT_V_CPAR 29 /* CPU parity err */
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#define INT_V_IPAR 28 /* IO parity err */
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#define INT_V_RTCS 27 /* clock sync */
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#define INT_V_RTCP 26 /* clock pulse */
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#define INT_V_YZWC 25 /* chan Y zero wc */
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#define INT_V_WZWC 24 /* chan W zero wc */
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#define INT_V_YEOR 23 /* chan Y end rec */
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#define INT_V_WEOR 22 /* chan W end rec */
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#define INT_V_CZWC 21 /* chan C */
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#define INT_V_CEOR 20
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#define INT_V_DZWC 19 /* chan D */
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#define INT_V_DEOR 18
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#define INT_V_EZWC 17 /* chan E */
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#define INT_V_EEOR 16
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#define INT_V_FZWC 15 /* chan F */
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#define INT_V_FEOR 14
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#define INT_V_GZWC 13 /* chan G */
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#define INT_V_GEOR 12
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#define INT_V_HZWC 11 /* chan H */
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#define INT_V_HEOR 10
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#define INT_V_MUXR 9 /* mux receive */
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#define INT_V_MUXT 8 /* mux transmit */
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#define INT_V_MUXCO 7 /* SDS carrier on */
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#define INT_V_MUXCF 6 /* SDS carrier off */
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#define INT_V_DRM 5 /* Genie drum */
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#define INT_V_FORK 4 /* fork */
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#define INT_PWRO (1 << INT_V_PWRO)
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#define INT_PWRF (1 << INT_V_PWRF)
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#define INT_CPAR (1 << INT_V_CPAR)
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#define INT_IPAR (1 << INT_V_IPAR)
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#define INT_RTCS (1 << INT_V_RTCS)
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#define INT_RTCP (1 << INT_V_RTCP)
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#define INT_YZWC (1 << INT_V_YZWC)
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#define INT_WZWC (1 << INT_V_WZWC)
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#define INT_YEOR (1 << INT_V_YEOR)
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#define INT_WEOR (1 << INT_V_WEOR)
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#define INT_CZWC (1 << INT_V_CZWC)
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#define INT_CEOR (1 << INT_V_CEOR)
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#define INT_DZWC (1 << INT_V_DZWC)
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#define INT_DEOR (1 << INT_V_DEOR)
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#define INT_EZWC (1 << INT_V_EZWC)
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#define INT_EEOR (1 << INT_V_EEOR)
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#define INT_FZWC (1 << INT_V_FZWC)
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#define INT_FEOR (1 << INT_V_FEOR)
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#define INT_GZWC (1 << INT_V_GZWC)
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#define INT_GEOR (1 << INT_V_GEOR)
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#define INT_HZWC (1 << INT_V_HZWC)
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#define INT_HEOR (1 << INT_V_HEOR)
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#define INT_MUXR (1 << INT_V_MUXR)
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#define INT_MUXT (1 << INT_V_MUXT)
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#define INT_MUXCO (1 << INT_V_MUXCO)
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#define INT_MUXCF (1 << INT_V_MUXCF)
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#define INT_DRM (1 << INT_V_DRM)
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#define INT_FORK (1 << INT_V_FORK)
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#define VEC_PWRO 0036
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#define VEC_PWRF 0037
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#define VEC_CPAR 0056
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#define VEC_IPAR 0057
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#define VEC_RTCS 0074
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#define VEC_RTCP 0075
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#define VEC_YZWC 0030
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#define VEC_WZWC 0031
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#define VEC_YEOR 0032
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#define VEC_WEOR 0033
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#define VEC_CZWC 0060
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#define VEC_CEOR 0061
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#define VEC_DZWC 0062
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#define VEC_DEOR 0063
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#define VEC_EZWC 0064
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#define VEC_EEOR 0065
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#define VEC_FZWC 0066
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#define VEC_FEOR 0067
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#define VEC_GZWC 0070
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#define VEC_GEOR 0071
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#define VEC_HZWC 0072
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#define VEC_HEOR 0073
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#define VEC_MUXR 0200 /* term mux rcv */
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#define VEC_MUXT 0201 /* term mux xmt */
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#define VEC_MUXCO 0202 /* SDS: mux carrier on */
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#define VEC_MUXCF 0203 /* SDS: mux carrier off */
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#define VEC_DRM 0202 /* Genie: drum */
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#define VEC_FORK 0216 /* "fork" */
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/* Device constants */
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#define DEV_MASK 077 /* device mask */
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#define DEV_TTI 001 /* teletype */
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#define DEV_PTR 004 /* paper tape rdr */
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#define DEV_MT 010 /* magtape */
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#define DEV_RAD 026 /* fixed head disk */
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#define DEV_DSK 026 /* moving head disk */
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#define DEV_TTO 041 /* teletype */
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#define DEV_PTP 044 /* paper tape punch */
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#define DEV_LPT 060 /* line printer */
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#define DEV_MTS 020 /* MT scan/erase */
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#define DEV_OUT 040 /* output flag */
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#define DEV3_GDRM 004 /* Genie drum */
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#define DEV3_GMUX 001 /* Genie mux */
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#define DEV3_SMUX (DEV_MASK) /* standard mux */
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#define LPT_WIDTH 132 /* line print width */
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#define CCT_LNT 132 /* car ctrl length */
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/* Transfer request flags for devices (0 is reserved) */
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#define XFR_V_TTI 1 /* console */
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#define XFR_V_TTO 2
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#define XFR_V_PTR 3 /* paper tape */
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#define XFR_V_PTP 4
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#define XFR_V_LPT 5 /* line printer */
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#define XFR_V_RAD 6 /* fixed hd disk */
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#define XFR_V_DSK 7 /* mving hd disk */
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#define XFR_V_MT0 8 /* magtape */
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#define XFR_TTI (1 << XFR_V_TTI)
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#define XFR_TTO (1 << XFR_V_TTO)
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#define XFR_PTR (1 << XFR_V_PTR)
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#define XFR_PTP (1 << XFR_V_PTP)
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#define XFR_LPT (1 << XFR_V_LPT)
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#define XFR_RAD (1 << XFR_V_RAD)
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#define XFR_DSK (1 << XFR_V_DSK)
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#define XFR_MT0 (1 << XFR_V_MT0)
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/* PIN/POT ordinals (0 is reserved) */
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#define POT_ILCY 1 /* interlace */
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#define POT_DCRY (POT_ILCY + NUM_CHAN) /* data chain */
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#define POT_ADRY (POT_DCRY + NUM_CHAN) /* address reg */
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#define POT_RL1 (POT_ADRY + NUM_CHAN) /* RL1 */
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#define POT_RL2 (POT_RL1 + 1) /* RL2 */
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#define POT_RL4 (POT_RL2 + 1) /* RL4 */
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#define POT_RADS (POT_RL4 + 1) /* fhd sector */
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#define POT_RADA (POT_RADS + 1) /* fhd addr */
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#define POT_DSK (POT_RADA + 1) /* mhd sec/addr */
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#define POT_SYSI (POT_DSK + 1) /* sys intr */
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#define POT_MUX (POT_SYSI + 1) /* multiplexor */
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/* Opcodes */
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enum opcodes {
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HLT, BRU, EOM, EOD = 006,
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MIY = 010, BRI, MIW, POT, ETR, MRG = 016, EOR,
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NOP, OVF = 022, EXU,
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YIM = 030, WIM = 032, PIN, STA = 035, STB, STX,
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SKS, BRX, BRM = 043, RCH = 046,
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SKE = 050, BRR, SKB, SKN, SUB, ADD, SUC, ADC,
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SKR, MIN, XMA, ADM, MUL, DIV, RSH, LSH,
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SKM, LDX, SKA, SKG, SKD, LDB, LDA, EAX
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};
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/* Channel function prototypes */
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void chan_set_flag (int32 ch, uint32 fl);
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void chan_set_ordy (int32 ch);
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void chan_disc (int32 ch);
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void chan_set_uar (int32 ch, uint32 dev);
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t_stat set_chan (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat show_chan (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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t_stat chan_process (void);
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t_bool chan_testact (void);
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/* Translation tables */
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extern const int8 odd_par[64];
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#endif
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