253f8a8dcf
Avoid redundant declarations in every simulator module that uses them and allow compiler to validate consistency of declarations and definitions.
309 lines
11 KiB
C
309 lines
11 KiB
C
/* vax_mmu.c - VAX memory management
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Copyright (c) 1998-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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29-Nov-13 RMS Reworked unaligned flows
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24-Oct-12 MB Added support for KA620 virtual addressing
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21-Jul-08 RMS Removed inlining support
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28-May-08 RMS Inlined physical memory routines
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29-Apr-07 RMS Added address masking for system page table reads
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22-Sep-05 RMS Fixed declarations (Sterling Garwood)
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30-Sep-04 RMS Comment and formating changes
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19-Sep-03 RMS Fixed upper/lower case linkage problems on VMS
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01-Jun-03 RMS Fixed compilation problem with USE_ADDR64
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This module contains the instruction simulators for
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Read - read virtual
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Write - write virtual
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ReadL(P) - read aligned physical longword (physical context)
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WriteL(P) - write aligned physical longword (physical context)
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ReadB(W) - read aligned physical byte (word)
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WriteB(W) - write aligned physical byte (word)
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Test - test acccess
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zap_tb - clear TB
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zap_tb_ent - clear TB entry
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chk_tb_ent - check TB entry
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set_map_reg - set up working map registers
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*/
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#include "vax_defs.h"
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#include "vax_mmu.h"
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#include <setjmp.h>
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int32 d_p0br, d_p0lr; /* dynamic copies */
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int32 d_p1br, d_p1lr; /* altered per ucode */
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int32 d_sbr, d_slr;
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TLBENT stlb[VA_TBSIZE], ptlb[VA_TBSIZE];
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static const int32 cvtacc[16] = { 0, 0,
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TLB_ACCW (KERN)+TLB_ACCR (KERN),
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TLB_ACCR (KERN),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCW (SUPV)+TLB_ACCW (USER)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCR (KERN)+TLB_ACCR (EXEC),
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TLB_ACCW (KERN)+TLB_ACCR (KERN)+TLB_ACCR (EXEC),
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TLB_ACCR (KERN)+TLB_ACCR (EXEC),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCW (SUPV)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCW (KERN)+TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+TLB_ACCW (SUPV)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCW (KERN)+TLB_ACCW (EXEC)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCW (KERN)+
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER),
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TLB_ACCR (KERN)+TLB_ACCR (EXEC)+TLB_ACCR (SUPV)+TLB_ACCR (USER)
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};
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t_stat tlb_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat tlb_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat tlb_reset (DEVICE *dptr);
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const char *tlb_description (DEVICE *dptr);
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TLBENT fill (uint32 va, int32 lnt, int32 acc, int32 *stat);
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extern int32 ReadIO (uint32 pa, int32 lnt);
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extern void WriteIO (uint32 pa, int32 val, int32 lnt);
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extern int32 ReadReg (uint32 pa, int32 lnt);
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extern void WriteReg (uint32 pa, int32 val, int32 lnt);
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int32 ReadU (uint32 pa, int32 lnt);
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void WriteU (uint32 pa, int32 val, int32 lnt);
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/* TLB data structures
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tlb_dev pager device descriptor
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tlb_unit pager units
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pager_reg pager register list
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*/
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UNIT tlb_unit[] = {
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{ UDATA (NULL, UNIT_FIX, VA_TBSIZE * 2) },
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{ UDATA (NULL, UNIT_FIX, VA_TBSIZE * 2) }
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};
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REG tlb_reg[] = {
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{ NULL }
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};
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DEVICE tlb_dev = {
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"TLB", tlb_unit, tlb_reg, NULL,
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2, 16, VA_N_TBI * 2, 1, 16, 32,
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&tlb_ex, &tlb_dep, &tlb_reset,
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NULL, NULL, NULL, NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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&tlb_description
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};
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/* TLB fill
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This routine fills the TLB after a tag or access mismatch, or
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on a write if pte<m> = 0. It fills the TLB and returns the
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pte to the caller. On an error, it aborts directly to the
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fault handler in the CPU.
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If called from map (VAX PROBEx), the error status is returned
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to the caller, and no fault occurs.
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*/
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#define MM_ERR(param) { \
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if (stat) { \
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*stat = param; \
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return zero_pte; \
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} \
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p1 = MM_PARAM (acc & TLB_WACC, param); \
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p2 = va; \
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ABORT ((param & PR_TNV)? ABORT_TNV: ABORT_ACV); }
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TLBENT fill (uint32 va, int32 lnt, int32 acc, int32 *stat)
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{
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int32 ptidx = (((uint32) va) >> 7) & ~03;
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int32 tlbpte, ptead, pte, tbi, vpn;
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static TLBENT zero_pte = { 0, 0 };
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if (va & VA_S0) { /* system space? */
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if (ptidx >= d_slr) /* system */
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MM_ERR (PR_LNV);
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ptead = (d_sbr + ptidx) & PAMASK;
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}
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else {
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if (va & VA_P1) { /* P1? */
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if (ptidx < d_p1lr)
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MM_ERR (PR_LNV);
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ptead = d_p1br + ptidx;
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}
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else { /* P0 */
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if (ptidx >= d_p0lr)
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MM_ERR (PR_LNV);
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ptead = d_p0br + ptidx;
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}
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#if !defined (VAX_620)
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if ((ptead & VA_S0) == 0)
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ABORT (STOP_PPTE); /* ppte must be sys */
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vpn = VA_GETVPN (ptead); /* get vpn, tbi */
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tbi = VA_GETTBI (vpn);
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if (stlb[tbi].tag != vpn) { /* in sys tlb? */
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ptidx = ((uint32) ptead) >> 7; /* xlate like sys */
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if (ptidx >= d_slr)
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MM_ERR (PR_PLNV);
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pte = ReadLP ((d_sbr + ptidx) & PAMASK); /* get system pte */
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#if defined (VAX_780)
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if ((pte & PTE_ACC) == 0) /* spte ACV? */
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MM_ERR (PR_PACV);
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#endif
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if ((pte & PTE_V) == 0) /* spte TNV? */
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MM_ERR (PR_PTNV);
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stlb[tbi].tag = vpn; /* set stlb tag */
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stlb[tbi].pte = cvtacc[PTE_GETACC (pte)] |
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((pte << VA_N_OFF) & TLB_PFN); /* set stlb data */
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}
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ptead = (stlb[tbi].pte & TLB_PFN) | VA_GETOFF (ptead);
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#endif
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}
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pte = ReadL (ptead); /* read pte */
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tlbpte = cvtacc[PTE_GETACC (pte)] | /* cvt access */
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((pte << VA_N_OFF) & TLB_PFN); /* set addr */
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if ((tlbpte & acc) == 0) /* chk access */
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MM_ERR (PR_ACV);
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if ((pte & PTE_V) == 0) /* check valid */
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MM_ERR (PR_TNV);
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if (acc & TLB_WACC) { /* write? */
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if ((pte & PTE_M) == 0)
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WriteL (ptead, pte | PTE_M);
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tlbpte = tlbpte | TLB_M; /* set M */
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}
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vpn = VA_GETVPN (va);
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tbi = VA_GETTBI (vpn);
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if ((va & VA_S0) == 0) { /* process space? */
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ptlb[tbi].tag = vpn; /* store tlb ent */
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ptlb[tbi].pte = tlbpte;
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return ptlb[tbi];
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}
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stlb[tbi].tag = vpn; /* system space */
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stlb[tbi].pte = tlbpte; /* store tlb ent */
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return stlb[tbi];
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}
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/* Utility routines */
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void set_map_reg (void)
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{
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d_p0br = P0BR & ~03;
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d_p1br = (P1BR - 0x800000) & ~03; /* VA<30> >> 7 */
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d_sbr = (SBR - 0x1000000) & ~03; /* VA<31> >> 7 */
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d_p0lr = (P0LR << 2);
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d_p1lr = (P1LR << 2) + 0x800000; /* VA<30> >> 7 */
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d_slr = (SLR << 2) + 0x1000000; /* VA<31> >> 7 */
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}
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/* Zap process (0) or whole (1) tb */
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void zap_tb (int stb)
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{
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size_t i;
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for (i = 0; i < VA_TBSIZE; i++) {
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ptlb[i].tag = ptlb[i].pte = -1;
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if (stb)
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stlb[i].tag = stlb[i].pte = -1;
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}
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}
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/* Zap single tb entry corresponding to va */
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void zap_tb_ent (uint32 va)
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{
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int32 tbi = VA_GETTBI (VA_GETVPN (va));
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if (va & VA_S0)
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stlb[tbi].tag = stlb[tbi].pte = -1;
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else ptlb[tbi].tag = ptlb[tbi].pte = -1;
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}
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/* Check for tlb entry corresponding to va */
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t_bool chk_tb_ent (uint32 va)
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{
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int32 vpn = VA_GETVPN (va);
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int32 tbi = VA_GETTBI (vpn);
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TLBENT xpte;
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xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi];
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if (xpte.tag == vpn)
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return TRUE;
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return FALSE;
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}
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/* TLB examine */
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t_stat tlb_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
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{
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int32 tlbn = uptr - tlb_unit;
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uint32 idx = (uint32) addr >> 1;
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if (idx >= VA_TBSIZE)
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return SCPE_NXM;
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if (addr & 1)
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*vptr = ((uint32) (tlbn? stlb[idx].pte: ptlb[idx].pte));
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else *vptr = ((uint32) (tlbn? stlb[idx].tag: ptlb[idx].tag));
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return SCPE_OK;
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}
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/* TLB deposit */
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t_stat tlb_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
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{
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int32 tlbn = uptr - tlb_unit;
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uint32 idx = (uint32) addr >> 1;
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if (idx >= VA_TBSIZE)
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return SCPE_NXM;
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if (addr & 1) {
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if (tlbn) stlb[idx].pte = (int32) val;
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else ptlb[idx].pte = (int32) val;
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}
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else {
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if (tlbn) stlb[idx].tag = (int32) val;
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else ptlb[idx].tag = (int32) val;
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}
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return SCPE_OK;
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}
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/* TLB reset */
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t_stat tlb_reset (DEVICE *dptr)
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{
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size_t i;
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for (i = 0; i < VA_TBSIZE; i++)
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stlb[i].tag = ptlb[i].tag = stlb[i].pte = ptlb[i].pte = -1;
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return SCPE_OK;
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}
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const char *tlb_description (DEVICE *dptr)
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{
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return "translation buffer";
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}
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