9c4779c061
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
315 lines
16 KiB
C
315 lines
16 KiB
C
/* hp2100_cpu1.h: HP 2100/1000 firmware dispatcher definitions
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Copyright (c) 2006-2008, J. David Bryan
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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11-Sep-08 JDB Moved microcode function prototypes here
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30-Apr-08 JDB Corrected OP_AFF to OP_AAFF for SIGNAL/1000
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Removed unused operand patterns
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23-Feb-08 HV Added more OP_* for SIGNAL/1000 and VIS
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28-Nov-07 JDB Added fprint_ops, fprint_regs for debug printouts
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19-Oct-07 JDB Revised OP_KKKAKK operand profile to OP_CCCACC for $LOC
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16-Oct-06 JDB Generalized operands for F-Series FP types
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26-Sep-06 JDB Split from hp2100_cpu1.c
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*/
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#ifndef _HP2100_CPU1_H_
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#define _HP2100_CPU1_H_
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/* Register print encoding */
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#define REG_COUNT 9 /* count of print flags */
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#define REG_CIR (1 << 0) /* print central interrupt register */
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#define REG_A (1 << 1) /* print A register */
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#define REG_B (1 << 2) /* print B register */
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#define REG_E (1 << 3) /* print E register */
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#define REG_X (1 << 4) /* print X register */
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#define REG_Y (1 << 5) /* print Y register */
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#define REG_O (1 << 6) /* print O register */
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#define REG_P (1 << 7) /* print P register */
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#define REG_P_REL (1 << 8) /* print P register as relative */
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/* Operand processing encoding */
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/* Base operand types. Note that all address encodings must be grouped together
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after OP_ADR.
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*/
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#define OP_NUL 0 /* no operand */
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#define OP_IAR 1 /* 1-word int in A reg */
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#define OP_JAB 2 /* 2-word int in A/B regs */
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#define OP_FAB 3 /* 2-word FP const in A/B regs */
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#define OP_CON 4 /* inline 1-word constant */
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#define OP_VAR 5 /* inline 1-word variable */
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#define OP_ADR 6 /* inline address */
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#define OP_ADK 7 /* addr of 1-word int const */
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#define OP_ADD 8 /* addr of 2-word int const */
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#define OP_ADF 9 /* addr of 2-word FP const */
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#define OP_ADX 10 /* addr of 3-word FP const */
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#define OP_ADT 11 /* addr of 4-word FP const */
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#define OP_ADE 12 /* addr of 5-word FP const */
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#define OP_N_FLAGS 4 /* number of bits needed for flags */
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#define OP_M_FLAGS ((1 << OP_N_FLAGS) - 1) /* mask for flag bits */
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#define OP_N_F (8 * sizeof (uint32) / OP_N_FLAGS) /* max number of op fields */
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#define OP_V_F1 (0 * OP_N_FLAGS) /* 1st operand field */
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#define OP_V_F2 (1 * OP_N_FLAGS) /* 2nd operand field */
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#define OP_V_F3 (2 * OP_N_FLAGS) /* 3rd operand field */
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#define OP_V_F4 (3 * OP_N_FLAGS) /* 4th operand field */
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#define OP_V_F5 (4 * OP_N_FLAGS) /* 5th operand field */
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#define OP_V_F6 (5 * OP_N_FLAGS) /* 6th operand field */
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#define OP_V_F7 (6 * OP_N_FLAGS) /* 7th operand field */
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#define OP_V_F8 (7 * OP_N_FLAGS) /* 8th operand field */
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/* Operand processing patterns */
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#define OP_N (OP_NUL << OP_V_F1)
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#define OP_I (OP_IAR << OP_V_F1)
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#define OP_J (OP_JAB << OP_V_F1)
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#define OP_R (OP_FAB << OP_V_F1)
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#define OP_C (OP_CON << OP_V_F1)
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#define OP_V (OP_VAR << OP_V_F1)
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#define OP_A (OP_ADR << OP_V_F1)
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#define OP_K (OP_ADK << OP_V_F1)
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#define OP_D (OP_ADD << OP_V_F1)
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#define OP_X (OP_ADX << OP_V_F1)
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#define OP_T (OP_ADT << OP_V_F1)
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#define OP_E (OP_ADE << OP_V_F1)
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#define OP_IA ((OP_IAR << OP_V_F1) | (OP_ADR << OP_V_F2))
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#define OP_JA ((OP_JAB << OP_V_F1) | (OP_ADR << OP_V_F2))
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#define OP_JD ((OP_JAB << OP_V_F1) | (OP_ADD << OP_V_F2))
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#define OP_RC ((OP_FAB << OP_V_F1) | (OP_CON << OP_V_F2))
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#define OP_RK ((OP_FAB << OP_V_F1) | (OP_ADK << OP_V_F2))
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#define OP_RF ((OP_FAB << OP_V_F1) | (OP_ADF << OP_V_F2))
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#define OP_CV ((OP_CON << OP_V_F1) | (OP_VAR << OP_V_F2))
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#define OP_AC ((OP_ADR << OP_V_F1) | (OP_CON << OP_V_F2))
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#define OP_AA ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2))
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#define OP_AK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2))
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#define OP_AX ((OP_ADR << OP_V_F1) | (OP_ADX << OP_V_F2))
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#define OP_AT ((OP_ADR << OP_V_F1) | (OP_ADT << OP_V_F2))
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#define OP_KV ((OP_ADK << OP_V_F1) | (OP_VAR << OP_V_F2))
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#define OP_KA ((OP_ADK << OP_V_F1) | (OP_ADR << OP_V_F2))
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#define OP_KK ((OP_ADK << OP_V_F1) | (OP_ADK << OP_V_F2))
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#define OP_IIF ((OP_IAR << OP_V_F1) | (OP_IAR << OP_V_F2) | \
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(OP_ADF << OP_V_F3))
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#define OP_IAT ((OP_IAR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADT << OP_V_F3))
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#define OP_CVA ((OP_CON << OP_V_F1) | (OP_VAR << OP_V_F2) | \
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(OP_ADR << OP_V_F3))
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#define OP_AAA ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADR << OP_V_F3))
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#define OP_AAF ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADF << OP_V_F3))
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#define OP_AAX ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADX << OP_V_F3))
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#define OP_AAT ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADT << OP_V_F3))
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#define OP_AKA ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
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(OP_ADR << OP_V_F3))
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#define OP_AKK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
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(OP_ADK << OP_V_F3))
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#define OP_AXX ((OP_ADR << OP_V_F1) | (OP_ADX << OP_V_F2) | \
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(OP_ADX << OP_V_F3))
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#define OP_ATT ((OP_ADR << OP_V_F1) | (OP_ADT << OP_V_F2) | \
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(OP_ADT << OP_V_F3))
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#define OP_AEE ((OP_ADR << OP_V_F1) | (OP_ADE << OP_V_F2) | \
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(OP_ADE << OP_V_F3))
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#define OP_AAXX ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADX << OP_V_F3) | (OP_ADX << OP_V_F4))
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#define OP_AAFF ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADF << OP_V_F3) | (OP_ADF << OP_V_F4))
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#define OP_AAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADK << OP_V_F3) | (OP_ADK << OP_V_F4))
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#define OP_KKKK ((OP_ADK << OP_V_F1) | (OP_ADK << OP_V_F2) | \
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(OP_ADK << OP_V_F3) | (OP_ADK << OP_V_F4))
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#define OP_AAAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \
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(OP_ADK << OP_V_F5))
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#define OP_AKAKK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
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(OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \
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(OP_ADK << OP_V_F5))
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#define OP_AAACCC ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADR << OP_V_F3) | (OP_CON << OP_V_F4) | \
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(OP_CON << OP_V_F5) | (OP_CON << OP_V_F6))
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#define OP_AAFFKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADF << OP_V_F3) | (OP_ADF << OP_V_F4) | \
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(OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))
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#define OP_AAKAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADK << OP_V_F3) | (OP_ADR << OP_V_F4) | \
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(OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))
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#define OP_CATAKK ((OP_CON << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADT << OP_V_F3) | (OP_ADR << OP_V_F4) | \
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(OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))
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#define OP_CCCACC ((OP_CON << OP_V_F1) | (OP_CON << OP_V_F2) | \
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(OP_CON << OP_V_F3) | (OP_ADR << OP_V_F4) | \
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(OP_CON << OP_V_F5) | (OP_CON << OP_V_F6))
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#define OP_AAAFFKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADR << OP_V_F3) | (OP_ADF << OP_V_F4) | \
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(OP_ADF << OP_V_F5) | (OP_ADK << OP_V_F6) | \
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(OP_ADK << OP_V_F7))
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#define OP_AKAKAKK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \
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(OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \
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(OP_ADR << OP_V_F5) | (OP_ADK << OP_V_F6) | \
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(OP_ADK << OP_V_F7))
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#define OP_AAKAKAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \
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(OP_ADK << OP_V_F3) | (OP_ADR << OP_V_F4) | \
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(OP_ADK << OP_V_F5) | (OP_ADR << OP_V_F6) | \
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(OP_ADK << OP_V_F7) | (OP_ADK << OP_V_F8))
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#define OP_CCACACCA ((OP_CON << OP_V_F1) | (OP_CON << OP_V_F2) | \
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(OP_ADR << OP_V_F3) | (OP_CON << OP_V_F4) | \
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(OP_ADR << OP_V_F5) | (OP_CON << OP_V_F6) | \
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(OP_CON << OP_V_F7) | (OP_ADR << OP_V_F8))
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/* Operand precisions (compatible with F-Series FPP):
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- S = 1-word integer
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- D = 2-word integer
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- F = 2-word single-precision floating-point
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- X = 3-word extended-precision floating-point
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- T = 4-word double-precision floating-point
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- E = 5-word expanded-exponent floating-point
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- A = null operand (operand is in FPP accumulator)
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5-word floating-point numbers are supported by the F-Series Floating-Point
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Processor hardware, but the instruction codes are not documented.
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Note that ordering is important, as we depend on the "fp" type codes to
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reflect the number of words needed.
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*/
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typedef enum { in_s, in_d, fp_f, fp_x, fp_t, fp_e, fp_a } OPSIZE;
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/* Conversion from operand size to word count */
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#define TO_COUNT(s) ((s == fp_a) ? 0 : (uint32) (s + (s < fp_f)))
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/* HP in-memory representation of a packed floating-point number.
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Actual value will use two, three, four, or five words, as needed.
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*/
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typedef uint16 FPK[5];
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/* Operand processing types.
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NOTE: Microsoft VC++ 6.0 does not support the C99 standard, so we cannot
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initialize unions by arbitrary variant ("designated initializers").
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Therefore, we follow the C90 form of initializing via the first named
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variant. The FPK variant must appear first in the OP structure, as we define
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a number of FPK constants in other modules.
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*/
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typedef union { /* general operand */
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FPK fpk; /* floating-point value */
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uint16 word; /* 16-bit integer */
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uint32 dword; /* 32-bit integer */
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} OP;
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typedef OP OPS[OP_N_F]; /* operand array */
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typedef uint32 OP_PAT; /* operand pattern */
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/* Microcode dispatcher functions (grouped by cpu module number) */
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extern t_stat cpu_ds (uint32 IR, uint32 intrq); /* [0] Distributed System stub */
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extern t_stat cpu_user (uint32 IR, uint32 intrq); /* [0] User firmware dispatcher */
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extern t_stat cpu_user_20 (uint32 IR, uint32 intrq); /* [0] Module 20 user microprograms stub */
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extern t_stat cpu_eau (uint32 IR, uint32 intrq); /* [1] EAU group simulator */
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extern t_stat cpu_uig_0 (uint32 IR, uint32 intrq, uint32 iotrap); /* [1] UIG group 0 dispatcher */
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extern t_stat cpu_uig_1 (uint32 IR, uint32 intrq, uint32 iotrap); /* [1] UIG group 1 dispatcher */
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#if !defined (HAVE_INT64) /* int64 support unavailable */
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extern t_stat cpu_fp (uint32 IR, uint32 intrq); /* [2] Firmware Floating Point */
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#endif
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extern t_stat cpu_dms (uint32 IR, uint32 intrq); /* [2] Dynamic mapping system */
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extern t_stat cpu_eig (uint32 IR, uint32 intrq); /* [2] Extended instruction group */
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extern t_stat cpu_iop (uint32 IR, uint32 intrq); /* [2] 2000 I/O Processor */
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extern t_stat cpu_ffp (uint32 IR, uint32 intrq); /* [3] Fast FORTRAN Processor */
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extern t_stat cpu_dbi (uint32 IR, uint32 intrq); /* [3] Double-Integer instructions */
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#if defined (HAVE_INT64) /* int64 support available */
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extern t_stat cpu_fpp (uint32 IR, uint32 intrq); /* [4] Floating Point Processor */
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extern t_stat cpu_sis (uint32 IR, uint32 intrq); /* [4] Scientific Instruction Set */
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#endif
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extern t_stat cpu_rte_vma (uint32 IR, uint32 intrq); /* [5] RTE-6 VMA */
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extern t_stat cpu_rte_ema (uint32 IR, uint32 intrq); /* [5] RTE-IV EMA */
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extern t_stat cpu_rte_os (uint32 IR, uint32 intrq, uint32 iotrap); /* [6] RTE-6 OS */
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#if defined (HAVE_INT64) /* int64 support available */
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extern t_stat cpu_vis (uint32 IR, uint32 intrq); /* [7] Vector Instruction Set */
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extern t_stat cpu_signal (uint32 IR, uint32 intrq); /* [7] SIGNAL/1000 Instructions */
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#endif
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/* Microcode helper functions */
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OP ReadOp (uint32 va, OPSIZE precision); /* generalized operand read */
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void WriteOp (uint32 va, OP operand, OPSIZE precision); /* generalized operand write */
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t_stat cpu_ops (OP_PAT pattern, OPS op, uint32 irq); /* operand processor */
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void fprint_ops (OP_PAT pattern, OPS op); /* debug print operands */
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void fprint_regs (char *caption, uint32 regs, uint32 base); /* debug print CPU registers */
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#endif
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