687 lines
27 KiB
C
687 lines
27 KiB
C
/* vax_stddev.c: VAX 3900 standard I/O devices
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Copyright (c) 1998-2012, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tti terminal input
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tto terminal output
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clk 100Hz and TODR clock
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18-Apr-12 RMS Revised TTI to use clock coscheduling and
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remove IORESET bug
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13-Jan-12 MP Normalized the saved format of the TODR persistent
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file so that it may be moved around from one platform
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to another along with other simulator state files
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(disk & tape images, save/restore files, etc.)
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28-Sep-11 MP Generalized setting TODR for all OSes.
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Unbound the TODR value from the 100hz clock tick
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interrupt. TODR now behaves like the original
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battery backed-up clock and runs with the wall
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clock, not the simulated instruction clock
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(except when running ROM diagnostics).
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Two operational modes are available:
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- Default VMS mode, which is similar to the previous
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behavior in that without initializing the TODR it
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would default to the value VMS would set it to if
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VMS knew the correct time. This would be correct
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almost all the time unless a VMS disk hadn't been
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booted from for more than a year. This mode
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produces strange time results for non VMS OSes on
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each system boot.
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- OS Agnostic mode. This mode behaves precisely like
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the VAX780 TODR and works correctly for all OSes.
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This mode is enabled by attaching the TODR to a
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battery backup state file for the TOY clock
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(i.e. sim> attach TODR TOY_CLOCK). When operating
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in OS Agnostic mode, the TODR will initially start
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counting from 0 and be adjusted differently when an
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OS specifically writes to the TODR. On the first OS
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boot with an attached TODR VMS will prompt to set
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the time unless the SYSGEN parameter TIMEPROMPTWAIT
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is set to 0.
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05-Jan-11 MP Added Asynch I/O support
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17-Aug-08 RMS Resync TODR on any clock reset
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18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock
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17-Oct-06 RMS Synced keyboard poll to real-time clock for idling
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22-Nov-05 RMS Revised for new terminal processing routines
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09-Sep-04 RMS Integrated powerup into RESET (with -p)
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28-May-04 RMS Removed SET TTI CTRL-C
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29-Dec-03 RMS Added console backpressure support
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25-Apr-03 RMS Revised for extended file support
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02-Mar-02 RMS Added SET TTI CTRL-C
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22-Dec-02 RMS Added console halt capability
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01-Nov-02 RMS Added 7B/8B capability to terminal
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12-Sep-02 RMS Removed paper tape, added variable vector support
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30-May-02 RMS Widened POS to 32b
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30-Apr-02 RMS Automatically set TODR to VMS-correct value during boot
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*/
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#include "vax_defs.h"
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#include "sim_tmxr.h"
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#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTICSR_RW (CSR_IE)
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#define TTIBUF_ERR 0x8000 /* error */
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#define TTIBUF_OVR 0x4000 /* overrun */
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#define TTIBUF_FRM 0x2000 /* framing error */
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#define TTIBUF_RBR 0x0400 /* receive break */
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#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOCSR_RW (CSR_IE)
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#define CLKCSR_IMP (CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 5000 /* 100 Hz */
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#define TMXR_MULT 1 /* 100 Hz */
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int32 tti_csr = 0; /* control/status */
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uint32 tti_buftime; /* time input character arrived */
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int32 tto_csr = 0; /* control/status */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 100; /* ticks/second */
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int32 todr_reg = 0; /* TODR register */
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int32 todr_blow = 1; /* TODR battery low */
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struct todr_battery_info {
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uint32 toy_gmtbase; /* GMT base of set value */
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uint32 toy_gmtbasemsec; /* The milliseconds of the set value */
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uint32 toy_endian_plus2; /* 2 -> Big Endian, 3 -> Little Endian, invalid otherwise */
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};
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typedef struct todr_battery_info TOY;
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int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* pgm timer poll */
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t_stat tti_svc (UNIT *uptr);
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t_stat tto_svc (UNIT *uptr);
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t_stat clk_svc (UNIT *uptr);
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t_stat tti_reset (DEVICE *dptr);
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t_stat tto_reset (DEVICE *dptr);
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t_stat clk_reset (DEVICE *dptr);
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t_stat clk_attach (UNIT *uptr, CONST char *cptr);
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t_stat clk_detach (UNIT *uptr);
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t_stat todr_resync (void);
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const char *tti_description (DEVICE *dptr);
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const char *tto_description (DEVICE *dptr);
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const char *clk_description (DEVICE *dptr);
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t_stat tti_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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t_stat tto_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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t_stat clk_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
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extern int32 sysd_hlt_enb (void);
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extern int32 fault_PC;
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/* TTI data structures
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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*/
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DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
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UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
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REG tti_reg[] = {
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{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
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{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
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{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
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{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
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{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
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{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
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{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
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{ NULL }
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};
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MTAB tti_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
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{ 0 }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 16, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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&tti_dib, 0, 0, NULL, NULL, NULL, &tti_help, NULL, NULL,
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&tti_description
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};
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/* TTO data structures
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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*/
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DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } };
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UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") },
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{ HRDATAD (CSR, tto_csr, 16, "control/status register") },
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{ FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") },
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{ FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") },
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{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
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{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
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{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
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{ NULL }
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};
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MTAB tto_mod[] = {
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing output)" },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 16, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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&tto_dib, 0, 0, NULL, NULL, NULL, &tto_help, NULL, NULL,
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&tto_description
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};
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } };
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UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
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REG clk_reg[] = {
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{ HRDATAD (CSR, clk_csr, 16, "control/status register") },
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{ FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") },
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{ FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
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{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
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{ FLDATAD (BLOW, todr_blow, 0, "TODR battery low indicator") },
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{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
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{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
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{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
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#if defined (SIM_ASYNCH_IO)
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{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
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{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
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{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
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#endif
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
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{ 0 }
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};
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#define DBG_REG 1 /* TODR register access */
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#define DBG_TIC 2 /* clock ticks */
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DEBTAB clk_debug[] = {
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{"REG", DBG_REG, "TODR register access"},
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{"TIC", DBG_TIC, "clock ticks"},
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{0}
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 0, 8, 4, 0, 32,
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NULL, NULL, &clk_reset,
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NULL, &clk_attach, &clk_detach,
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&clk_dib, DEV_DEBUG, 0, clk_debug,
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NULL, NULL, &clk_help, NULL, NULL,
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&clk_description
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};
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/* Clock and terminal MxPR routines
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iccs_rd/wr interval timer
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rxcs_rd/wr input control/status
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rxdb_rd input buffer
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txcs_rd/wr output control/status
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txdb_wr output buffer
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*/
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int32 iccs_rd (void)
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{
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return (clk_csr & CLKCSR_IMP);
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}
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int32 rxcs_rd (void)
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{
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return (tti_csr & TTICSR_IMP);
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}
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int32 rxdb_rd (void)
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{
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int32 t = tti_unit.buf; /* char + error */
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if (tti_csr & CSR_DONE) { /* Input pending ? */
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tti_csr = tti_csr & ~CSR_DONE; /* clr done */
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tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
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CLR_INT (TTI);
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sim_activate_after_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
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}
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return t;
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}
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int32 txcs_rd (void)
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{
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return (tto_csr & TTOCSR_IMP);
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}
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void iccs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (CLK);
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if (data & CSR_DONE) /* Interrupt Acked? */
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sim_rtcn_tick_ack (20, TMR_CLK); /* Let timers know */
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clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
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return;
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}
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void rxcs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (TTI);
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else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTI);
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tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);
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return;
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}
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void txcs_wr (int32 data)
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{
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if ((data & CSR_IE) == 0)
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CLR_INT (TTO);
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else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTO);
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tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
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return;
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}
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void txdb_wr (int32 data)
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{
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tto_unit.buf = data & 0377;
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tto_csr = tto_csr & ~CSR_DONE;
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CLR_INT (TTO);
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sim_activate (&tto_unit, tto_unit.wait);
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return;
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}
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/* Terminal input routines
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tti_svc process event (character ready)
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tti_reset process reset
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*/
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t_stat tti_svc (UNIT *uptr)
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{
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int32 c;
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sim_clock_coschedule_tmr (uptr, TMR_CLK, TMXR_MULT); /* continue poll */
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if ((tti_csr & CSR_DONE) && /* input still pending and < 500ms? */
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((sim_os_msec () - tti_buftime) < 500))
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return SCPE_OK;
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if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
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return c;
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if (c & SCPE_BREAK) { /* break? */
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if (sysd_hlt_enb ()) /* if enabled, halt */
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hlt_pin = 1;
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tti_unit.buf = TTIBUF_ERR | TTIBUF_FRM | TTIBUF_RBR;
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}
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else tti_unit.buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
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tti_buftime = sim_os_msec ();
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uptr->pos = uptr->pos + 1;
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tti_csr = tti_csr | CSR_DONE;
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if (tti_csr & CSR_IE)
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SET_INT (TTI);
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return SCPE_OK;
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}
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t_stat tti_reset (DEVICE *dptr)
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{
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tmxr_set_console_units (&tti_unit, &tto_unit);
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tti_unit.buf = 0;
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tti_csr = 0;
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CLR_INT (TTI);
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sim_activate (&tti_unit, tmr_poll);
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return SCPE_OK;
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}
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t_stat tti_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Console Terminal Input (TTI)\n\n");
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fprintf (st, "The terminal input (TTI) polls the console keyboard for input.\n\n");
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fprintf (st, "When the console terminal is attached to a Telnet session or the simulator is\n");
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fprintf (st, "running from a Windows command prompt, it recognizes BREAK. If BREAK is\n");
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fprintf (st, "entered, and BDR<7> is set (also known as SET CPU NOAUTOBOOT), control returns\n");
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fprintf (st, "to the console firmware; otherwise, BREAK is treated as a normal terminal\n");
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fprintf (st, "input condition.\n\n");
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fprint_set_help (st, dptr);
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fprint_show_help (st, dptr);
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fprint_reg_help (st, dptr);
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return SCPE_OK;
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}
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const char *tti_description (DEVICE *dptr)
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{
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return "console terminal input";
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}
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/* Terminal output routines
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tto_svc process event (character typed)
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tto_reset process reset
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*/
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t_stat tto_svc (UNIT *uptr)
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{
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int32 c;
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t_stat r;
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c = sim_tt_outcvt (tto_unit.buf, TT_GET_MODE (uptr->flags));
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if (c >= 0) {
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if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* retry */
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return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
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}
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}
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tto_csr = tto_csr | CSR_DONE;
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if (tto_csr & CSR_IE)
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SET_INT (TTO);
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uptr->pos = uptr->pos + 1;
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return SCPE_OK;
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}
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t_stat tto_reset (DEVICE *dptr)
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{
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tto_unit.buf = 0;
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tto_csr = CSR_DONE;
|
|
CLR_INT (TTO);
|
|
sim_cancel (&tto_unit); /* deactivate unit */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat tto_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf (st, "Console Terminal Output (TTO)\n\n");
|
|
fprintf (st, "The terminal output (TTO) writes to the simulator console.\n\n");
|
|
fprint_set_help (st, dptr);
|
|
fprint_show_help (st, dptr);
|
|
fprint_reg_help (st, dptr);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *tto_description (DEVICE *dptr)
|
|
{
|
|
return "console terminal output";
|
|
}
|
|
|
|
/* Clock routines
|
|
|
|
clk_svc process event (clock tick)
|
|
clk_reset process reset
|
|
todr_rd/wr time of year clock
|
|
todr_resync powerup for TODR (get date from system)
|
|
*/
|
|
|
|
t_stat clk_svc (UNIT *uptr)
|
|
{
|
|
int32 t;
|
|
|
|
if (clk_csr & CSR_IE)
|
|
SET_INT (CLK);
|
|
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
|
|
sim_activate_after (&clk_unit, 1000000/clk_tps); /* reactivate unit */
|
|
tmr_poll = t; /* set tmr poll */
|
|
tmxr_poll = t * TMXR_MULT; /* set mux poll */
|
|
if (!todr_blow && todr_reg) /* if running? */
|
|
todr_reg = todr_reg + 1; /* incr TODR */
|
|
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
int32 todr_rd (void)
|
|
{
|
|
TOY *toy = (TOY *)clk_unit.filebuf;
|
|
struct timespec base, now, val;
|
|
|
|
if ((fault_PC&0xFFFE0000) == 0x20040000) { /* running from ROM? */
|
|
sim_debug (DBG_REG, &clk_dev, "todr_rd(ROM) - TODR=0x%X\n", todr_reg);
|
|
return todr_reg; /* return counted value for ROM diags */
|
|
}
|
|
|
|
if (0 == todr_reg) { /* clock running? */
|
|
sim_debug (DBG_REG, &clk_dev, "todr_rd(Not Running) - TODR=0x%X\n", todr_reg);
|
|
return todr_reg;
|
|
}
|
|
|
|
/* Maximum number of seconds which can be represented as 10ms ticks
|
|
in the 32bit TODR. This is the 33bit value 0x100000000/100 to get seconds */
|
|
#define TOY_MAX_SECS (0x40000000/25)
|
|
|
|
sim_rtcn_get_time(&now, TMR_CLK); /* get curr time */
|
|
base.tv_sec = toy->toy_gmtbase;
|
|
base.tv_nsec = toy->toy_gmtbasemsec * 1000000;
|
|
sim_timespec_diff (&val, &now, &base);
|
|
|
|
if (val.tv_sec >= TOY_MAX_SECS) { /* todr overflowed? */
|
|
sim_debug (DBG_REG, &clk_dev, "todr_rd(Overflowed) - TODR=0x%X\n", 0);
|
|
return todr_reg = 0; /* stop counting */
|
|
}
|
|
|
|
sim_debug (DBG_REG, &clk_dev, "todr_rd() - TODR=0x%X\n", (int32)(val.tv_sec*100 + val.tv_nsec/10000000));
|
|
return (int32)(val.tv_sec*100 + (val.tv_nsec + 5000000)/10000000); /* 100hz Clock rounded Ticks */
|
|
}
|
|
|
|
|
|
void todr_wr (int32 data)
|
|
{
|
|
TOY *toy = (TOY *)clk_unit.filebuf;
|
|
struct timespec now, val, base;
|
|
|
|
if (data) {
|
|
todr_blow = 0;
|
|
/* Save the GMT time when set value is not 0 to record the base for
|
|
future read operations in "battery backed-up" state */
|
|
|
|
sim_rtcn_get_time(&now, TMR_CLK); /* get curr time */
|
|
val.tv_sec = ((uint32)data) / 100;
|
|
val.tv_nsec = (((uint32)data) % 100) * 10000000;
|
|
sim_timespec_diff (&base, &now, &val); /* base = now - data */
|
|
toy->toy_gmtbase = (uint32)base.tv_sec;
|
|
toy->toy_gmtbasemsec = (base.tv_nsec + 500000)/1000000;
|
|
}
|
|
else { /* stop the clock */
|
|
toy->toy_gmtbase = 0;
|
|
toy->toy_gmtbasemsec = 0;
|
|
}
|
|
if (clk_unit.flags & UNIT_ATT) { /* OS Agnostic mode? */
|
|
rewind (clk_unit.fileref);
|
|
fwrite (toy, sizeof (*toy), 1, clk_unit.fileref); /* Save sync time info */
|
|
fflush (clk_unit.fileref);
|
|
}
|
|
todr_reg = data;
|
|
sim_debug (DBG_REG, &clk_dev, "todr_wr(0x%X) - TODR=0x%X blow=%d\n", data, todr_reg, todr_blow);
|
|
}
|
|
|
|
/* TODR resync routine */
|
|
|
|
t_stat todr_resync (void)
|
|
{
|
|
TOY *toy = (TOY *)clk_unit.filebuf;
|
|
|
|
if (clk_unit.flags & UNIT_ATT) { /* Attached means behave like real VAX780 */
|
|
if (!toy->toy_gmtbase) /* Never set? */
|
|
todr_wr (0); /* Start ticking from 0 */
|
|
}
|
|
else { /* Not-Attached means */
|
|
uint32 base; /* behave like simh VMS default */
|
|
time_t curr;
|
|
struct tm *ctm;
|
|
struct timespec now;
|
|
|
|
sim_rtcn_get_time(&now, TMR_CLK); /* get curr time */
|
|
curr = (time_t)now.tv_sec;
|
|
if (curr == (time_t) -1) /* error? */
|
|
return SCPE_NOFNC;
|
|
ctm = localtime (&curr); /* decompose */
|
|
if (ctm == NULL) /* error? */
|
|
return SCPE_NOFNC;
|
|
base = (((((ctm->tm_yday * 24) + /* sec since 1-Jan */
|
|
ctm->tm_hour) * 60) +
|
|
ctm->tm_min) * 60) +
|
|
ctm->tm_sec;
|
|
todr_wr ((base * 100) + 0x10000000 + /* use VMS form */
|
|
(int32)((now.tv_nsec + 5000000)/ 10000000));
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Reset routine */
|
|
|
|
t_stat clk_reset (DEVICE *dptr)
|
|
{
|
|
int32 t;
|
|
|
|
clk_csr = 0;
|
|
CLR_INT (CLK);
|
|
if (!sim_is_running) { /* RESET (not IORESET)? */
|
|
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
|
|
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
|
|
tmr_poll = t; /* set tmr poll */
|
|
tmxr_poll = t * TMXR_MULT; /* set mux poll */
|
|
}
|
|
if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
|
|
clk_unit.filebuf = calloc(sizeof(TOY), 1);
|
|
if (clk_unit.filebuf == NULL)
|
|
return SCPE_MEM;
|
|
todr_resync ();
|
|
}
|
|
return SCPE_OK;
|
|
}
|
|
|
|
t_stat clk_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf (st, "Real-Time Clock (%s)\n\n", dptr->name);
|
|
fprintf (st, "The real-time clock autocalibrates; the clock interval is adjusted up or down\n");
|
|
fprintf (st, "so that the clock tracks actual elapsed time.\n\n");
|
|
fprintf (st, "The TODR (Time Of Day Register) is a 32 bit register that counts up once every\n");
|
|
fprintf (st, "10 milliseconds of wall clock time. At the 10 millisecond rate, the 32 bit\n");
|
|
fprintf (st, "value will overflow after approximately 16 months. The operating system\n");
|
|
fprintf (st, "running on the machine generally keeps track of when the system date/time has\n");
|
|
fprintf (st, "been set and thus can use the system's known base time plus the current TODR\n");
|
|
fprintf (st, "value to provide the correct current date/time.\n\n");
|
|
fprintf (st, "There are two modes of TODR operation:\n\n");
|
|
fprintf (st, " Default VMS mode. Without initializing the TODR it returns the current\n");
|
|
fprintf (st, " time of year offset which VMS would set the clock to\n");
|
|
fprintf (st, " if VMS knew the correct time (i.e. by manual input).\n");
|
|
fprintf (st, " This is correct almost all the time unless a VMS disk\n");
|
|
fprintf (st, " hadn't been booted from in the current year. This mode\n");
|
|
fprintf (st, " produces strange time results for non VMS OSes on each\n");
|
|
fprintf (st, " system boot.\n");
|
|
fprintf (st, " OS Agnostic mode. This mode behaves precisely like the VAX780 TODR and\n");
|
|
fprintf (st, " works correctly for all OSes. This mode is enabled by\n");
|
|
fprintf (st, " attaching the %s to a battery backup state file for the\n", dptr->name);
|
|
fprintf (st, " TOY clock (i.e. sim> attach %s TOY_CLOCK). When\n", dptr->name);
|
|
fprintf (st, " operating in OS Agnostic mode, the TODR will initially\n");
|
|
fprintf (st, " start counting from 0 and be adjusted differently when\n");
|
|
fprintf (st, " an OS specifically writes to the TODR. VMS determines\n");
|
|
fprintf (st, " if the TODR currently contains a valid time if the value\n");
|
|
fprintf (st, " it sees is less than about 1 month. If the time isn't\n");
|
|
fprintf (st, " valid VMS will prompt to set the time during the system\n");
|
|
fprintf (st, " boot. While prompting for the time it will wait for an\n");
|
|
fprintf (st, " answer to the prompt for up to the SYSGEN parameter\n");
|
|
fprintf (st, " TIMEPROMPTWAIT seconds. A value of 0 for TIMEPROMPTWAIT\n");
|
|
fprintf (st, " will disable the clock setting prompt.\n");
|
|
fprint_reg_help (st, dptr);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
const char *clk_description (DEVICE *dptr)
|
|
{
|
|
return "time of year clock";
|
|
}
|
|
|
|
static uint32 sim_byteswap32 (uint32 data)
|
|
{
|
|
uint8 *bdata = (uint8 *)&data;
|
|
uint8 tmp;
|
|
|
|
tmp = bdata[0];
|
|
bdata[0] = bdata[3];
|
|
bdata[3] = tmp;
|
|
tmp = bdata[1];
|
|
bdata[1] = bdata[2];
|
|
bdata[2] = tmp;
|
|
return data;
|
|
}
|
|
|
|
/* CLK attach */
|
|
|
|
t_stat clk_attach (UNIT *uptr, CONST char *cptr)
|
|
{
|
|
t_stat r;
|
|
|
|
uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE);
|
|
memset (uptr->filebuf, 0, (size_t)uptr->capac);
|
|
r = attach_unit (uptr, cptr);
|
|
if (r != SCPE_OK)
|
|
uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
|
|
else {
|
|
TOY *toy = (TOY *)uptr->filebuf;
|
|
|
|
uptr->hwmark = (uint32) uptr->capac;
|
|
if ((toy->toy_endian_plus2 < 2) || (toy->toy_endian_plus2 > 3))
|
|
memset (uptr->filebuf, 0, (size_t)uptr->capac);
|
|
else {
|
|
if (toy->toy_endian_plus2 != sim_end + 2) { /* wrong endian? */
|
|
toy->toy_gmtbase = sim_byteswap32 (toy->toy_gmtbase);
|
|
toy->toy_gmtbasemsec = sim_byteswap32 (toy->toy_gmtbasemsec);
|
|
}
|
|
}
|
|
toy->toy_endian_plus2 = sim_end + 2;
|
|
todr_resync ();
|
|
}
|
|
return r;
|
|
}
|
|
|
|
/* CLK detach */
|
|
|
|
t_stat clk_detach (UNIT *uptr)
|
|
{
|
|
t_stat r;
|
|
|
|
r = detach_unit (uptr);
|
|
if ((uptr->flags & UNIT_ATT) == 0)
|
|
uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE);
|
|
return r;
|
|
}
|
|
|