5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
304 lines
12 KiB
C
304 lines
12 KiB
C
/* pdp18b_rb.c: RB09 fixed head disk simulator
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Copyright (c) 2003-2016, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rb RB09 fixed head disk
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07-Mar-16 RMS Revised for dynamically allocated memory
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03-Sep-13 RMS Added explicit void * cast
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14-Jan-04 RMS Revised IO device call interface
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26-Oct-03 RMS Cleaned up buffer copy code
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The RB09 is a head-per-track disk. It uses the single cycle data break
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facility. To minimize overhead, the entire RB09 is buffered in memory.
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Two timing parameters are provided:
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rb_time Interword timing. Must be non-zero.
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rb_burst Burst mode. If 0, DMA occurs cycle by cycle; otherwise,
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DMA occurs in a burst.
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*/
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#include "pdp18b_defs.h"
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#include <math.h>
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/* Constants */
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#define RB_NUMWD 64 /* words/sector */
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#define RB_NUMSC 80 /* sectors/track */
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#define RB_NUMTR 200 /* tracks/disk */
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#define RB_WLKTR 10 /* tracks/wlock switch */
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#define RB_SIZE (RB_NUMTR * RB_NUMSC * RB_NUMWD) /* words/drive */
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/* Function/status register */
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#define RBS_ERR 0400000 /* error */
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#define RBS_PAR 0200000 /* parity error */
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#define RBS_ILA 0100000 /* ill addr error */
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#define RBS_TIM 0040000 /* timing transfer */
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#define RBS_NRY 0020000 /* not ready error */
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#define RBS_DON 0010000 /* done */
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#define RBS_IE 0004000 /* int enable */
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#define RBS_BSY 0002000 /* busy */
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#define RBS_WR 0001000 /* read/write */
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#define RBS_XOR (RBS_IE|RBS_BSY|RBS_WR) /* set by XOR */
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#define RBS_MBZ 0000777 /* always clear */
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#define RBS_EFLGS (RBS_PAR|RBS_ILA|RBS_TIM|RBS_NRY) /* error flags */
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/* BCD disk address */
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#define RBA_V_TR 8
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#define RBA_M_TR 0x1FF
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#define RBA_V_SC 0
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#define RBA_M_SC 0xFF
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#define RBA_GETTR(x) (((x) >> RBA_V_TR) & RBA_M_TR)
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#define RBA_GETSC(x) (((x) >> RBA_V_SC) & RBA_M_SC)
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#define GET_POS(x) ((int) fmod (sim_gtime () / ((double) (x)), \
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((double) (RB_NUMSC * RB_NUMWD))))
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extern int32 *M;
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extern int32 int_hwre[API_HLVL+1];
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extern UNIT cpu_unit;
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int32 rb_sta = 0; /* status register */
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int32 rb_da = 0; /* disk address */
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int32 rb_ma = 0; /* current addr */
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int32 rb_wc = 0; /* word count */
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int32 rb_wlk = 0; /* write lock */
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int32 rb_time = 10; /* inter-word time */
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int32 rb_burst = 1; /* burst mode flag */
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int32 rb_stopioe = 1; /* stop on error */
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int32 rb71 (int32 dev, int32 pulse, int32 AC);
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t_stat rb_svc (UNIT *uptr);
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t_stat rb_reset (DEVICE *dptr);
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int32 rb_updsta (int32 val);
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int32 rb_make_da (int32 dat);
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int32 rb_make_bcd (int32 dat);
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int32 rb_set_da (int32 dat, int32 old);
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int32 rb_set_bcd (int32 dat);
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/* RB data structures
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rb_dev RF device descriptor
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rb_unit RF unit descriptor
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rb_reg RF register list
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*/
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DIB rb_dib = { DEV_RB, 1, NULL, { &rb71 } };
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UNIT rb_unit = {
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UDATA (&rb_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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RB_SIZE)
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};
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REG rb_reg[] = {
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{ ORDATA (STA, rb_sta, 18) },
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{ ORDATA (DA, rb_da, 20) },
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{ ORDATA (WC, rb_wc, 16) },
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{ ORDATA (MA, rb_ma, ADDRSIZE) },
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{ FLDATA (INT, int_hwre[API_RB], INT_V_RB) },
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{ ORDATA (WLK, rb_wlk, RB_NUMTR / RB_WLKTR) },
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{ DRDATA (TIME, rb_time, 24), PV_LEFT + REG_NZ },
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{ FLDATA (BURST, rb_burst, 0) },
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{ FLDATA (STOP_IOE, rb_stopioe, 0) },
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{ ORDATA (DEVNO, rb_dib.dev, 6), REG_HRO },
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{ NULL }
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};
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MTAB rb_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
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{ 0 }
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};
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DEVICE rb_dev = {
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"RB", &rb_unit, rb_reg, rb_mod,
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1, 8, 21, 1, 8, 18,
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NULL, NULL, &rb_reset,
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NULL, NULL, NULL,
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&rb_dib, DEV_DIS | DEV_DISABLE
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};
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/* IOT routines */
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int32 rb71 (int32 dev, int32 pulse, int32 AC)
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{
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int32 tow, t, sb = pulse & 060;
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if (pulse & 001) {
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if (sb == 000) /* DBCF */
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rb_sta = rb_sta & ~(RBS_ERR | RBS_EFLGS | RBS_DON);
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if ((sb == 020) && (rb_sta & (RBS_ERR | RBS_DON)))
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AC = AC | IOT_SKP; /* DBSF */
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if (sb == 040) /* DBCS */
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rb_sta = 0;
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}
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if (pulse & 002) {
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if (sb == 000) /* DBRD */
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AC = AC | rb_make_da (rb_da);
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if (sb == 020) /* DBRS */
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AC = AC | rb_sta;
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if (sb == 040) /* DBLM */
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rb_ma = AC & AMASK;
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}
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if (pulse & 004) {
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if (sb == 000) /* DBLD */
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rb_da = rb_set_da (AC, rb_da);
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if (sb == 020) /* DBLW */
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rb_wc = AC & 0177777;
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if (sb == 040) { /* DBLS */
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rb_sta = (rb_sta & RBS_XOR) ^ (AC & ~RBS_MBZ);
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if (rb_sta & RBS_BSY) { /* busy set? */
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if (!sim_is_active (&rb_unit)) { /* schedule */
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tow = rb_da % (RB_NUMSC * RB_NUMWD);
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t = tow - GET_POS (rb_time);
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if (t < 0)
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t = t + (RB_NUMSC * RB_NUMWD);
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sim_activate (&rb_unit, t * rb_time);
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}
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}
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else sim_cancel (&rb_unit); /* no, stop */
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}
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}
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rb_updsta (0); /* update status */
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return AC;
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}
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int32 rb_make_da (int32 da)
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{
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int32 t = da / (RB_NUMSC * RB_NUMWD); /* bin track */
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int32 s = (da % (RB_NUMSC * RB_NUMWD)) / RB_NUMWD; /* bin sector */
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int32 bcd_t = rb_make_bcd (t); /* bcd track */
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int32 bcd_s = rb_make_bcd (s); /* bcd sector */
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return (bcd_t << RBA_V_TR) | (bcd_s << RBA_V_SC);
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}
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int32 rb_set_da (int32 bcda, int32 old_da)
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{
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int32 bcd_t = RBA_GETTR (bcda); /* bcd track */
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int32 bcd_s = RBA_GETSC (bcda); /* bcd sector */
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int32 t = rb_set_bcd (bcd_t); /* bin track */
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int32 s = rb_set_bcd (bcd_s); /* bin sector */
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if ((t >= RB_NUMTR) || (t < 0) || /* invalid? */
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(s >= RB_NUMSC) || (s < 0)) {
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rb_updsta (RBS_ILA); /* error */
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return old_da; /* don't change */
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}
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else return (((t * RB_NUMSC) + s) * RB_NUMWD); /* new da */
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}
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int32 rb_make_bcd (int32 bin)
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{
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int32 d, i, r;
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for (r = i = 0; bin != 0; bin = bin / 10) { /* while nz */
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d = bin % 10; /* dec digit */
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r = r | (d << i); /* insert bcd */
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i = i + 4;
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}
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return r;
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}
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int32 rb_set_bcd (int32 bcd)
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{
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int32 d, i, r;
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for (r = 0, i = 1; bcd != 0; bcd = bcd >> 4) { /* while nz */
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d = bcd & 0xF; /* bcd digit */
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if (d >= 10) /* invalid? */
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return -1;
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r = r + (d * i); /* insert bin */
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i = i * 10;
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}
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return r;
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}
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/* Unit service - disk is buffered in memory */
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t_stat rb_svc (UNIT *uptr)
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{
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int32 t, sw;
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int32 *fbuf = (int32 *) uptr->filebuf;
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
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rb_updsta (RBS_NRY | RBS_DON); /* set nxd, done */
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return IORETURN (rb_stopioe, SCPE_UNATT);
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}
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do {
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if (rb_sta & RBS_WR) { /* write? */
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t = rb_da / (RB_NUMSC * RB_NUMWD); /* track */
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sw = t / RB_WLKTR; /* switch */
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if ((rb_wlk >> sw) & 1) { /* write locked? */
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rb_updsta (RBS_ILA | RBS_DON);
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break;
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}
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else { /* not locked */
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fbuf[rb_da] = M[rb_ma]; /* write word */
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if (((t_addr) rb_da) >= uptr->hwmark)
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uptr->hwmark = rb_da + 1;
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}
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}
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else if (MEM_ADDR_OK (rb_ma)) /* read, valid addr? */
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M[rb_ma] = fbuf[rb_da]; /* read word */
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rb_wc = (rb_wc + 1) & 0177777; /* incr word count */
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rb_ma = (rb_ma + 1) & AMASK; /* incr mem addr */
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rb_da = rb_da + 1; /* incr disk addr */
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if (rb_da > RB_SIZE) /* disk wraparound? */
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rb_da = 0;
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} while ((rb_wc != 0) && (rb_burst != 0)); /* brk if wc, no brst */
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if ((rb_wc != 0) && ((rb_sta & RBS_ERR) == 0)) /* more to do? */
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sim_activate (&rb_unit, rb_time); /* sched next */
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else rb_updsta (RBS_DON); /* set done */
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return SCPE_OK;
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}
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/* Update status */
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int32 rb_updsta (int32 val)
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{
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rb_sta = (rb_sta | val) & ~(RBS_ERR | RBS_MBZ); /* clear err, mbz */
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if (rb_sta & RBS_EFLGS) /* error? */
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rb_sta = rb_sta | RBS_ERR;
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if (rb_sta & RBS_DON) /* done? clear busy */
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rb_sta = rb_sta & ~RBS_BSY;
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if ((rb_sta & (RBS_ERR | RBS_DON)) && (rb_sta & RBS_IE))
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SET_INT (RB); /* set or clr intr */
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else CLR_INT (RB);
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return rb_sta;
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}
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/* Reset routine */
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t_stat rb_reset (DEVICE *dptr)
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{
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rb_sta = rb_da = 0;
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rb_wc = rb_ma = 0;
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rb_updsta (0);
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sim_cancel (&rb_unit);
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return SCPE_OK;
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}
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