844 lines
28 KiB
C
844 lines
28 KiB
C
/* 3b2_cpu.h: AT&T 3B2 Model 400 Hard Disk (uPD7261) Implementation
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Copyright (c) 2017, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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/*
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* The larger of the two hard drive options shipped with the AT&T 3B2
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* was a 72MB Wren II ST-506 MFM hard disk. That's what we emulate
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* here, as a start.
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*
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* Formatted Capacity: 76,723,200 Bytes
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*
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* Cylinders: 925
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* Sectors/Track: 18
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* Heads: 9
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* Bytes/Sector: 512
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* Avg. seek: 28 ms
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* Seek/track: 5 ms
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*
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* Drive Information from the 3B2 FAQ:
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*
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* Drive type drv id cyls trk/cyl sec/trk byte/cyl abbrev
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* --------------- ------ ---- ------- ------- -------- ------
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* Wren II 30MB 3 697 5 18 512 HD30
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* Wren II 72MB 5 925 9 18 512 HD72
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* Fujitsu M2243AS 8 754 11 18 512 HD72C
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* Micropolis 1325 5 1024 8 18 512 HD72
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* Maxtor 1140 4* 918= 15 18 512 HD120
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* Maxtor 1190 11 1224+ 15 18 512 HD135
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*
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*/
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#include <assert.h>
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#include "3b2_id.h"
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/* Wait times, in CPU steps, for various actions */
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/* Each step is 50 us in buffered mode */
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#define ID_SEEK_WAIT 100 /* us */
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#define ID_SEEK_BASE 700 /* us */
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#define ID_RECAL_WAIT 6000 /* us */
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/* Reading data takes about 8ms per sector, plus time to seek if not
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on cylinder */
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#define ID_RW_WAIT 8000 /* us */
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/* Sense Unit Status completes in about 200 us */
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#define ID_SUS_WAIT 200 /* us */
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/* Specify takes a bit longer, 1.25 ms */
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#define ID_SPEC_WAIT 1250 /* us */
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/* Sense Interrupt Status is about 142 us */
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#define ID_SIS_WAIT 142 /* us */
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/* The catch-all command wait time is about 140 us */
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#define ID_CMD_WAIT 140 /* us */
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/* State. The DP7261 supports four MFM (winchester) disks connected
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simultaneously. There is only one set of registers, however, so
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commands must be completed for one unit before they can begin on
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another unit. */
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/* Data FIFO pointer - Read */
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uint8 id_dpr = 0;
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/* Data FIFO pointer - Write */
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uint8 id_dpw = 0;
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/* Selected unit */
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uint8 id_sel = 0;
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/* Controller Status Register */
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uint8 id_status = 0;
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/* Unit Interrupt Status */
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uint8 id_int_status;
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/* Last command received */
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uint8 id_cmd = 0;
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/* DMAC request */
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t_bool id_drq = FALSE;
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/* 8-byte FIFO */
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uint8 id_data[ID_FIFO_LEN] = {0};
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/* INT output pin */
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t_bool id_irq = FALSE;
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/* Special flag for seek end SIS */
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t_bool id_seek_sis = FALSE;
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/* State of each drive */
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/* Cylinder the drive is positioned on */
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uint16 id_cyl[ID_NUM_UNITS] = {0};
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/* DTLH byte for each drive */
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uint8 id_dtlh[ID_NUM_UNITS] = {0};
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/* Arguments of last READ, WRITE, VERIFY ID, or READ ID command */
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/* Ending Track Number (from Specify) */
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uint8 id_etn = 0;
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/* Ending Sector Number (from Specify) */
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uint8 id_esn = 0;
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/* Physical sector number */
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uint8 id_psn = 0;
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/* Physical head number */
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uint8 id_phn = 0;
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/* Logical cylinder number, high byte */
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uint8 id_lcnh = 0;
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/* Logical cylinder number, low byte */
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uint8 id_lcnl = 0;
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/* Logical head number */
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uint8 id_lhn = 0;
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/* Logical sector number */
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uint8 id_lsn = 0;
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/* Number of sectors to transfer, decremented after each sector */
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uint8 id_scnt = 0;
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/* Sector buffer */
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uint8 id_buf[ID_SEC_SIZE];
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/* Buffer pointer */
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size_t id_buf_ptr = 0;
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uint8 id_idfield[ID_IDFIELD_LEN];
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uint8 id_idfield_ptr = 0;
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/*
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* TODO: Macros used for debugging timers. Remove when debugging is complete.
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*/
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double id_start_time;
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#define ID_START_TIME() { id_start_time = sim_gtime(); }
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#define ID_DIFF_MS() ((sim_gtime() - id_start_time) / INST_PER_MS)
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UNIT id_unit[] = {
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{UDATA (&id_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BINK, ID_DSK_SIZE), 0, 0 },
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{UDATA (&id_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BINK, ID_DSK_SIZE), 0, 1 },
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{ NULL }
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};
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/* The currently selected drive number */
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UNIT *id_sel_unit = &id_unit[0];
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REG id_reg[] = {
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{ HRDATAD(CMD, id_cmd, 8, "Command") },
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{ HRDATAD(STAT, id_status, 8, "Status") },
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{ BRDATAD(CYL, id_cyl, 8, 8, ID_NUM_UNITS, "Track") },
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{ NULL }
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};
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DEVICE id_dev = {
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"ID", id_unit, id_reg, NULL,
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ID_NUM_UNITS, 16, 32, 1, 16, 8,
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NULL, NULL, &id_reset,
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NULL, &id_attach, &id_detach, NULL,
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DEV_DEBUG|DEV_SECTORS, 0, sys_deb_tab,
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NULL, NULL, &id_help, NULL, NULL,
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&id_description
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};
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/* Function implementation */
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static SIM_INLINE void id_activate(uint32 delay)
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{
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ID_START_TIME();
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sim_activate_abs(id_sel_unit, (int32) delay);
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}
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static SIM_INLINE void id_clear_fifo()
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{
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id_dpr = 0;
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id_dpw = 0;
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}
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t_stat id_svc(UNIT *uptr)
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{
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/* Complete the last command */
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id_status = ID_STAT_CEH;
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switch (CMD_NUM) {
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case ID_CMD_SEEK: /* fall-through */
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case ID_CMD_RECAL:
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/* SRQ is only set in polling mode (POL bit is 0) */
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if ((id_dtlh[UNIT_NUM] & ID_DTLH_POLL) == 0) {
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id_status |= ID_STAT_SRQ;
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}
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if (uptr->flags & UNIT_ATT) {
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id_int_status = ID_IST_SEN|(uint8)uptr->ID_UNIT_NUM;
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} else {
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id_int_status = ID_IST_NR|(uint8)uptr->ID_UNIT_NUM;
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}
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break;
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case ID_CMD_SIS:
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if (!id_seek_sis) {
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id_status = ID_STAT_CEL;
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}
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id_seek_sis = FALSE;
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id_data[0] = id_int_status;
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id_status &= ~ID_STAT_SRQ;
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break;
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case ID_CMD_SUS:
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if ((id_sel_unit->flags & UNIT_ATT) == 0) {
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/* If no HD is attached, SUS puts 0x00 into the data
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buffer */
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id_data[0] = 0;
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} else {
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/* Put Unit Status into byte 0 */
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id_data[0] = (ID_UST_DSEL|ID_UST_SCL|ID_UST_RDY);
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if (id_cyl[UNIT_NUM] == 0) {
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id_data[0] |= ID_UST_TK0;
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}
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}
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break;
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default:
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break;
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}
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sim_debug(EXECUTE_MSG, &id_dev,
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"[%08x] \tINTR\t\tDELTA=%f ms\n",
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R[NUM_PC], ID_DIFF_MS());
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id_irq = TRUE;
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return SCPE_OK;
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}
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t_stat id_reset(DEVICE *dptr)
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{
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id_clear_fifo();
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return SCPE_OK;
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}
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t_stat id_attach(UNIT *uptr, CONST char *cptr)
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{
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return sim_disk_attach(uptr, cptr, 512, 1, TRUE, 0, "HD72", 0, 0);
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}
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t_stat id_detach(UNIT *uptr)
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{
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return sim_disk_detach(uptr);
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}
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/* Return the logical block address of the given sector */
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static SIM_INLINE t_lba id_lba(uint16 cyl, uint8 head, uint8 sec)
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{
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return((ID_SEC_CNT * ID_HEADS * cyl) +
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(ID_SEC_CNT * head) +
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sec);
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}
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/* At the end of each sector read or write, we update the FIFO
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* with the correct return parameters. */
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static void SIM_INLINE id_end_rw(uint8 est) {
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sim_debug(EXECUTE_MSG, &id_dev,
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">>> ending R/W with status: %02x\n",
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est);
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id_dpr = 0;
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id_dpw = 0;
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id_data[0] = est;
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id_data[1] = id_phn;
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id_data[2] = ~(id_lcnh);
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id_data[3] = id_lcnl;
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id_data[4] = id_lhn;
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id_data[5] = id_lsn;
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id_data[6] = id_scnt;
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}
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/* The controller wraps id_lsn, id_lhn, and id_lcnl on each sector
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* read, so that they point to the next C/H/S */
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static void SIM_INLINE id_update_chs() {
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sim_debug(EXECUTE_MSG, &id_dev,
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">>> id_update_chs(): id_esn=%02x id_etn=%02x\n",
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id_esn, id_etn);
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if (id_lsn++ >= id_esn) {
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sim_debug(EXECUTE_MSG, &id_dev,
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">>> id_update_chs(): id_lsn reset to 0. id_lhn is %02x\n",
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id_lhn);
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id_lsn = 0;
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if (id_lhn++ >= id_etn) {
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sim_debug(EXECUTE_MSG, &id_dev,
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">>> id_update_chs(): id_lhn reset to 0. id_lcnl is %02x\n",
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id_lcnl);
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id_lhn = 0;
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if (id_lcnl == 0xff) {
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id_lcnl = 0;
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id_lcnh++;
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} else {
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id_lcnl++;
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}
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}
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}
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}
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uint32 id_read(uint32 pa, size_t size) {
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uint8 reg;
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uint16 cyl;
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t_lba lba;
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uint32 data;
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t_seccnt sectsread;
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reg = (uint8) (pa - IDBASE);
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switch(reg) {
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case ID_DATA_REG: /* Data Buffer Register */
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/* If we're in a DMA transfer, we need to be reading data from
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* the disk buffer. Otherwise, we're reading from the FIFO. */
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if (id_drq) {
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/* If the drive isn't attached, there's really nothing we
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can do. */
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if ((id_sel_unit->flags & UNIT_ATT) == 0) {
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id_end_rw(ID_EST_NR);
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return 0;
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}
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/* We could be in one of these commands:
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* - Read Data
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* - Read ID
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*/
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if (CMD_NUM == ID_CMD_RDATA) {
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/* If we're still in DRQ but we've read all our sectors,
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* that's an error state. */
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if (id_scnt == 0) {
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sim_debug(READ_MSG, &id_dev,
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"[%08x] ERROR\tid_scnt = 0 but still in dma\n",
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R[NUM_PC]);
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id_end_rw(ID_EST_OVR);
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return 0;
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}
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/* If the disk buffer is empty, fill it. */
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if (id_buf_ptr == 0 || id_buf_ptr >= ID_SEC_SIZE) {
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/* It's time to read a new sector into our sector buf */
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id_buf_ptr = 0;
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cyl = (uint16) (((uint16)id_lcnh << 8)|(uint16)id_lcnl);
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id_cyl[UNIT_NUM] = cyl;
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lba = id_lba(cyl, id_lhn, id_lsn);
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if (sim_disk_rdsect(id_sel_unit, lba, id_buf, §sread, 1) == SCPE_OK) {
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if (sectsread !=1) {
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sim_debug(READ_MSG, &id_dev,
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"[%08x]\tERROR: ASKED TO READ ONE SECTOR, READ: %d\n",
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R[NUM_PC], sectsread);
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}
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sim_debug(READ_MSG, &id_dev,
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"[%08x] \tRDATA\tCYL=%d PHN=%d LCNH=%02x "
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"LCNL=%02x LHN=%d LSN=%d SCNT=%d LBA=%04x\n",
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R[NUM_PC], cyl, id_phn, id_lcnh, id_lcnl,
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id_lhn, id_lsn, id_scnt-1, lba);
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id_update_chs();
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} else {
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/* Uh-oh! */
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sim_debug(READ_MSG, &id_dev,
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"[%08x]\tRDATA READ ERROR. Failure from sim_disk_rdsect!\n",
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R[NUM_PC]);
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id_end_rw(ID_EST_DER);
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return 0;
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}
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}
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data = id_buf[id_buf_ptr++];
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sim_debug(READ_MSG, &id_dev,
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"[%08x]\tSECTOR DATA\t%02x\t(%c)\n",
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R[NUM_PC], data, (data >= 0x20 && data < 0x7f) ? data : '.');
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/* Done with this current sector, update id_scnt */
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if (id_buf_ptr >= ID_SEC_SIZE) {
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if (--id_scnt == 0) {
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id_end_rw(0);
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}
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}
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} else if (CMD_NUM == ID_CMD_RID) {
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/* We have to return the ID bytes for the current C/H/S */
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if (id_idfield_ptr == 0 || id_idfield_ptr >= ID_IDFIELD_LEN) {
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id_idfield[0] = ~(id_lcnh);
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id_idfield[1] = id_lcnl;
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id_idfield[2] = id_lhn;
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id_idfield[3] = id_lsn;
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id_idfield_ptr = 0;
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}
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data = id_idfield[id_idfield_ptr++];
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sim_debug(READ_MSG, &id_dev,
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"[%08x]\tID DATA\t%02x\n",
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R[NUM_PC], data);
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if (id_idfield_ptr >= ID_IDFIELD_LEN) {
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if (id_scnt-- > 0) {
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/* Another sector to ID */
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id_idfield_ptr = 0;
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} else {
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/* All done, set return codes */
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id_dpr = 0;
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id_dpw = 0;
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id_data[0] = 0;
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id_data[1] = id_scnt;
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}
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}
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} else {
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assert(0); // cmd not Read Data or Read ID
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}
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return data;
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} else {
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if (id_dpr < ID_FIFO_LEN) {
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sim_debug(READ_MSG, &id_dev,
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"[%08x]\tDATA\t%02x\n",
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R[NUM_PC], id_data[id_dpr]);
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return id_data[id_dpr++];
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} else {
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sim_debug(READ_MSG, &id_dev,
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"[%08x] ERROR\tFIFO OVERRUN\n",
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R[NUM_PC]);
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return 0;
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}
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}
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break;
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case ID_CMD_STAT_REG: /* Status Register */
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sim_debug(READ_MSG, &id_dev,
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"[%08x]\tSTATUS\t%02x\n",
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R[NUM_PC], id_status|id_drq);
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return id_status|(id_drq ? 1u : 0);
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}
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sim_debug(READ_MSG, &id_dev,
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"[%08x] Read of unsuported register %x\n",
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R[NUM_PC], id_status);
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return 0;
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}
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void id_write(uint32 pa, uint32 val, size_t size)
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{
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uint8 reg;
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uint16 cyl;
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t_lba lba;
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t_seccnt sectswritten;
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reg = (uint8) (pa - IDBASE);
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switch(reg) {
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case ID_DATA_REG:
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/* If we're in a DMA transfer, we need to be writing data to
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* the disk buffer. Otherwise, we're writing to the FIFO. */
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if (id_drq) {
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/* If we're still in DRQ but we've written all our sectors,
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* that's an error state. */
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if (id_scnt == 0) {
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sim_debug(WRITE_MSG, &id_dev,
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"[%08x] ERROR\tid_scnt = 0 but still in dma\n",
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R[NUM_PC]);
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id_end_rw(ID_EST_OVR);
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return;
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}
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/* Write to the disk buffer */
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if (id_buf_ptr < ID_SEC_SIZE) {
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sim_debug(WRITE_MSG, &id_dev,
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"[%08x]\tSECTOR DATA\t%02x\t(%c)\n",
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R[NUM_PC], val, (val >= 0x20 && val < 0x7f) ? val : '.');
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id_buf[id_buf_ptr++] = (uint8)(val & 0xff);
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} else {
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sim_debug(WRITE_MSG, &id_dev,
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"[%08x] ERROR\tWDATA OVERRUN\n",
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R[NUM_PC]);
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id_end_rw(ID_EST_OVR);
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return;
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}
|
|
|
|
/* If we've hit the end of a sector, flush it */
|
|
if (id_buf_ptr >= ID_SEC_SIZE) {
|
|
/* It's time to start the next sector, and flush the old. */
|
|
id_buf_ptr = 0;
|
|
cyl = (uint16) (((uint16) id_lcnh << 8)|(uint16)id_lcnl);
|
|
id_cyl[UNIT_NUM] = cyl;
|
|
lba = id_lba(cyl, id_lhn, id_lsn);
|
|
if (sim_disk_wrsect(id_sel_unit, lba, id_buf, §swritten, 1) == SCPE_OK) {
|
|
if (sectswritten !=1) {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tERROR: ASKED TO WRITE ONE SECTOR, WROTE: %d\n",
|
|
R[NUM_PC], sectswritten);
|
|
}
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tWDATA\tCYL=%d PHN=%d LCNH=%02x "
|
|
"LCNL=%02x LHN=%d LSN=%d SCNT=%d LBA=%04x\n",
|
|
R[NUM_PC], cyl, id_phn, id_lcnh, id_lcnl,
|
|
id_lhn, id_lsn, id_scnt, lba);
|
|
id_update_chs();
|
|
if (--id_scnt == 0) {
|
|
id_end_rw(0);
|
|
}
|
|
} else {
|
|
/* Uh-oh! */
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x] ERROR\tWDATA WRITE ERROR. lba=%04x\n",
|
|
R[NUM_PC], lba);
|
|
id_end_rw(ID_EST_DER);
|
|
return;
|
|
}
|
|
}
|
|
|
|
return;
|
|
} else {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tDATA\t%02x\n",
|
|
R[NUM_PC], val);
|
|
|
|
if (id_dpw < ID_FIFO_LEN) {
|
|
id_data[id_dpw++] = (uint8) val;
|
|
} else {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x] ERROR\tFIFO OVERRUN\n",
|
|
R[NUM_PC]);
|
|
}
|
|
}
|
|
return;
|
|
case ID_CMD_STAT_REG:
|
|
id_handle_command((uint8) val);
|
|
return;
|
|
default:
|
|
return;
|
|
}
|
|
}
|
|
|
|
void id_handle_command(uint8 val)
|
|
{
|
|
uint8 cmd, aux_cmd, sec, pattern;
|
|
uint16 cyl;
|
|
uint32 time;
|
|
t_lba lba;
|
|
|
|
/* Save the full command byte */
|
|
id_cmd = val;
|
|
|
|
/* Reset the FIFO pointer */
|
|
id_dpr = 0;
|
|
id_dpw = 0;
|
|
|
|
/* Writing a command always de-asserts INT output, UNLESS
|
|
the SRQ bit is set. */
|
|
if ((id_status & ID_STAT_SRQ) != ID_STAT_SRQ) {
|
|
id_irq = FALSE;
|
|
}
|
|
|
|
/* Is this an aux command or a full command? */
|
|
if ((val & 0xf0) == 0) {
|
|
aux_cmd = val & 0x0f;
|
|
id_status &= ~(ID_STAT_CB);
|
|
|
|
if (aux_cmd & ID_AUX_CLCE) {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x] \tCOMMAND\t%02x\tAUX:CLCE\n",
|
|
R[NUM_PC], val);
|
|
id_status &= ~(ID_STAT_CEL|ID_STAT_CEH);
|
|
sim_cancel(id_sel_unit);
|
|
}
|
|
|
|
if (aux_cmd & ID_AUX_HSRQ) {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x] \tCOMMAND\t%02x\tAUX:HSRQ\n",
|
|
R[NUM_PC], val);
|
|
id_status &= ~ID_STAT_SRQ;
|
|
sim_cancel(id_sel_unit);
|
|
}
|
|
|
|
if (aux_cmd & ID_AUX_CLB) {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tAUX:CLBUF\n",
|
|
R[NUM_PC], val);
|
|
id_clear_fifo();
|
|
}
|
|
|
|
if (aux_cmd & ID_AUX_RST) {
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tAUX:RESET\n",
|
|
R[NUM_PC], val);
|
|
sim_cancel(id_sel_unit);
|
|
id_clear_fifo();
|
|
}
|
|
|
|
/* Just return early */
|
|
return;
|
|
}
|
|
|
|
/* Now that we know it's not an aux command, get the unit number
|
|
this command is for */
|
|
id_sel_unit = &id_unit[UNIT_NUM];
|
|
|
|
cmd = (id_cmd >> 4) & 0xf;
|
|
|
|
/* If this command is anything BUT a sense interrupt status, set
|
|
* the seek flag to false.
|
|
*/
|
|
if (cmd != ID_CMD_SIS) {
|
|
id_seek_sis = FALSE;
|
|
}
|
|
|
|
id_status = ID_STAT_CB;
|
|
|
|
switch(cmd) {
|
|
case ID_CMD_SIS:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tSense Int. Status - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_activate(DELAY_US(ID_SIS_WAIT));
|
|
break;
|
|
case ID_CMD_SPEC:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tSpecify - %d - ETN=%02x ESN=%02x\n",
|
|
R[NUM_PC], val, UNIT_NUM, id_data[3], id_data[4]);
|
|
id_dtlh[UNIT_NUM] = id_data[1];
|
|
id_etn = id_data[3];
|
|
id_esn = id_data[4];
|
|
id_activate(DELAY_US(ID_SPEC_WAIT));
|
|
break;
|
|
case ID_CMD_SUS:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tSense Unit Status - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_activate(DELAY_US(ID_SUS_WAIT));
|
|
break;
|
|
case ID_CMD_DERR:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tDetect Error - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_status |= ID_STAT_CEH;
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_RECAL:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tRecalibrate - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_cyl[UNIT_NUM] = 0;
|
|
time = id_cyl[UNIT_NUM];
|
|
id_activate(DELAY_US(ID_RECAL_WAIT + (time * ID_SEEK_WAIT)));
|
|
id_seek_sis = TRUE;
|
|
break;
|
|
case ID_CMD_SEEK:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tSeek - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_lcnh = id_data[0];
|
|
id_lcnl = id_data[1];
|
|
cyl = id_lcnh << 8 | id_lcnl;
|
|
time = (uint32) abs(id_cyl[UNIT_NUM] - cyl);
|
|
id_activate(DELAY_US(ID_SEEK_BASE + (ID_SEEK_WAIT * time)));
|
|
id_cyl[UNIT_NUM] = cyl;
|
|
id_seek_sis = TRUE;
|
|
break;
|
|
case ID_CMD_FMT:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tFormat - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
|
|
id_phn = id_data[0];
|
|
id_scnt = id_data[1];
|
|
pattern = id_data[2];
|
|
|
|
/* Format scnt sectors with the given pattern, if attached */
|
|
if (id_sel_unit->flags & UNIT_ATT) {
|
|
/* Formatting soft-sectored disks always begins at sector 0 */
|
|
sec = 0;
|
|
|
|
while (id_scnt-- > 0) {
|
|
/* Write one sector of pattern */
|
|
for (id_buf_ptr = 0; id_buf_ptr < ID_SEC_SIZE; id_buf_ptr++) {
|
|
id_buf[id_buf_ptr] = pattern;
|
|
}
|
|
lba = id_lba(id_cyl[UNIT_NUM], id_phn, sec++);
|
|
if (sim_disk_wrsect(id_sel_unit, lba, id_buf, NULL, 1) == SCPE_OK) {
|
|
sim_debug(EXECUTE_MSG, &id_dev,
|
|
"[%08x]\tFORMAT: PHN=%d SCNT=%d PAT=%02x LBA=%04x\n",
|
|
R[NUM_PC], id_phn, id_scnt, pattern, lba);
|
|
} else {
|
|
sim_debug(EXECUTE_MSG, &id_dev,
|
|
"[%08x]\tFORMAT FAILED! PHN=%d SCNT=%d PAT=%02x LBA=%04x\n",
|
|
R[NUM_PC], id_phn, id_scnt, pattern, lba);
|
|
break;
|
|
}
|
|
}
|
|
|
|
id_data[0] = 0;
|
|
} else {
|
|
/* Not attached */
|
|
id_data[0] = ID_EST_NR;
|
|
}
|
|
|
|
id_data[1] = id_scnt;
|
|
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_VID:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tVerify ID - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_data[0] = 0;
|
|
id_data[1] = 0x05; /* What do we put here? */
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_RID:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tRead ID - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
if (id_sel_unit->flags & UNIT_ATT) {
|
|
id_drq = TRUE;
|
|
|
|
/* Grab our arguments */
|
|
id_phn = id_data[0];
|
|
id_scnt = id_data[1];
|
|
|
|
/* Compute logical values used by ID verification */
|
|
id_lhn = id_phn;
|
|
id_lsn = 0;
|
|
} else {
|
|
sim_debug(EXECUTE_MSG, &id_dev,
|
|
"[%08x]\tUNIT %d NOT ATTACHED, CANNOT READ ID.\n",
|
|
R[NUM_PC], UNIT_NUM);
|
|
}
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_RDIAG:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tRead Diag - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_RDATA:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tRead Data - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
if (id_sel_unit->flags & UNIT_ATT) {
|
|
id_drq = TRUE;
|
|
id_buf_ptr = 0;
|
|
|
|
/* Grab our arguments */
|
|
id_phn = id_data[0];
|
|
id_lcnh = ~(id_data[1]);
|
|
id_lcnl = id_data[2];
|
|
id_lhn = id_data[3];
|
|
id_lsn = id_data[4];
|
|
id_scnt = id_data[5];
|
|
} else {
|
|
sim_debug(EXECUTE_MSG, &id_dev,
|
|
"[%08x]\tUNIT %d NOT ATTACHED, CANNOT READ DATA.\n",
|
|
R[NUM_PC], UNIT_NUM);
|
|
}
|
|
|
|
time = (uint32) abs(id_cyl[UNIT_NUM] - ((id_lcnh<<8)|id_lcnl));
|
|
if (time == 0) {
|
|
time++;
|
|
}
|
|
time = time * ID_SEEK_WAIT;
|
|
id_activate(DELAY_US(time + ID_RW_WAIT));
|
|
break;
|
|
case ID_CMD_CHECK:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tCheck - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_SCAN:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tScan - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_VDATA:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tVerify Data - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
id_activate(DELAY_US(ID_CMD_WAIT));
|
|
break;
|
|
case ID_CMD_WDATA:
|
|
sim_debug(WRITE_MSG, &id_dev,
|
|
"[%08x]\tCOMMAND\t%02x\tWrite Data - %d\n",
|
|
R[NUM_PC], val, UNIT_NUM);
|
|
if (id_sel_unit->flags & UNIT_ATT) {
|
|
id_drq = TRUE;
|
|
id_buf_ptr = 0;
|
|
|
|
/* Grab our arguments */
|
|
id_phn = id_data[0];
|
|
id_lcnh = ~(id_data[1]);
|
|
id_lcnl = id_data[2];
|
|
id_lhn = id_data[3];
|
|
id_lsn = id_data[4];
|
|
id_scnt = id_data[5];
|
|
} else {
|
|
sim_debug(EXECUTE_MSG, &id_dev,
|
|
"[%08x]\tUNIT %d NOT ATTACHED, CANNOT WRITE.\n",
|
|
R[NUM_PC], UNIT_NUM);
|
|
}
|
|
time = (uint32) abs(id_cyl[UNIT_NUM] - ((id_lcnh<<8)|id_lcnl));
|
|
if (time == 0) {
|
|
time++;
|
|
}
|
|
time = time * ID_SEEK_WAIT;
|
|
id_activate(DELAY_US(time + ID_RW_WAIT));
|
|
break;
|
|
}
|
|
}
|
|
|
|
void id_drq_handled()
|
|
{
|
|
id_status &= ~ID_STAT_DRQ;
|
|
id_drq = FALSE;
|
|
}
|
|
|
|
CONST char *id_description(DEVICE *dptr)
|
|
{
|
|
return "72MB MFM Hard Disk";
|
|
}
|
|
|
|
t_stat id_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf(st, "71MB MFM Integrated Hard Disk (ID)\n\n");
|
|
fprintf(st,
|
|
"The ID controller implements the integrated MFM hard disk controller\n"
|
|
"of the 3B2/400. Up to four drives are supported on a single controller.\n");
|
|
return SCPE_OK;
|
|
}
|