0a33758e47
The B5500 simulator supports the following peripherals.
Two CPUs with between 4K and 32K of memory. The second CPU can be
enabled with "set cpu1 enable". "set cpu1 disable" disables the
second CPU.
Up to 4 floating IO channels. Individual channels can be enabled with
"set io# enable", or "set io# disable".
There are two card readers. The second reader is disabled by default.
There is one Card Punch.
The Card reader and Card Punch support the following options:
set cr format=
auto - will automatically determine the format based on the
text it recieves.
text Text based cards. Tabs are converted to the correct
number of spaces. A record of
~raw octal will enter a binary card.
~eor will enter a 7/8/9 punch in column 1.
~eof will enter a 6/7/9 punch in column 1.
~eoi will enter a 6/7/8/9 punch in column 1.
~~ will enter a ~ as the first character.
bin Binary Card format:
Each record 160 characters.
First characters 6789----
Second character 21012345
111
Top 4 bits of second character are 0.
It is unlikely that any other format could
look like this.
bcd BCD Format:
Each record variable length (80 chars or less).
Record mark has bit 7 set.
Bit 6 is even parity.
Bits 5-0 are character.
cbn CBN Format:
Each record 160 charaters.
First char has bit 7 set. Rest set to 0.
Bit 6 is odd parity.
Bit 5-0 of first character are top 6 bits
of card.
Bit 5-0 of second character are lower 6 bits
of card.
For punch format of auto if the card can't be converted to text it is
output as a raw record.
There are two line printers, the second one is disabled by default. The LP
supports the option "set lp# linesperpage=#" which determines when the
printer will force out a page break.
There are up to 16 mag tape drives, the format is controlled by the standard
simh format control for tapes. These are 6 bit tapes, 1 character per record
with parity. Units 8-16 are disabled by default.
There are up to two drum units DR0 and DR1. These can either be attached
to a file or set to AUXMEM. Setting to AUXMEM causes them to exist only
during the given simh run. Setting back to DRUM will clear whatever was
stored on the drum. To enable use of DRUM on XV the following options should
be turned on "DRA,DRB,CODEOLAY,DATAOLAY". MCP will then use the drum as a
overlay device instead of the disk system.
Disks can be attached to the various ESU's, ESU0-9 are on DKA by default,
ESU10-19 are on DKB. If "set dk1 dfx" is set, then ESU10-19 are not used and
the disks are shared by both DKA and DKB. To use more then 10 ESU's in a non
shared mode, a new version of MCP must be created. MCP must be compiled with
DFX option set to false. For MCP XV DKBNODFX must also be set to true. ESU units
can be set to MODI or MODIB. MODIB will double the size of the drive.
The DTC can be attached to a telnet port with "attach dtc #" to enable dialup
access to the sim.
The loader card for the card reader is:
~raw0104441100204231524012004000004444550211002041317700000000000024045303040243
00050000006501004131011041310055005500000062005042310000006600304231000000720010
42310000007675610165001002310010413100040107202500440106202533554061256520252265
20251765202514655355536117650000004401062025155522610165225572610465044101160500
4131
This card should be all in one line.
795 lines
21 KiB
C
795 lines
21 KiB
C
/* B5500_io.c: Burroughs 5500 I/O System.
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Copyright (c) 2016, Richard Cornwell
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "b5500_defs.h"
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#define EOR 1
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#define USEGM 2
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t_stat chan_reset(DEVICE * dptr);
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/* Channel data structures
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chan_dev Channel device descriptor
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chan_unit Channel unit descriptor
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chan_reg Channel register list
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chan_mod Channel modifiers list
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*/
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t_uint64 D[NUM_CHAN]; /* Current I/O instruction */
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uint8 CC[NUM_CHAN]; /* Channel character count */
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t_uint64 W[NUM_CHAN]; /* Assembly register */
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uint8 status[NUM_CHAN]; /* Channel status */
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uint8 cstatus; /* Active status */
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#define WC(x) (uint16)(((x) & DEV_WC) >> DEV_WC_V)
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#define toWC(x) (((t_uint64)(x) << DEV_WC_V) & DEV_WC)
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UNIT chan_unit[] = {
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/* Normal channels */
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{UDATA(NULL,UNIT_DISABLE,0)},/* A */
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{UDATA(NULL,UNIT_DISABLE,0)},/* B */
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{UDATA(NULL,UNIT_DISABLE,0)},/* C */
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{UDATA(NULL,UNIT_DISABLE,0)},/* D */
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};
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REG chan_reg[] = {
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{BRDATA(D, D, 8, 48, NUM_CHAN), REG_RO},
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{BRDATA(CC, CC, 7, 6, NUM_CHAN), REG_RO},
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{BRDATA(W, W, 8, 48, NUM_CHAN), REG_RO},
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{NULL}
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};
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/* Simulator debug controls */
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DEBTAB chn_debug[] = {
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{"CHANNEL", DEBUG_CHAN},
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{"DETAIL", DEBUG_DETAIL},
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{"DATA", DEBUG_DATA},
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{"CH0", 0x0100 << 0},
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{"CH1", 0x0100 << 1},
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{"CH2", 0x0100 << 2},
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{"CH3", 0x0100 << 3},
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{0, 0}
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};
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DEVICE chan_dev = {
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"IO", chan_unit, chan_reg, NULL,
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NUM_CHAN, 10, 18, 1, 10, 44,
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NULL, NULL, &chan_reset, NULL, NULL, NULL,
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NULL, DEV_DEBUG, 0, chn_debug
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};
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t_stat
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chan_reset(DEVICE * dptr)
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{
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int i;
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int j = 1;
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cstatus = 0;
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/* Clear channel assignment */
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for (i = 0; i < NUM_CHAN; i++) {
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status[i] = 0;
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D[i] = 0;
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W[i] = 0;
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CC[i] = 0;
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if (chan_unit[i].flags & UNIT_DIS)
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cstatus |= j;
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j <<= 1;
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}
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return SCPE_OK;
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}
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/* Boot from given device */
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t_stat
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chan_boot(t_uint64 desc)
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{
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M[020] = desc;
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M[010] = 020;
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loading = 1;
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start_io();
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return SCPE_OK;
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}
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int
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find_chan() {
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int i;
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int chan;
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i = 1;
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for(chan = 0; chan < NUM_CHAN; chan++) {
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if ((cstatus & i) == 0)
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break;
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i <<= 1;
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}
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if (chan == NUM_CHAN) {
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return 0;
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}
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return chan + 1;
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}
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void
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chan_release(int chan) {
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cstatus &= ~(1 << chan);
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}
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int
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chan_advance(int chan) {
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uint16 addr = (uint16)(D[chan] & CORE);
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if (D[chan] & DEV_WCFLG) {
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uint16 wc = WC(D[chan]);
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if (wc == 0) {
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status[chan] |= EOR;
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return 1;
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}
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D[chan] &= ~DEV_WC;
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D[chan] |= toWC(wc-1);
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}
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if (addr > MEMSIZE) {
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D[chan] |= DEV_MEMERR;
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status[chan] |= EOR;
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return 1;
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}
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W[chan] = M[addr];
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D[chan] &= ~CORE;
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if (D[chan] & DEV_BACK)
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D[chan] |= (t_uint64)((addr - 1) & CORE);
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else
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D[chan] |= (t_uint64)((addr + 1) & CORE);
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CC[chan] = 0;
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return 0;
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}
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void
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start_io() {
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int i;
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int chan;
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t_stat r;
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uint16 dev;
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uint16 cmd;
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uint16 wc;
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int addr;
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chan = find_chan();
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addr = M[010] & CORE;
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if (chan == 0) {
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IAR |= IRQ_1;
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return;
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}
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chan--;
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i = 1 << chan;
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sim_debug(DEBUG_DETAIL, &chan_dev, "strtio(%016llo %d)\n", M[addr], chan);
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D[chan] = M[addr] & D_MASK;
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CC[chan] = 0;
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W[chan] = 0;
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dev = (uint16)((D[chan] & DEVMASK) >> DEV_V);
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cmd = (uint16)((D[chan] & DEV_CMD) >> DEV_CMD_V);
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wc = WC(D[chan]);
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D[chan] &= ~DEV_RESULT;
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status[chan] = 0;
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if (dev & 1) {
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#if (NUM_DEVS_MT > 0)
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status[chan] = USEGM;
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r = mt_cmd(cmd, dev, chan, &wc);
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#else
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r = SCPE_UNATT;
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#endif
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} else {
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switch(dev) {
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#if (NUM_DEVS_DR > 0)
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case DRUM1_DEV:
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case DRUM2_DEV:
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r = drm_cmd(cmd, dev, chan, &wc, (uint8)((M[addr] & PRESENT)!=0));
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break;
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#endif
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#if (NUM_DEVS_CDR > 0) | (NUM_DEVS_CDP > 0)
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case CARD1_DEV:
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case CARD2_DEV:
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r = card_cmd(cmd, dev, chan, &wc);
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break;
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#endif
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#if (NUM_DEVS_DSK > 0)
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case DSK1_DEV:
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case DSK2_DEV:
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/* Need to pass word count to identify interrogates */
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r = dsk_cmd(cmd, dev, chan, &wc);
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break;
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#endif
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#if (NUM_DEVS_DTC > 0)
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case DTC_DEV:
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status[chan] = USEGM;
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/* Word count is TTU and BUF number */
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r = dtc_cmd(cmd, dev, chan, &wc);
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if (r == SCPE_OK)
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D[chan] &= ~DEV_WC;
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D[chan] &= ~(DEV_BIN|DEV_WCFLG);
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wc = 0;
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break;
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#endif
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#if (NUM_DEVS_LPR > 0)
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case PRT1_DEV:
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case PRT2_DEV:
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r = lpr_cmd(cmd, dev, chan, &wc);
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if (r == SCPE_OK)
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D[chan] &= ~DEV_BACK; /* Clear this bit, since printer
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uses this to determine 120/132
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char line */
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break;
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#endif
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#if (NUM_DEVS_CON > 0)
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case SPO_DEV:
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status[chan] = USEGM;
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r = con_cmd(cmd, dev, chan, &wc);
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break;
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#endif
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default:
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r = SCPE_UNATT;
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break;
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}
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}
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if (wc != 0) {
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D[chan] &= ~DEV_WC;
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D[chan] |= toWC(wc) | DEV_WCFLG;
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}
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switch(r) {
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case SCPE_OK:
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cstatus |= i;
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return;
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case SCPE_NXDEV:
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case SCPE_UNATT:
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D[chan] |= DEV_NOTRDY;
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break;
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case SCPE_BUSY:
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D[chan] |= DEV_BUSY;
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break;
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case SCPE_EOF:
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D[chan] |= DEV_EOF;
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break;
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}
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chan_set_end(chan);
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}
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void
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chan_set_end(int chan) {
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uint16 dev;
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dev = (uint16)((D[chan] & DEVMASK) >> DEV_V);
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/* Set character count if reading and tape */
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if ((dev & 1) && (D[chan] & DEV_IORD)) {
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D[chan] &= ~((7LL)<<DEV_WC_V);
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/* If not data transfered, return zero code */
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if ((D[chan] & DEV_BACK) != 0 &&
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(status[chan] & EOR) != 0)
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D[chan] |= ((t_uint64)((7-CC[chan]) & 07)) << DEV_WC_V;
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else
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D[chan] |= ((t_uint64)(CC[chan] & 07)) << DEV_WC_V;
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}
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/* Flush last buffer if short write */
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if ((D[chan] & DEV_IORD) && CC[chan] != 0) {
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uint16 addr = (uint16)(D[chan] & CORE);
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if ((D[chan] & (DEV_BIN|DEV_WCFLG)) == 0) {
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/* Insert group mark */
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if (D[chan] & DEV_BACK) {
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W[chan] |= (t_uint64)037LL << ((CC[chan]) * 6);
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CC[chan]++;
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} else {
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while(CC[chan] != 8) {
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W[chan] |= 037LL << ((7 - CC[chan]) * 6);
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CC[chan]++;
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}
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}
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}
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M[addr] = W[chan];
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sim_debug(DEBUG_DATA, &chan_dev, "write(%d, %05o, %016llo)f\n",
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chan, addr, W[chan]);
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(void)chan_advance(chan);
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}
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M[014+chan] = D[chan];
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if (loading == 0)
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IAR |= IRQ_5 << chan;
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else
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loading = 0;
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sim_debug(DEBUG_DETAIL, &chan_dev, "endio (%016llo %o)\n", D[chan], chan);
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}
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void
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chan_set_eof(int chan) {
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D[chan] |= DEV_EOF;
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}
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void
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chan_set_parity(int chan) {
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D[chan] |= DEV_PARITY;
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}
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void
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chan_set_error(int chan) {
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D[chan] |= DEV_ERROR;
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}
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void
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chan_set_wcflg(int chan) {
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D[chan] |= DEV_WCFLG;
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}
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void
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chan_set_read(int chan) {
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D[chan] |= DEV_IORD;
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}
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void
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chan_set_gm(int chan) {
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D[chan] |= DEV_BACK;
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}
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void
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chan_set_notrdy(int chan) {
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D[chan] |= DEV_NOTRDY;
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chan_set_end(chan);
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}
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void
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chan_set_eot(int chan) {
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D[chan] &= ~DEV_WC;
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D[chan] |= DEV_EOT;
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}
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void
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chan_set_bot(int chan) {
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D[chan] &= ~DEV_WC;
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D[chan] |= DEV_BOT;
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}
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void
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chan_set_blank(int chan) {
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D[chan] &= ~DEV_WC;
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D[chan] |= DEV_BLANK;
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}
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void
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chan_set_wrp(int chan) {
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D[chan] |= DEV_ERROR|DEV_MEMERR;
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}
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void
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chan_set_wc(int chan, uint16 wc) {
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D[chan] &= ~DEV_WC;
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D[chan] |= toWC(wc);
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}
|
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|
||
|
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/*
|
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Internal BCD
|
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00 0000 00 1010 0000 -> 1010
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00 0001 00 0001
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00 0010 00 0010
|
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00 0011 00 0011
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00 0100 00 0100
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00 0101 00 0101
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00 0110 00 0110
|
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00 0111 00 0111
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00 1000 00 1000
|
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00 1001 00 1001
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00 1010 00 1011 1010 -> 1011
|
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00 1011 00 1100 1011 -> 1100
|
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00 1100 00 0000 1100 -> 0000
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00 1101 00 1101
|
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00 1110 00 1110
|
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00 1111 00 1111
|
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01 0000 11 1010 0000 -> 1010 10
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01 0001 11 0001 1
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01 0010 11 0010 2
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01 0011 11 0011 3
|
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01 0100 11 0100
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01 0101 11 0101
|
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01 0110 11 0110
|
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01 0111 11 0111
|
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01 1000 11 1000 8
|
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01 1001 11 1001 9
|
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01 1010 11 1011 1010 -> 1011 10
|
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01 1011 11 1100 1011 -> 1100 11
|
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01 1100 11 0000 1100 -> 0000 12
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01 1101 11 1101 13
|
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01 1110 11 1110 14
|
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01 1111 11 1111 15
|
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10 0000 10 1010 0000 -> 1010
|
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10 0001 10 0001
|
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10 0010 10 0010
|
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10 0011 10 0011
|
||
10 0100 10 0100
|
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10 0101 10 0101
|
||
10 0110 10 0110
|
||
10 0111 10 0111
|
||
10 1000 10 1000
|
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10 1001 10 1001
|
||
10 1010 10 1011 1010 -> 1011
|
||
10 1011 10 1100 1011 -> 1100
|
||
10 1100 10 0000 1100 -> 0000
|
||
10 1101 10 1101
|
||
10 1110 10 1110
|
||
10 1111 10 1111
|
||
11 0000 01 0000
|
||
11 0001 01 0001
|
||
11 0010 01 0010
|
||
11 0011 01 0011
|
||
11 0100 01 0100
|
||
11 0101 01 0101
|
||
11 0110 01 0110
|
||
11 0111 01 0111
|
||
11 1000 01 1000
|
||
11 1001 01 1001
|
||
11 1010 01 1011 1010 -> 1011
|
||
11 1011 01 1100 1011 -> 1100
|
||
11 1100 01 1010 1100 -> 1010
|
||
11 1101 01 1101
|
||
11 1110 01 1110
|
||
11 1111 01 1111 */
|
||
|
||
/* returns 1 when channel can take no more characters.
|
||
A return of 1 indicates that the character was not
|
||
processed.
|
||
*/
|
||
int chan_write_char(int chan, uint8 *ch, int flags) {
|
||
uint8 c;
|
||
|
||
if (status[chan] & EOR)
|
||
return 1;
|
||
|
||
if (D[chan] & DEV_INHTRF) {
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
|
||
/* Check if first word */
|
||
if (CC[chan] == 0) {
|
||
uint16 wc = WC(D[chan]);
|
||
|
||
if (D[chan] & DEV_WCFLG && wc == 0) {
|
||
sim_debug(DEBUG_DATA, &chan_dev, "zerowc(%d)\n", chan);
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
W[chan] = 0;
|
||
}
|
||
|
||
c = *ch & 077;
|
||
if ((D[chan] & DEV_BIN) == 0) {
|
||
/* Translate BCL to BCD */
|
||
uint8 cx = c & 060;
|
||
|
||
c &= 017;
|
||
switch(c) {
|
||
case 0:
|
||
/* 11-0 -> 01 C */
|
||
/* 10-0 -> 10 C */
|
||
/* 01-0 -> 11 0 */
|
||
/* 00-0 -> 00 C */
|
||
if (cx != 020)
|
||
c = 0xc;
|
||
break;
|
||
case 1:
|
||
case 2:
|
||
case 3:
|
||
case 4:
|
||
case 5:
|
||
case 6:
|
||
case 7:
|
||
case 8:
|
||
case 9:
|
||
case 0xd:
|
||
case 0xe:
|
||
case 0xf:
|
||
break;
|
||
case 0xa:
|
||
/* 11-A -> 01 0 */
|
||
/* 10-A -> 10 0 */
|
||
/* 01-A -> 11 C */
|
||
/* 00-A -> 00 0 */
|
||
if (cx == 020)
|
||
c = 0xc;
|
||
else
|
||
c = 0;
|
||
break;
|
||
case 0xb:
|
||
c = 0xa;
|
||
break;
|
||
case 0xc:
|
||
c = 0xb;
|
||
break;
|
||
}
|
||
c |= cx ^ ((cx & 020)<<1);
|
||
}
|
||
|
||
if (D[chan] & DEV_BACK)
|
||
W[chan] |= ((t_uint64)c) << ((CC[chan]) * 6);
|
||
else
|
||
W[chan] |= ((t_uint64)c) << ((7 - CC[chan]) * 6);
|
||
CC[chan]++;
|
||
|
||
if (CC[chan] == 8) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
|
||
M[addr] = W[chan];
|
||
sim_debug(DEBUG_DATA, &chan_dev, "write(%d, %05o, %016llo)\n",
|
||
chan, addr, W[chan]);
|
||
|
||
if (chan_advance(chan))
|
||
return 1;
|
||
}
|
||
if (flags) {
|
||
if ((D[chan] & (DEV_BIN|DEV_WCFLG)) == 0) {
|
||
/* Insert group mark */
|
||
if (D[chan] & DEV_BACK) {
|
||
int i = CC[chan];
|
||
W[chan] |= (t_uint64)037LL << ((CC[chan]) * 6);
|
||
|
||
while(i < 8) {
|
||
W[chan] |= (t_uint64)014LL << (i * 6);
|
||
i++;
|
||
}
|
||
} else {
|
||
W[chan] |= 037LL << ((7 - CC[chan]) * 6);
|
||
}
|
||
CC[chan]++;
|
||
}
|
||
|
||
/* Flush last word */
|
||
if (CC[chan] != 0) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
|
||
M[addr] = W[chan];
|
||
sim_debug(DEBUG_DATA, &chan_dev, "write(%d, %05o, %016llo)\n",
|
||
chan, addr, W[chan]);
|
||
(void)chan_advance(chan);
|
||
}
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Returns 1 on last character. If it returns 1, the
|
||
character in ch is not valid. If flag is set to 1, then
|
||
this is the last character the device will request.
|
||
*/
|
||
int chan_read_char(int chan, uint8 *ch, int flags) {
|
||
uint8 c;
|
||
int gm;
|
||
|
||
if (status[chan] & EOR)
|
||
return 1;
|
||
|
||
if (D[chan] & DEV_INHTRF) {
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
|
||
if (CC[chan] == 0) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
if (chan_advance(chan))
|
||
return 1;
|
||
sim_debug(DEBUG_DATA, &chan_dev, "read(%d, %05o, %016llo)\n", chan,
|
||
addr, W[chan]);
|
||
}
|
||
|
||
if (D[chan] & DEV_BACK)
|
||
c = 077 & (W[chan] >> ((CC[chan]) * 6));
|
||
else
|
||
c = 077 & (W[chan] >> ((7 - CC[chan]) * 6));
|
||
gm = (c == 037);
|
||
CC[chan]++;
|
||
if (CC[chan] == 8) {
|
||
CC[chan] = 0;
|
||
}
|
||
if ((D[chan] & DEV_BIN) == 0) {
|
||
/* Translate BCD to BCL */
|
||
uint8 cx = c & 060;
|
||
c &= 017;
|
||
switch(c) {
|
||
case 0:
|
||
if (cx != 060)
|
||
c = 0xa;
|
||
break;
|
||
case 1:
|
||
case 2:
|
||
case 3:
|
||
case 4:
|
||
case 5:
|
||
case 6:
|
||
case 7:
|
||
case 8:
|
||
case 9:
|
||
case 0xd:
|
||
case 0xe:
|
||
case 0xf:
|
||
break;
|
||
case 0xa:
|
||
c = 0xb;
|
||
break;
|
||
case 0xb:
|
||
c = 0xc;
|
||
break;
|
||
case 0xc:
|
||
if (cx == 060)
|
||
c = 0xa;
|
||
else
|
||
c = 0;
|
||
break;
|
||
}
|
||
c |= cx ^ ((cx & 020)<<1);
|
||
}
|
||
*ch = c;
|
||
if ((status[chan] & USEGM) != 0 && (D[chan] & DEV_WCFLG) == 0 && gm) {
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
if (flags) {
|
||
status[chan] |= EOR;
|
||
}
|
||
return 0;
|
||
}
|
||
|
||
/* Same as chan_read_char, however we do not check word count
|
||
nor do we advance it.
|
||
*/
|
||
int chan_read_disk(int chan, uint8 *ch, int flags) {
|
||
uint8 c;
|
||
|
||
if (CC[chan] == 0) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
if (addr > MEMSIZE) {
|
||
D[chan] |= DEV_MEMERR;
|
||
return 1;
|
||
}
|
||
|
||
W[chan] = M[addr];
|
||
D[chan] &= ~CORE;
|
||
D[chan] |= (addr + 1) & CORE;
|
||
}
|
||
|
||
c = 077 & (W[chan] >> ((7 - CC[chan]) * 6));
|
||
CC[chan]++;
|
||
*ch = c;
|
||
if (CC[chan] == 8) {
|
||
CC[chan] = 0;
|
||
return 1;
|
||
}
|
||
return 0;
|
||
}
|
||
|
||
int
|
||
chan_advance_drum(int chan) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
uint16 wc = WC(D[chan]);
|
||
if (wc == 0) {
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
D[chan] &= ~DEV_WC;
|
||
D[chan] |= toWC(wc-1);
|
||
if (addr > MEMSIZE) {
|
||
D[chan] |= DEV_MEMERR;
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
|
||
W[chan] = M[addr];
|
||
D[chan] &= ~CORE;
|
||
D[chan] |= (addr + 1) & CORE;
|
||
CC[chan] = 0;
|
||
return 0;
|
||
}
|
||
|
||
/* returns 1 when channel can take no more characters.
|
||
A return of 1 indicates that the character was not
|
||
processed.
|
||
*/
|
||
int chan_write_drum(int chan, uint8 *ch, int flags) {
|
||
uint8 c;
|
||
|
||
if (status[chan] & EOR)
|
||
return 1;
|
||
|
||
/* Check if first word */
|
||
if (CC[chan] == 0) {
|
||
uint16 wc = WC(D[chan]);
|
||
|
||
if (wc == 0) {
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
W[chan] = 0;
|
||
}
|
||
|
||
c = *ch;
|
||
c &= 077;
|
||
|
||
W[chan] |= (t_uint64)c << ((7 - CC[chan]) * 6);
|
||
CC[chan]++;
|
||
|
||
if (CC[chan] == 8) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
|
||
M[addr] = W[chan];
|
||
if (chan_advance_drum(chan))
|
||
return 1;
|
||
}
|
||
if (flags) {
|
||
/* Flush last word */
|
||
if (CC[chan] != 0) {
|
||
uint16 addr = (uint16)(D[chan] & CORE);
|
||
|
||
M[addr] = W[chan];
|
||
(void)chan_advance_drum(chan);
|
||
}
|
||
status[chan] |= EOR;
|
||
return 1;
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Returns 1 on last character. If it returns 1, the
|
||
character in ch is not valid. If flag is set to 1, then
|
||
this is the last character the device will request.
|
||
*/
|
||
int chan_read_drum(int chan, uint8 *ch, int flags) {
|
||
uint8 c;
|
||
|
||
if (status[chan] & EOR)
|
||
return 1;
|
||
|
||
|
||
if (CC[chan] == 0) {
|
||
if (chan_advance_drum(chan))
|
||
return 1;
|
||
}
|
||
|
||
c = 077 & (W[chan] >> ((7 - CC[chan]) * 6));
|
||
CC[chan]++;
|
||
if (CC[chan] == 8) {
|
||
CC[chan] = 0;
|
||
}
|
||
*ch = c;
|
||
if (flags) {
|
||
status[chan] |= EOR;
|
||
}
|
||
return 0;
|
||
}
|
||
|