84bf5f4d14
This change updates the 3B2 README.md file, and fixes all line endings on 3B2 source files.
79 lines
3.4 KiB
C
79 lines
3.4 KiB
C
/* 3b2_mem.h: Memory Map Access Routines
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Copyright (c) 2021-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use, copy,
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modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Except as contained in this notice, the name of the author shall
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not be used in advertising or otherwise to promote the sale, use or
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other dealings in this Software without prior written authorization
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from the author.
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*/
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#ifndef _3B2_MEM_H_
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#define _3B2_MEM_H_
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#include "3b2_defs.h"
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#define IS_ROM(PA) ((PA) < ROM_SIZE)
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#define IS_RAM(PA) (((PA) >= PHYS_MEM_BASE) && ((PA) < (PHYS_MEM_BASE + MEM_SIZE)))
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#if defined(REV3)
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#define IS_IO(PA) (((PA >= IO_BOTTOM) && (PA < IO_TOP)) || \
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((PA >= CIO_BOTTOM) && (PA < CIO_TOP)) || \
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((PA >= VCACHE_BOTTOM) && (PA < VCACHE_TOP)) || \
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((PA >= BUB_BOTTOM) && (PA < BUB_TOP)))
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#else
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#define IS_IO(PA) (((PA >= IO_BOTTOM) && (PA < IO_TOP)) || \
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((PA >= CIO_BOTTOM) && (PA < CIO_TOP)))
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#endif
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#define MA_BUB3 0x100 /* BUBUS slot 3 master on fault */
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#define MA_BUB2 0x200 /* BUBUS slot 2 master on fault */
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#define MA_BUB1 0x400 /* BUBUS slot 1 master on fault */
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#define MA_CPU_BU 0x2000 /* CPU access BUBUS peripheral */
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#define MA_BUB0 0x4000 /* BUBUS slot 0 master on fault */
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#define MA_CPU_IO 0x8000 /* CPU accessing I/O peripheral */
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#define MA_IO_NLY 0x10000 /* IO Bus Master on fault */
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#define MA_IO_BM 0x80000 /* IO Bus Master or BUBUS was master on fault */
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#define BUS_PER 0 /* Read or Write is from peripheral */
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#define BUS_CPU 1 /* Read or Write is from CPU */
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uint32 pread_w(uint32 pa, uint8 src);
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void pwrite_w(uint32 pa, uint32 val, uint8 src);
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uint8 pread_b(uint32 pa, uint8 src);
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void pwrite_b(uint32 pa, uint8 val, uint8 src);
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void pwrite_b_rom(uint32 pa, uint8 val);
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uint16 pread_h(uint32 pa, uint8 src);
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void pwrite_h(uint32 pa, uint16 val, uint8 src);
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uint8 read_b(uint32 va, uint8 r_acc, uint8 src);
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uint16 read_h(uint32 va, uint8 r_acc, uint8 src);
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uint32 read_w(uint32 va, uint8 r_acc, uint8 src);
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void write_b(uint32 va, uint8 val, uint8 src);
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void write_h(uint32 va, uint16 val, uint8 src);
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void write_w(uint32 va, uint32 val, uint8 src);
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t_stat read_operand(uint32 va, uint8 *val);
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t_stat examine(uint32 va, uint8 *val);
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t_stat deposit(uint32 va, uint8 val);
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#endif /* _3B2_MEM_H_ */
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