9c4779c061
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
502 lines
16 KiB
C
502 lines
16 KiB
C
/* pdp11_stddev.c: PDP-11 standard I/O devices simulator
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Copyright (c) 1993-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tti,tto DL11 terminal input/output
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clk KW11L (and other) line frequency clock
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20-May-08 RMS Standardized clock delay at 1mips
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18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock
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29-Oct-06 RMS Synced keyboard and clock
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Added clock coscheduling support
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05-Jul-06 RMS Added UC only support for early DOS/RSTS
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22-Nov-05 RMS Revised for new terminal processing routines
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22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
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07-Jul-05 RMS Removed extraneous externs
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11-Oct-04 RMS Added clock model dependencies
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28-May-04 RMS Removed SET TTI CTRL-C
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29-Dec-03 RMS Added console backpressure support
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25-Apr-03 RMS Revised for extended file support
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01-Mar-03 RMS Added SET/SHOW CLOCK FREQ, SET TTI CTRL-C
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22-Nov-02 RMS Changed terminal default to 7B for UNIX
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01-Nov-02 RMS Added 7B/8B support to terminal
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29-Sep-02 RMS Added vector display support
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Split out paper tape
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Split DL11 dibs
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30-May-02 RMS Widened POS to 32b
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26-Jan-02 RMS Revised for multiple timers
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09-Jan-02 RMS Fixed bugs in KW11L (found by John Dundas)
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06-Jan-02 RMS Split I/O address routines, revised enable/disable support
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29-Nov-01 RMS Added read only unit support
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09-Nov-01 RMS Added RQDX3 support
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07-Oct-01 RMS Upgraded clock to full KW11L for RSTS/E autoconfigure
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07-Sep-01 RMS Moved function prototypes, revised interrupt mechanism
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17-Jul-01 RMS Moved function prototype
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04-Jul-01 RMS Added DZ11 support
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05-Mar-01 RMS Added clock calibration support
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30-Oct-00 RMS Standardized register order
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25-Jun-98 RMS Fixed bugs in paper tape error handling
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*/
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#include "pdp11_defs.h"
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#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTICSR_RW (CSR_IE)
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#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOCSR_RW (CSR_IE)
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#define CLKCSR_IMP (CSR_DONE + CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 16667
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extern int32 int_req[IPL_HLVL];
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extern uint32 cpu_type;
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int32 tti_csr = 0; /* control/status */
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int32 tto_csr = 0; /* control/status */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 60; /* ticks/second */
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int32 clk_default = 60; /* default ticks/second */
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int32 clk_fie = 0; /* force IE = 1 */
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int32 clk_fnxm = 0; /* force NXM on reg */
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int32 tmxr_poll = CLK_DELAY; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* timer poll */
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t_stat tti_rd (int32 *data, int32 PA, int32 access);
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t_stat tti_wr (int32 data, int32 PA, int32 access);
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t_stat tti_svc (UNIT *uptr);
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t_stat tti_reset (DEVICE *dptr);
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t_stat tto_rd (int32 *data, int32 PA, int32 access);
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t_stat tto_wr (int32 data, int32 PA, int32 access);
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t_stat tto_svc (UNIT *uptr);
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t_stat tto_reset (DEVICE *dptr);
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t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat clk_rd (int32 *data, int32 PA, int32 access);
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t_stat clk_wr (int32 data, int32 PA, int32 access);
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t_stat clk_svc (UNIT *uptr);
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int32 clk_inta (void);
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t_stat clk_reset (DEVICE *dptr);
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t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
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/* TTI data structures
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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*/
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DIB tti_dib = {
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IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
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1, IVCL (TTI), VEC_TTI, { NULL }
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};
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UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 };
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REG tti_reg[] = {
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{ ORDATA (BUF, tti_unit.buf, 8) },
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{ ORDATA (CSR, tti_csr, 16) },
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{ FLDATA (INT, IREQ (TTI), INT_V_TTI) },
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{ FLDATA (ERR, tti_csr, CSR_V_ERR) },
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{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
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{ FLDATA (IE, tti_csr, CSR_V_IE) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
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{ NULL }
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};
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MTAB tti_mod[] = {
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{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
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{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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&tti_dib, DEV_UBUS | DEV_QBUS
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};
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/* TTO data structures
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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*/
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DIB tto_dib = {
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IOBA_TTO, IOLN_TTO, &tto_rd, &tto_wr,
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1, IVCL (TTO), VEC_TTO, { NULL }
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};
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UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_7P, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ ORDATA (BUF, tto_unit.buf, 8) },
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{ ORDATA (CSR, tto_csr, 16) },
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{ FLDATA (INT, IREQ (TTO), INT_V_TTO) },
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{ FLDATA (ERR, tto_csr, CSR_V_ERR) },
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{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
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{ FLDATA (IE, tto_csr, CSR_V_IE) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ NULL }
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};
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MTAB tto_mod[] = {
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{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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&tto_dib, DEV_UBUS | DEV_QBUS
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};
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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DIB clk_dib = {
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IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr,
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1, IVCL (CLK), VEC_CLK, { &clk_inta }
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};
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UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
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REG clk_reg[] = {
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{ ORDATA (CSR, clk_csr, 16) },
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{ FLDATA (INT, IREQ (CLK), INT_V_CLK) },
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{ FLDATA (DONE, clk_csr, CSR_V_DONE) },
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{ FLDATA (IE, clk_csr, CSR_V_IE) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 16), PV_LEFT + REG_HRO },
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{ DRDATA (DEFTPS, clk_default, 16), PV_LEFT + REG_HRO },
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{ FLDATA (FIE, clk_fie, 0), REG_HIDDEN },
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{ FLDATA (FNXM, clk_fnxm, 0), REG_HIDDEN },
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
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NULL, &clk_show_freq, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
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&clk_dib, DEV_UBUS | DEV_QBUS
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};
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/* Terminal input address routines */
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t_stat tti_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 00: /* tti csr */
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*data = tti_csr & TTICSR_IMP;
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return SCPE_OK;
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case 01: /* tti buf */
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tti_csr = tti_csr & ~CSR_DONE;
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CLR_INT (TTI);
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*data = tti_unit.buf & 0377;
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return SCPE_OK;
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} /* end switch PA */
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return SCPE_NXM;
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}
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t_stat tti_wr (int32 data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 00: /* tti csr */
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if (PA & 1)
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return SCPE_OK;
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if ((data & CSR_IE) == 0)
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CLR_INT (TTI);
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else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTI);
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tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);
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return SCPE_OK;
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case 01: /* tti buf */
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return SCPE_OK;
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} /* end switch PA */
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return SCPE_NXM;
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}
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/* Terminal input service */
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t_stat tti_svc (UNIT *uptr)
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{
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int32 c;
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sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */
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if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
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return c;
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if (c & SCPE_BREAK) /* break? */
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uptr->buf = 0;
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else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
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uptr->pos = uptr->pos + 1;
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tti_csr = tti_csr | CSR_DONE;
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if (tti_csr & CSR_IE)
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SET_INT (TTI);
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return SCPE_OK;
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}
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/* Terminal input reset */
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t_stat tti_reset (DEVICE *dptr)
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{
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tti_unit.buf = 0;
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tti_csr = 0;
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CLR_INT (TTI);
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sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
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return SCPE_OK;
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}
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/* Terminal output address routines */
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t_stat tto_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 00: /* tto csr */
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*data = tto_csr & TTOCSR_IMP;
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return SCPE_OK;
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case 01: /* tto buf */
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*data = tto_unit.buf;
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return SCPE_OK;
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} /* end switch PA */
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return SCPE_NXM;
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}
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t_stat tto_wr (int32 data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 00: /* tto csr */
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if (PA & 1)
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return SCPE_OK;
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if ((data & CSR_IE) == 0)
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CLR_INT (TTO);
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else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
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SET_INT (TTO);
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tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
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return SCPE_OK;
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case 01: /* tto buf */
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if ((PA & 1) == 0)
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tto_unit.buf = data & 0377;
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tto_csr = tto_csr & ~CSR_DONE;
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CLR_INT (TTO);
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sim_activate (&tto_unit, tto_unit.wait);
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return SCPE_OK;
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} /* end switch PA */
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return SCPE_NXM;
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}
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/* Terminal output service */
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t_stat tto_svc (UNIT *uptr)
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{
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int32 c;
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t_stat r;
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c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags));
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if (c >= 0) {
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if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* try again */
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return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
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}
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}
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tto_csr = tto_csr | CSR_DONE;
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if (tto_csr & CSR_IE)
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SET_INT (TTO);
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uptr->pos = uptr->pos + 1;
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return SCPE_OK;
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}
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/* Terminal output reset */
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t_stat tto_reset (DEVICE *dptr)
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{
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tto_unit.buf = 0;
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tto_csr = CSR_DONE;
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CLR_INT (TTO);
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sim_cancel (&tto_unit); /* deactivate unit */
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return SCPE_OK;
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}
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t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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tti_unit.flags = (tti_unit.flags & ~TT_MODE) | val;
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tto_unit.flags = (tto_unit.flags & ~TT_MODE) | val;
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return SCPE_OK;
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}
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/* The line time clock has a few twists and turns through the history of 11's
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LSI-11 no CSR
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LSI-11/23 (KDF11A) no CSR
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PDP-11/23+ (KDF11B) no monitor bit
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PDP-11/24 (KDF11U) monitor bit clears on IAK
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*/
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/* Clock I/O address routines */
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t_stat clk_rd (int32 *data, int32 PA, int32 access)
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{
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if (clk_fnxm) /* not there??? */
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return SCPE_NXM;
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if (CPUT (HAS_LTCM)) /* monitor bit? */
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*data = clk_csr & CLKCSR_IMP;
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else *data = clk_csr & (CLKCSR_IMP & ~CSR_DONE); /* no, just IE */
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return SCPE_OK;
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}
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t_stat clk_wr (int32 data, int32 PA, int32 access)
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{
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if (clk_fnxm) /* not there??? */
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return SCPE_NXM;
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if (PA & 1)
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return SCPE_OK;
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clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
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if (CPUT (HAS_LTCM) && ((data & CSR_DONE) == 0)) /* monitor bit? */
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clk_csr = clk_csr & ~CSR_DONE; /* clr if zero */
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if ((((clk_csr & CSR_IE) == 0) && !clk_fie) || /* unless IE+DONE */
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((clk_csr & CSR_DONE) == 0)) /* clr intr */
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CLR_INT (CLK);
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return SCPE_OK;
|
|
}
|
|
|
|
/* Clock service */
|
|
|
|
t_stat clk_svc (UNIT *uptr)
|
|
{
|
|
int32 t;
|
|
|
|
clk_csr = clk_csr | CSR_DONE; /* set done */
|
|
if ((clk_csr & CSR_IE) || clk_fie)
|
|
SET_INT (CLK);
|
|
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
|
|
sim_activate (&clk_unit, t); /* reactivate unit */
|
|
tmr_poll = t; /* set timer poll */
|
|
tmxr_poll = t; /* set mux poll */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Clock interrupt acknowledge */
|
|
|
|
int32 clk_inta (void)
|
|
{
|
|
if (CPUT (CPUT_24))
|
|
clk_csr = clk_csr & ~CSR_DONE;
|
|
return clk_dib.vec;
|
|
}
|
|
|
|
/* Clock coscheduling routine */
|
|
|
|
int32 clk_cosched (int32 wait)
|
|
{
|
|
int32 t;
|
|
|
|
t = sim_is_active (&clk_unit);
|
|
return (t? t - 1: wait);
|
|
}
|
|
|
|
/* Clock reset */
|
|
|
|
t_stat clk_reset (DEVICE *dptr)
|
|
{
|
|
if (CPUT (HAS_LTCR)) /* reg there? */
|
|
clk_fie = clk_fnxm = 0;
|
|
else clk_fie = clk_fnxm = 1; /* no, BEVENT */
|
|
clk_tps = clk_default; /* set default tps */
|
|
clk_csr = CSR_DONE; /* set done */
|
|
CLR_INT (CLK);
|
|
sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */
|
|
sim_activate_abs (&clk_unit, clk_unit.wait); /* activate unit */
|
|
tmr_poll = clk_unit.wait; /* set timer poll */
|
|
tmxr_poll = clk_unit.wait; /* set mux poll */
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Set frequency */
|
|
|
|
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
if (cptr)
|
|
return SCPE_ARG;
|
|
if ((val != 50) && (val != 60))
|
|
return SCPE_IERR;
|
|
clk_tps = clk_default = val;
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Show frequency */
|
|
|
|
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
fprintf (st, "%dHz", clk_tps);
|
|
return SCPE_OK;
|
|
}
|