b6393b36b4
RESTRICTION: The HP DS disk is not debugged. DO NOT enable this feature for normal operations. WARNING: Massive changes in the PDP-11 make all previous SAVEd file obsolete. Do not attempt to use a PDP-11 SAVE file from a prior release with V3.3! 1. New Features in 3.3 1.1 SCP - Added -p (powerup) qualifier to RESET - Changed SET <unit> ONLINE/OFFLINE to SET <unit> ENABLED/DISABLED - Moved SET DEBUG under SET CONSOLE hierarchy - Added optional parameter value to SHOW command - Added output file option to SHOW command 1.2 PDP-11 - Separated RH Massbus adapter from RP controller - Added TU tape support - Added model emulation framework - Added model details 1.3 VAX - Separated out CVAX-specific features from core instruction simulator - Implemented capability for CIS, octaword, compatibility mode instructions - Added instruction display and parse for compatibility mode - Changed SET CPU VIRTUAL=n to SHOW CPU VIRTUAL=n - Added =n optional parameter to SHOW CPU HISTORY 1.4 Unibus/Qbus simulators (PDP-11, VAX, PDP-10) - Simplified DMA API's - Modified DMA peripherals to use simplified API's 1.5 HP2100 (all changes from Dave Bryan) CPU - moved MP into its own device; added MP option jumpers - modified DMA to allow disabling - modified SET CPU 2100/2116 to truncate memory > 32K - added -F switch to SET CPU to force memory truncation - modified WRU to be REG_HRO - added BRK and DEL to save console settings DR - provided protected tracks and "Writing Enabled" status bit - added "parity error" status return on writes for 12606 - added track origin test for 12606 - added SCP test for 12606 - added "Sector Flag" status bit - added "Read Inhibit" status bit for 12606 - added TRACKPROT modifier LPS - added SET OFFLINE/ONLINE, POWEROFF/POWERON - added fast/realistic timing - added debug printouts LPT - added SET OFFLINE/ONLINE, POWEROFF/POWERON PTR - added paper tape loop mode, DIAG/READER modifiers to PTR - added PV_LEFT to PTR TRLLIM register CLK - modified CLK to permit disable 1.6 IBM 1401, IBM 1620, Interdata 16b, SDS 940, PDP-10 - Added instruction history 1.7 H316, PDP-15, PDP-8 - Added =n optional value to SHOW CPU HISTORY 2. Bugs Fixed in 3.3 2.1 SCP - Fixed comma-separated SET options (from Dave Bryan) - Fixed duplicate HELP displays with user-specified commands 2.2 PDP-10 - Replicated RP register state per drive - Fixed TU to set FCE on short record - Fixed TU to return bit<15> in drive type - Fixed TU format specification, 1:0 are don't cares - Fixed TU handling of TMK status - Fixed TU handling of DONE, ATA at end of operation - Implemented TU write check 2.3 PDP-11 - Replicated RP register state per drive - Fixed RQ, TQ to report correct controller type and stage 1 configuration flags on a Unibus system - Fixed HK CS2<output_ready> flag 2.4 VAX - Fixed parsing of indirect displacement modes in instruction input 2.5 HP2100 (all fixes from Dave Bryan) CPU - fixed S-register behavior on 2116 - fixed LIx/MIx behavior for DMA on 2116 and 2100 - fixed LIx/MIx behavior for empty I/O card slots DP - fixed enable/disable from either device - fixed ANY ERROR status for 12557A interface - fixed unattached drive status for 12557A interface - status cmd without prior STC DC now completes (12557A) - OTA/OTB CC on 13210A interface also does CLC CC - fixed RAR model - fixed seek check on 13210 if sector out of range DQ - fixed enable/disable from either device - shortened xtime from 5 to 3 (drive avg 156KW/second) - fixed not ready/any error status - fixed RAR model DR - fixed enable/disable from either device - fixed sector return in status word - fixed DMA last word write, incomplete sector fill value - fixed 12610 SFC operation - fixed current-sector determination IPL - fixed enable/disable from either device LPS - fixed status returns for error conditions - fixed handling of non-printing characters - fixed handling of characters after column 80 - improved timing model accuracy for RTE LPT - fixed status returns for error conditions - fixed TOF handling so form remains on line 0 SYS - fixed display of CCA/CCB/CCE instructions 2.5 PDP-15 FPP - fixed URFST to mask low 9b of fraction - fixed exception PC setting
590 lines
20 KiB
C
590 lines
20 KiB
C
/* hp2100_sys.c: HP 2100 simulator interface
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Copyright (c) 1993-2004, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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25-Sep-04 JDB Added memory protect device
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Fixed display of CCA/CCB/CCE instructions
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01-Jun-04 RMS Added latent 13037 support
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19-Apr-04 RMS Recognize SFS x,C and SFC x,C
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22-Mar-02 RMS Revised for dynamically allocated memory
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14-Feb-02 RMS Added DMS instructions
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04-Feb-02 RMS Fixed bugs in alter/skip display and parsing
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01-Feb-02 RMS Added terminal multiplexor support
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16-Jan-02 RMS Added additional device support
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17-Sep-01 RMS Removed multiconsole support
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27-May-01 RMS Added multiconsole support
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14-Mar-01 RMS Revised load/dump interface (again)
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30-Oct-00 RMS Added examine to file support
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15-Oct-00 RMS Added dynamic device number support
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27-Oct-98 RMS V2.4 load interface
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*/
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#include "hp2100_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern UNIT cpu_unit;
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extern DEVICE mp_dev;
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extern DEVICE dma0_dev, dma1_dev;
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extern DEVICE ptr_dev, ptp_dev;
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extern DEVICE tty_dev, clk_dev;
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extern DEVICE lps_dev, lpt_dev;
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extern DEVICE mtd_dev, mtc_dev;
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extern DEVICE msd_dev, msc_dev;
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extern DEVICE dpd_dev, dpc_dev;
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extern DEVICE dqd_dev, dqc_dev;
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extern DEVICE drd_dev, drc_dev;
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extern DEVICE ds_dev;
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extern DEVICE muxl_dev, muxu_dev, muxc_dev;
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extern DEVICE ipli_dev, iplo_dev;
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extern REG cpu_reg[];
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extern uint16 *M;
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax maximum number of words for examine/deposit
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "HP 2100";
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char halt_msg[] = "HALT instruction xxxxxx";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 3;
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&mp_dev,
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&dma0_dev,
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&dma1_dev,
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&ptr_dev,
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&ptp_dev,
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&tty_dev,
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&clk_dev,
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&lps_dev,
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&lpt_dev,
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&dpd_dev, &dpc_dev,
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&dqd_dev, &dqc_dev,
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&drd_dev, &drc_dev,
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&ds_dev,
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&mtd_dev, &mtc_dev,
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&msd_dev, &msc_dev,
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&muxl_dev, &muxu_dev, &muxc_dev,
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&ipli_dev, &iplo_dev,
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NULL };
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const char *sim_stop_messages[] = {
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"Unknown error",
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"Unimplemented instruction",
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"Non-existent I/O device",
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halt_msg,
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"Breakpoint",
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"Indirect address loop",
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"Indirect address interrupt (should not happen!)",
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"No connection on interprocessor link" };
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/* Binary loader
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The binary loader consists of blocks preceded and trailed by zero frames.
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A block consists of 16b words (punched big endian), as follows:
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count'xxx
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origin
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word 0
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:
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word count-1
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checksum
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The checksum includes the origin but not the count.
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*/
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int32 fgetw (FILE *fileref)
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{
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int c1, c2;
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if ((c1 = fgetc (fileref)) == EOF) return -1;
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if ((c2 = fgetc (fileref)) == EOF) return -1;
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return ((c1 & 0377) << 8) | (c2 & 0377);
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}
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t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
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{
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int32 origin, csum, zerocnt, count, word, i;
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if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
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for (zerocnt = 1;; zerocnt = -10) { /* block loop */
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for (;; zerocnt++) { /* skip 0's */
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if ((count = fgetc (fileref)) == EOF) return SCPE_OK;
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else if (count) break;
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else if (zerocnt == 0) return SCPE_OK; }
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if (fgetc (fileref) == EOF) return SCPE_FMT;
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if ((origin = fgetw (fileref)) < 0) return SCPE_FMT;
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csum = origin; /* seed checksum */
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for (i = 0; i < count; i++) { /* get data words */
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if ((word = fgetw (fileref)) < 0) return SCPE_FMT;
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if (MEM_ADDR_OK (origin)) M[origin] = word;
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origin = origin + 1;
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csum = csum + word; }
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if ((word = fgetw (fileref)) < 0) return SCPE_FMT;
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if ((word ^ csum) & DMASK) return SCPE_CSUM; }
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return SCPE_OK;
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}
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/* Symbol tables */
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#define I_V_FL 16 /* flag start */
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#define I_M_FL 017 /* flag mask */
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#define I_V_NPN 0 /* no operand */
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#define I_V_NPC 1 /* no operand + C */
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#define I_V_MRF 2 /* mem ref */
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#define I_V_ASH 3 /* alter/skip, shift */
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#define I_V_ESH 4 /* extended shift */
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#define I_V_EMR 5 /* extended mem ref */
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#define I_V_IO1 6 /* I/O + HC */
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#define I_V_IO2 7 /* I/O only */
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#define I_V_EGZ 010 /* ext grp, 1 op + 0 */
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#define I_V_EG2 011 /* ext grp, 2 op */
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#define I_NPN (I_V_NPN << I_V_FL)
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#define I_NPC (I_V_NPC << I_V_FL)
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#define I_MRF (I_V_MRF << I_V_FL)
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#define I_ASH (I_V_ASH << I_V_FL)
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#define I_ESH (I_V_ESH << I_V_FL)
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#define I_EMR (I_V_EMR << I_V_FL)
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#define I_IO1 (I_V_IO1 << I_V_FL)
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#define I_IO2 (I_V_IO2 << I_V_FL)
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#define I_EGZ (I_V_EGZ << I_V_FL)
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#define I_EG2 (I_V_EG2 << I_V_FL)
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static const int32 masks[] = {
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0177777, 0176777, 0074000, 0170000,
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0177760, 0177777, 0176700, 0177700,
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0177777, 0177777 };
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static const char *opcode[] = {
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"NOP", "NOP", "AND", "JSB",
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"XOR", "JMP", "IOR", "ISZ",
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"ADA", "ADB" ,"CPA", "CPB",
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"LDA", "LDB", "STA", "STB",
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"DIAG", "ASL", "LSL", "TIMER",
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"RRL", "ASR", "LSR", "RRR",
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"MPY", "DIV", "DLD", "DST",
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"FAD", "FSB", "FMP", "FDV",
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"FIX", "FLT",
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"STO", "CLO", "SOC", "SOS",
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"HLT", "STF", "CLF",
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"SFC", "SFS", "MIA", "MIB",
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"LIA", "LIB", "OTA", "OTB",
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"STC", "CLC",
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"SYA", "USA", "PAA", "PBA",
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"XMA",
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"XLA", "XSA", "XCA", "LFA",
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"RSA", "RVA",
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"MBI", "MBF",
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"MBW", "MWI", "MWF", "MWW",
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"SYB", "USB", "PAB", "PBB",
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"SSM", "JRS",
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"XMM", "XMS", "XMB",
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"XLB", "XSB", "XCB", "LFB",
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"RSB", "RVB", "DJP", "DJS",
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"SJP", "SJS", "UJP", "UJS",
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"SAX", "SBX", "CAX", "CBX",
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"LAX", "LBX", "STX",
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"CXA", "CXB", "LDX",
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"ADX", "XAX", "XBX",
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"SAY", "SBY", "CAY", "CBY",
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"LAY", "LBY", "STY",
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"CYA", "CYB", "LDY",
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"ADY", "XAY", "XBY",
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"ISX", "DSX", "JLY", "LBT",
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"SBT", "MBT", "CBT", "SBT",
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"ISY", "DSY", "JPY", "SBS",
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"CBS", "TBS", "CMW", "MVW",
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NULL, /* decode only */
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NULL };
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static const int32 opc_val[] = {
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0000000+I_NPN, 0002000+I_NPN, 0010000+I_MRF, 0014000+I_MRF,
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0020000+I_MRF, 0024000+I_MRF, 0030000+I_MRF, 0034000+I_MRF,
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0040000+I_MRF, 0044000+I_MRF, 0050000+I_MRF, 0054000+I_MRF,
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0060000+I_MRF, 0064000+I_MRF, 0070000+I_MRF, 0074000+I_MRF,
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0100000+I_NPN, 0100020+I_ESH, 0100040+I_ESH, 0100060+I_NPN,
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0100100+I_ESH, 0101020+I_ESH, 0101040+I_ESH, 0101100+I_ESH,
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0100200+I_EMR, 0100400+I_EMR, 0104200+I_EMR, 0104400+I_EMR,
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0105000+I_EMR, 0105020+I_EMR, 0105040+I_EMR, 0105060+I_EMR,
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0105100+I_NPN, 0105120+I_NPN,
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0102101+I_NPN, 0103101+I_NPN, 0102201+I_NPC, 0102301+I_NPC,
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0102000+I_IO1, 0102100+I_IO2, 0103100+I_IO2,
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0102200+I_IO1, 0102300+I_IO1, 0102400+I_IO1, 0106400+I_IO1,
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0102500+I_IO1, 0106500+I_IO1, 0102600+I_IO1, 0106600+I_IO1,
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0102700+I_IO1, 0106700+I_IO1,
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0101710+I_NPN, 0101711+I_NPN, 0101712+I_NPN, 0101713+I_NPN,
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0101722+I_NPN,
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0101724+I_EMR, 0101725+I_EMR, 0101726+I_EMR, 0101727+I_NPN,
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0101730+I_NPN, 0101731+I_NPN,
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0105702+I_NPN, 0105703+I_NPN,
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0105704+I_NPN, 0105705+I_NPN, 0105706+I_NPN, 0105707+I_NPN,
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0105710+I_NPN, 0105711+I_NPN, 0105712+I_NPN, 0105713+I_NPN,
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0105714+I_EMR, 0105715+I_EG2,
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0105720+I_NPN, 0105721+I_NPN, 0105722+I_NPN,
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0105724+I_EMR, 0105725+I_EMR, 0105726+I_EMR, 0105727+I_NPN,
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0105730+I_NPN, 0105731+I_NPN, 0105732+I_EMR, 0105733+I_EMR,
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0105734+I_EMR, 0105735+I_EMR, 0105736+I_EMR, 0105737+I_EMR,
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0101740+I_EMR, 0105740+I_EMR, 0101741+I_NPN, 0105741+I_NPN,
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0101742+I_EMR, 0105742+I_EMR, 0105743+I_EMR,
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0101744+I_NPN, 0105744+I_NPN, 0105745+I_EMR,
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0105746+I_EMR, 0101747+I_NPN, 0105747+I_NPN,
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0101750+I_EMR, 0105750+I_EMR, 0101751+I_NPN, 0105751+I_NPN,
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0101752+I_EMR, 0105752+I_EMR, 0105753+I_EMR,
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0101754+I_NPN, 0105754+I_NPN, 0105755+I_EMR,
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0105756+I_EMR, 0101757+I_NPN, 0105757+I_NPN,
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0105760+I_NPN, 0105761+I_NPN, 0105762+I_EMR, 0105763+I_NPN,
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0105764+I_NPN, 0105765+I_EGZ, 0105766+I_EGZ, 0105767+I_NPN,
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0105770+I_NPN, 0105771+I_NPN, 0105772+I_EMR, 0105773+I_EG2,
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0105774+I_EG2, 0105775+I_EG2, 0105776+I_EGZ, 0105777+I_EGZ,
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0000000+I_ASH, /* decode only */
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-1 };
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/* Decode tables for shift and alter/skip groups */
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static const char *stab[] = {
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"ALS", "ARS", "RAL", "RAR", "ALR", "ERA", "ELA", "ALF",
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"BLS", "BRS", "RBL", "RBR", "BLR", "ERB", "ELB", "BLF",
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"CLA", "CMA", "CCA", "CLB", "CMB", "CCB",
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"SEZ", "CLE", "CLE", "CME", "CCE",
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"SSA", "SSB", "SLA", "SLB",
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"ALS", "ARS", "RAL", "RAR", "ALR", "ERA", "ELA", "ALF",
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"BLS", "BRS", "RBL", "RBR", "BLR", "ERB", "ELB", "BLF",
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"INA", "INB", "SZA", "SZB", "RSS",
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NULL };
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static const int32 mtab[] = {
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0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700,
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0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700, 0007700,
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0007400, 0007400, 0007400, 0007400, 0007400, 0007400,
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0002040, 0002040, 0002300, 0002300, 0002300,
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0006020, 0006020, 0004010, 0004010,
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0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027,
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0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027, 0006027,
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0006004, 0006004, 0006002, 0006002, 0002001,
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0 };
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static const int32 vtab[] = {
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0001000, 0001100, 0001200, 0001300, 0001400, 0001500, 0001600, 0001700,
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0005000, 0005100, 0005200, 0005300, 0005400, 0005500, 0005600, 0005700,
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0002400, 0003000, 0003400, 0006400, 0007000, 0007400,
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0002040, 0000040, 0002100, 0002200, 0002300,
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0002020, 0006020, 0000010, 0004010,
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0000020, 0000021, 0000022, 0000023, 0000024, 0000025, 0000026, 0000027,
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0004020, 0004021, 0004022, 0004023, 0004024, 0004025, 0004026, 0004027,
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0002004, 0006004, 0002002, 0006002, 0002001,
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-1 };
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/* Symbolic decode
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Inputs:
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*of = output stream
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addr = current PC
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*val = pointer to data
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*uptr = pointer to unit
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sw = switches
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Outputs:
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return = status code
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*/
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#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw)
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{
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int32 cflag, cm, i, j, inst, disp;
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cflag = (uptr == NULL) || (uptr == &cpu_unit);
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inst = val[0];
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if (sw & SWMASK ('A')) { /* ASCII? */
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if (inst > 0377) return SCPE_ARG;
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fprintf (of, FMTASC (inst & 0177));
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||
return SCPE_OK; }
|
||
if (sw & SWMASK ('C')) { /* characters? */
|
||
fprintf (of, FMTASC ((inst >> 8) & 0177));
|
||
fprintf (of, FMTASC (inst & 0177));
|
||
return SCPE_OK; }
|
||
if (!(sw & SWMASK ('M'))) return SCPE_ARG;
|
||
|
||
/* Instruction decode */
|
||
|
||
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||
if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
|
||
|
||
switch (j) { /* case on class */
|
||
case I_V_NPN: /* no operands */
|
||
fprintf (of, "%s", opcode[i]); /* opcode */
|
||
break;
|
||
case I_V_NPC: /* no operands + C */
|
||
fprintf (of, "%s", opcode[i]);
|
||
if (inst & I_HC) fprintf (of, " C");
|
||
break;
|
||
case I_V_MRF: /* mem ref */
|
||
disp = inst & I_DISP; /* displacement */
|
||
fprintf (of, "%s ", opcode[i]); /* opcode */
|
||
if (inst & I_CP) { /* current page? */
|
||
if (cflag) fprintf (of, "%-o", (addr & I_PAGENO) | disp);
|
||
else fprintf (of, "C %-o", disp); }
|
||
else fprintf (of, "%-o", disp); /* page zero */
|
||
if (inst & I_IA) fprintf (of, ",I");
|
||
break;
|
||
case I_V_ASH: /* shift, alter-skip */
|
||
cm = FALSE;
|
||
for (i = 0; mtab[i] != 0; i++) {
|
||
if ((inst & mtab[i]) == vtab[i]) {
|
||
inst = inst & ~(vtab[i] & 01777);
|
||
if (cm) fprintf (of, ",");
|
||
cm = TRUE;
|
||
fprintf (of, "%s", stab[i]); } }
|
||
if (!cm) return SCPE_ARG; /* nothing decoded? */
|
||
break;
|
||
case I_V_ESH: /* extended shift */
|
||
disp = inst & 017; /* shift count */
|
||
if (disp == 0) disp = 16;
|
||
fprintf (of, "%s %d", opcode[i], disp);
|
||
break;
|
||
case I_V_EMR: /* extended mem ref */
|
||
fprintf (of, "%s %-o", opcode[i], val[1] & VAMASK);
|
||
if (val[1] & I_IA) fprintf (of, ",I");
|
||
return -1; /* extra word */
|
||
case I_V_IO1: /* IOT with H/C */
|
||
fprintf (of, "%s %-o", opcode[i], inst & I_DEVMASK);
|
||
if (inst & I_HC) fprintf (of, ",C");
|
||
break;
|
||
case I_V_IO2: /* IOT */
|
||
fprintf (of, "%s %-o", opcode[i], inst & I_DEVMASK);
|
||
break;
|
||
case I_V_EGZ: /* ext grp 1 op + 0 */
|
||
fprintf (of, "%s %-o", opcode[i], val[1] & VAMASK);
|
||
if (val[1] & I_IA) fprintf (of, ",I");
|
||
return -2; /* extra words */
|
||
case I_V_EG2: /* ext grp 2 op */
|
||
fprintf (of, "%s %-o", opcode[i], val[1] & VAMASK);
|
||
if (val[1] & I_IA) fprintf (of, ",I");
|
||
fprintf (of, " %-o", val[2] & VAMASK);
|
||
if (val[2] & I_IA) fprintf (of, ",I");
|
||
return -2; } /* extra words */
|
||
return SCPE_OK; } /* end if */
|
||
} /* end for */
|
||
return SCPE_ARG;
|
||
}
|
||
|
||
/* Get address with indirection
|
||
|
||
Inputs:
|
||
*cptr = pointer to input string
|
||
Outputs:
|
||
val = address
|
||
-1 if error
|
||
*/
|
||
|
||
int32 get_addr (char *cptr)
|
||
{
|
||
int32 d;
|
||
t_stat r;
|
||
char gbuf[CBUFSIZE];
|
||
|
||
cptr = get_glyph (cptr, gbuf, ','); /* get next field */
|
||
d = get_uint (gbuf, 8, VAMASK, &r); /* construe as addr */
|
||
if (r != SCPE_OK) return -1;
|
||
if (*cptr != 0) { /* more? */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* look for indirect */
|
||
if (*cptr != 0) return -1; /* should be done */
|
||
if (strcmp (gbuf, "I")) return -1; /* I? */
|
||
d = d | I_IA; }
|
||
return d;
|
||
}
|
||
|
||
/* Symbolic input
|
||
|
||
Inputs:
|
||
*iptr = pointer to input string
|
||
addr = current PC
|
||
*uptr = pointer to unit
|
||
*val = pointer to output values
|
||
sw = switches
|
||
Outputs:
|
||
status = error status
|
||
*/
|
||
|
||
t_stat parse_sym (char *iptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||
{
|
||
int32 cflag, d, i, j, k, clef, tbits;
|
||
t_stat r, ret;
|
||
char *cptr, gbuf[CBUFSIZE];
|
||
|
||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||
while (isspace (*iptr)) iptr++; /* absorb spaces */
|
||
if ((sw & SWMASK ('A')) || ((*iptr == '\'') && iptr++)) { /* ASCII char? */
|
||
if (iptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (t_value) iptr[0] & 0177;
|
||
return SCPE_OK; }
|
||
if ((sw & SWMASK ('C')) || ((*iptr == '"') && iptr++)) { /* char string? */
|
||
if (iptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||
val[0] = (((t_value) iptr[0] & 0177) << 8) |
|
||
((t_value) iptr[1] & 0177);
|
||
return SCPE_OK; }
|
||
|
||
/* Instruction parse */
|
||
|
||
ret = SCPE_OK;
|
||
cptr = get_glyph (iptr, gbuf, 0); /* get opcode */
|
||
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||
if (opcode[i]) { /* found opcode? */
|
||
val[0] = opc_val[i] & DMASK; /* get value */
|
||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||
|
||
switch (j) { /* case on class */
|
||
case I_V_NPN: /* no operand */
|
||
break;
|
||
case I_V_NPC: /* no operand + C */
|
||
if (*cptr != 0) {
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
if (strcmp (gbuf, "C")) return SCPE_ARG;
|
||
val[0] = val[0] | I_HC; }
|
||
break;
|
||
case I_V_MRF: /* mem ref */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if (k = (strcmp (gbuf, "C") == 0)) { /* C specified? */
|
||
val[0] = val[0] | I_CP;
|
||
cptr = get_glyph (cptr, gbuf, 0); }
|
||
else if (k = (strcmp (gbuf, "Z") == 0)) { /* Z specified? */
|
||
cptr = get_glyph (cptr, gbuf, ','); }
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
if ((d & VAMASK) <= I_DISP) val[0] = val[0] | d;
|
||
else if (cflag && !k && (((addr ^ d) & I_PAGENO) == 0))
|
||
val[0] = val[0] | (d & (I_IA | I_DISP)) | I_CP;
|
||
else return SCPE_ARG;
|
||
break;
|
||
case I_V_ESH: /* extended shift */
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
d = get_uint (gbuf, 10, 16, &r);
|
||
if ((r != SCPE_OK) || (d == 0)) return SCPE_ARG;
|
||
val[0] = val[0] | (d & 017);
|
||
break;
|
||
case I_V_EMR: /* extended mem ref */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
val[1] = d;
|
||
ret = -1;
|
||
break;
|
||
case I_V_IO1: /* IOT + optional C */
|
||
cptr = get_glyph (cptr, gbuf, ','); /* get device */
|
||
d = get_uint (gbuf, 8, I_DEVMASK, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
val[0] = val[0] | d;
|
||
if (*cptr != 0) {
|
||
cptr = get_glyph (cptr, gbuf, 0);
|
||
if (strcmp (gbuf, "C")) return SCPE_ARG;
|
||
val[0] = val[0] | I_HC; }
|
||
break;
|
||
case I_V_IO2: /* IOT */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get device */
|
||
d = get_uint (gbuf, 8, I_DEVMASK, &r);
|
||
if (r != SCPE_OK) return SCPE_ARG;
|
||
val[0] = val[0] | d;
|
||
break;
|
||
case I_V_EGZ: /* ext grp 1 op + 0 */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
val[1] = d;
|
||
val[2] = 0;
|
||
ret = -2;
|
||
break;
|
||
case I_V_EG2: /* ext grp 2 op */
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||
if ((k = get_addr (gbuf)) < 0) return SCPE_ARG;
|
||
val[1] = d;
|
||
val[2] = k;
|
||
ret = -2;
|
||
break; } /* end case */
|
||
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
|
||
return ret;
|
||
} /* end if opcode */
|
||
|
||
/* Shift or alter-skip
|
||
|
||
Each opcode is matched by a mask, specifiying the bits affected, and
|
||
the value, specifying the value. As opcodes are processed, the mask
|
||
values are used to specify which fields have already been filled in.
|
||
|
||
The mask has two subfields, the type bits (A/B and A/S), and the field
|
||
bits. The type bits, once specified by any instruction, must be
|
||
consistent in all other instructions. The mask bits assure that no
|
||
field is filled in twice.
|
||
|
||
Two special cases:
|
||
|
||
1. The dual shift field in shift requires checking how much of the
|
||
target word has been filled in before assigning the shift value.
|
||
To implement this, shifts are listed twice is the decode table.
|
||
If the current subopcode is a shift in the first part of the table
|
||
(entries 0..15), and CLE has been seen or the first shift field is
|
||
filled in, the code forces a mismatch. The glyph will match in
|
||
the second part of the table.
|
||
|
||
2. CLE processing must be deferred until the instruction can be
|
||
classified as shift or alter-skip, since it has two different
|
||
bit values in the two classes. To implement this, CLE seen is
|
||
recorded as a flag and processed after all other subopcodes.
|
||
*/
|
||
|
||
clef = FALSE;
|
||
tbits = 0;
|
||
val[0] = 0;
|
||
for (cptr = get_glyph (iptr, gbuf, ','); gbuf[0] != 0;
|
||
cptr = get_glyph (cptr, gbuf, ',')) { /* loop thru glyphs */
|
||
if (strcmp (gbuf, "CLE") == 0) { /* CLE? */
|
||
if (clef) return SCPE_ARG; /* already seen? */
|
||
clef = TRUE; /* set flag */
|
||
continue; }
|
||
for (i = 0; stab[i] != NULL; i++) { /* find subopcode */
|
||
if ((strcmp (gbuf, stab[i]) == 0) &&
|
||
((i >= 16) || (!clef && ((val[0] & 001710) == 0)))) break; }
|
||
if (stab[i] == NULL) return SCPE_ARG;
|
||
if (tbits & mtab[i] & (I_AB | I_ASKP) & (vtab[i] ^ val[0]))
|
||
return SCPE_ARG;
|
||
if (tbits & mtab[i] & ~(I_AB | I_ASKP)) return SCPE_ARG;
|
||
tbits = tbits | mtab[i]; /* fill type+mask */
|
||
val[0] = val[0] | vtab[i]; } /* fill value */
|
||
if (clef) { /* CLE seen? */
|
||
if (val[0] & I_ASKP) { /* alter-skip? */
|
||
if (tbits & 0100) return SCPE_ARG; /* already filled in? */
|
||
else val[0] = val[0] | 0100; }
|
||
else val[0] = val[0] | 040; } /* fill in shift */
|
||
return ret;
|
||
}
|