26aa6de663
RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. WARNING: The core simulator files (scp.c, sim_*.c) have been reorganized. Unzip V3.2-0 to an empty directory before attempting to compile the source. IMPORTANT: If you are compiling for UNIX, please read the notes for Ethernet very carefully. You may need to download a new version of the pcap library, or make changes to the makefile, to get Ethernet support to work. 1. New Features in 3.2-0 1.1 SCP and libraries - Added SHOW <device> RADIX command. - Added SHOW <device> MODIFIERS command. - Added SHOW <device> NAMES command. - Added SET/SHOW <device> DEBUG command. - Added sim_vm_parse_addr and sim_vm_fprint_addr optional interfaces. - Added REG_VMAD flag. - Split SCP into separate libraries for easier modification. - Added more room to the device and unit flag fields. - Changed terminal multiplexor library to support unlimited. number of async lines. 1.2 All DECtapes - Added STOP_EOR flag to enable end-of-reel error stop - Added device debug support. 1.3 Nova and Eclipse - Added QTY and ALM multiplexors (Bruce Ray). 1.4 LGP-30 - Added LGP-30/LGP-21 simulator. 1.5 PDP-11 - Added format, address increment inhibit, transfer overrun detection to RK. - Added device debug support to HK, RP, TM, TQ, TS. - Added DEUNA/DELUA (XU) support (Dave Hittner). - Add DZ per-line logging. 1.6 18b PDP's - Added support for 1-4 (PDP-9)/1-16 (PDP-15) additional terminals. 1.7 PDP-10 - Added DEUNA/DELUA (XU) support (Dave Hittner). 1.8 VAX - Added extended memory to 512MB (Mark Pizzolato). - Added RXV21 support. 2. Bugs Fixed in 3.2-0 2.1 SCP - Fixed double logging of SHOW BREAK (found by Mark Pizzolato). - Fixed implementation of REG_VMIO. 2.2 Nova and Eclipse - Fixed device enable/disable support (found by Bruce Ray). 2.3 PDP-1 - Fixed bug in LOAD (found by Mark Crispin). 2.4 PDP-10 - Fixed bug in floating point unpack. - Fixed bug in FIXR (found by Phil Stone, fixed by Chris Smith). 2.6 PDP-11 - Fixed bug in RQ interrupt control (found by Tom Evans). 2.6 PDP-18B - Fixed bug in PDP-15 XVM g_mode implementation. - Fixed bug in PDP-15 indexed address calculation. - Fixed bug in PDP-15 autoindexed address calculation. - Fixed bugs in FPP-15 instruction decode. - Fixed clock response to CAF. - Fixed bug in hardware read-in mode bootstrap. - Fixed PDP-15 XVM instruction decoding errors. 2.7 VAX - Fixed PC read fault in EXTxV. - Fixed PC write fault in INSV.
471 lines
16 KiB
C
471 lines
16 KiB
C
/* id_fp.c: Interdata floating point instructions
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Copyright (c) 2000-2004, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The Interdata uses IBM 360 floating point format:
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0 7 8 15 23 31
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|S| exponent | fraction | :single
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| fraction low | :double
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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where S = 0 for plus, 1 for minus
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exponent = 16**n, in excess 64 code
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fraction = .hhhhhh, seen as 6-14 hexadecimal digits
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Numbers can be normalized or unnormalized but are always normalized
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when loaded.
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Interdata has 8 floating point registers, F0, F2, ... , FE. In floating
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point instructions, the low order bit of the register number is ignored.
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On floating point overflow, the exponent and fraction are set to 1's.
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On floating point underflow, the exponent and fraction are set to 0's.
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Interdata has both 32b only and 32b/64b floating point implementations.
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In 32b only implementations, add and subtract are truncated, but multiply
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and divide are rounded, and the floating point registers are kept in
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memory. In 64b implementations, all single precision precision operations
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are rounded, double precision operations are truncated, and the floating
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point registers are kept in separate hardware arrays.
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*/
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#include "id_defs.h"
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struct ufp { /* unpacked fp */
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int32 sign; /* sign */
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int32 exp; /* unbiased exp */
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uint32 h; /* fr high */
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uint32 l; }; /* fr low */
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#define FP_V_SIGN 31 /* sign */
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#define FP_M_SIGN 0x1
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#define FP_GETSIGN(x) (((x) >> FP_V_SIGN) & FP_M_SIGN)
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#define FP_V_EXP 24 /* exponent */
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#define FP_M_EXP 0x7F
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#define FP_GETEXP(x) (((x) >> FP_V_EXP) & FP_M_EXP)
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#define FP_V_FRH 0 /* fraction */
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#define FP_M_FRH 0xFFFFFF
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#define FP_GETFRH(x) (((x) >> FP_V_FRH) & FP_M_FRH)
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#define FP_GETFRL(x) (x)
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#define FP_BIAS 0x40 /* exp bias */
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#define FP_CARRY (1 << FP_V_EXP ) /* carry out */
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#define FP_NORM (0xF << (FP_V_EXP - 4)) /* normalized */
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#define FP_ROUND 0x80000000
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/* Double precision fraction add/subtract/compare */
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#define FR_ADD(d,s) d.l = (d.l + s.l) & DMASK32; \
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d.h = (d.h + s.h + (d.l < s.l)) & DMASK32
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#define FR_SUB(d,s) d.h = (d.h - s.h - (d.l < s.l)) & DMASK32; \
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d.l = (d.l - s.l) & DMASK32
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#define FR_GE(s1,s2) ((s1.h > s2.h) || \
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((s1.h == s2.h) && (s1.l >= s2.l)))
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/* Variable and constant shifts; for constants, 0 < k < 32 */
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#define FR_RSH_V(v,s) if ((s) < 32) { \
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v.l = ((v.l >> (s)) | \
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(v.h << (32 - (s)))) & DMASK32; \
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v.h = (v.h >> (s)) & DMASK32; } \
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else { v.l = v.h >> ((s) - 32); \
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v.h = 0; }
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#define FR_RSH_K(v,s) v.l = ((v.l >> (s)) | \
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(v.h << (32 - (s)))) & DMASK32; \
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v.h = (v.h >> (s)) & DMASK32
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#define FR_LSH_K(v,s) v.h = ((v.h << (s)) | \
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(v.l >> (32 - (s)))) & DMASK32; \
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v.l = (v.l << (s)) & DMASK32
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#define Q_RND(op) (OP_DPFP (op) == 0)
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#define Q_RND_AS(op) ((OP_DPFP (op) == 0) && fp_in_hwre)
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extern uint32 *R;
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extern uint32 F[8];
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extern dpr_t D[8];
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extern uint16 decrom[];
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extern uint32 fp_in_hwre;
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extern uint32 ReadF (uint32 loc, uint32 rel);
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extern void WriteF (uint32 loc, uint32 dat, uint32 rel);
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void ReadFP2 (struct ufp *fop, uint32 op, uint32 r2, uint32 ea);
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void UnpackFPR (struct ufp *fop, uint32 op, uint32 r1);
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void NormUFP (struct ufp *fop);
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uint32 StoreFPR (struct ufp *fop, uint32 op, uint32 r1, uint32 rnd);
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uint32 StoreFPX (struct ufp *fop, uint32 op, uint32 r1);
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/* Floating point load */
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uint32 f_l (uint32 op, uint32 r1, uint32 r2, uint32 ea)
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{
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struct ufp fop2;
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ReadFP2 (&fop2, op, r2, ea); /* get op, normalize */
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return StoreFPR (&fop2, op, r1, 0); /* store, chk unflo */
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}
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/* Floating point compare */
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uint32 f_c (uint32 op, uint32 r1, uint32 r2, uint32 ea)
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{
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struct ufp fop1, fop2;
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ReadFP2 (&fop2, op, r2, ea); /* get op2, norm */
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UnpackFPR (&fop1, op, r1); /* get op1, norm */
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if (fop1.sign ^ fop2.sign) /* signs differ? */
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return (fop2.sign? CC_G: (CC_C | CC_L));
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if (fop1.exp != fop2.exp) /* exps differ? */
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return (((fop1.exp > fop2.exp) ^ fop1.sign)? CC_G: (CC_C | CC_L));
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if (fop1.h != fop2.h) /* hi fracs differ? */
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return (((fop1.h > fop2.h) ^ fop1.sign)? CC_G: (CC_C | CC_L));
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if (OP_DPFP (op) && (fop1.l != fop2.l)) /* dp: low fracs diff? */
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return (((fop1.l > fop2.l) ^ fop1.sign)? CC_G: (CC_C | CC_L));
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return 0;
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}
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/* Floating to integer conversion */
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uint32 f_fix (uint32 op, uint32 r1, uint32 r2) /* 16b */
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{
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struct ufp res;
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uint32 cc;
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UnpackFPR (&res, op, r2); /* get op2, norm */
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if ((res.h == 0) || (res.exp < 0x41)) { /* result zero? */
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R[r1] = 0;
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return 0; }
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if ((res.exp > 0x44) || /* result too big? */
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((res.exp == 0x44) && (res.h >= 0x00800000))) {
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res.h = MMASK16;
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cc = CC_V; }
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else { res.h = res.h >> ((0x46 - res.exp) * 4); /* right align frac */
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cc = 0; }
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if (res.sign) {
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R[r1] = ((res.h ^ DMASK16) + 1) & DMASK16; /* negate result */
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return cc | CC_L; }
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R[r1] = res.h & DMASK16;
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return cc | CC_G;
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}
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uint32 f_fix32 (uint32 op, uint32 r1, uint32 r2) /* 32b */
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{
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struct ufp res;
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uint32 cc;
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UnpackFPR (&res, op, r2); /* get op2, norm */
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if ((res.h == 0) || (res.exp < 0x41)) { /* result zero? */
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R[r1] = 0;
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return 0; }
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if ((res.exp > 0x48) || /* result too big? */
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((res.exp == 0x48) && (res.h >= 0x00800000))) {
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res.h = MMASK32;
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cc = CC_V; }
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else { FR_LSH_K (res, 8); /* get all in 32b */
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res.h = res.h >> ((0x48 - res.exp) * 4); /* right align frac */
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cc = 0; }
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if (res.sign) {
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R[r1] = (res.h ^ DMASK32) + 1; /* negate result */
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return cc | CC_L; }
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R[r1] = res.h;
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return cc | CC_G;
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}
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/* Integer to floating conversion */
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uint32 f_flt (uint32 op, uint32 r1, uint32 r2) /* 16b */
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{
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struct ufp res = { 0, 0x44, 0, 0 }; /* +, 16**4 */
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uint32 cc;
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if (R[r2] == 0) cc = 0; /* zero arg? */
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else if (R[r2] & SIGN16) { /* neg arg? */
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res.sign = FP_M_SIGN; /* set sign */
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res.h = ((~R[r2] + 1) & DMASK16) << 8; /* get magnitude */
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cc = CC_L; }
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else { res.h = R[r2] << 8; /* pos nz arg */
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cc = CC_G; }
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NormUFP (&res); /* normalize */
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StoreFPR (&res, op, r1, 0); /* store result */
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return cc;
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}
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uint32 f_flt32 (uint32 op, uint32 r1, uint32 r2) /* 32b */
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{
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struct ufp res = { 0, 0x48, 0, 0 }; /* +, 16**8 */
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uint32 cc, t;
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t = R[r2]; /* int op */
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if (t) { /* nonzero arg? */
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if (t & SIGN32) { /* neg arg? */
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res.sign = FP_M_SIGN; /* set sign */
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t = (~t + 1) & DMASK32; /* get magnitude */
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cc = CC_L; }
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else cc = CC_G; /* pos nz arg */
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res.h = t >> 8; /* hi frac */
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res.l = t << 24; } /* lo frac */
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else cc = 0; /* zero arg */
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NormUFP (&res); /* normalize */
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StoreFPR (&res, op, r1, 0); /* store result */
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return cc;
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}
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/* Floating point add/subtract */
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uint32 f_as (uint32 op, uint32 r1, uint32 r2, uint32 ea)
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{
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struct ufp fop1, fop2, t;
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int32 ediff;
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ReadFP2 (&fop2, op, r2, ea); /* get op2, norm */
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UnpackFPR (&fop1, op, r1); /* get op1, norm */
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if (op & 1) fop2.sign = fop2.sign ^ 1; /* if sub, inv sign2 */
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if (fop1.h == 0) fop1 = fop2; /* if op1 = 0, res = op2 */
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else if (fop2.h != 0) { /* if op2 = 0, no add */
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if ((fop1.exp < fop2.exp) || /* |op1| < |op2|? */
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((fop1.exp == fop2.exp) &&
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((fop1.h < fop2.h) ||
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((fop1.h == fop2.h) && (fop1.l < fop2.l))))) {
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t = fop2; /* swap operands */
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fop2 = fop1;
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fop1 = t; }
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ediff = fop1.exp - fop2.exp; /* exp difference */
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if (OP_DPFP (op) || fp_in_hwre) { /* dbl prec or hwre? */
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if (ediff >= 14) fop2.h = fop2.l = 0; /* diff too big? */
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else if (ediff) { /* any difference? */
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FR_RSH_V (fop2, ediff * 4); } } /* shift frac */
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else { /* sgl prec ucode */
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if (ediff >= 6) fop2.h = 0; /* diff too big? */
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else if (ediff) /* any difference? */
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fop2.h = fop2.h >> (ediff * 4); } /* shift frac */
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if (fop1.sign ^ fop2.sign) { /* eff subtract */
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FR_SUB (fop1, fop2); /* sub fractions */
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NormUFP (&fop1); } /* normalize result */
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else {
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FR_ADD (fop1, fop2); /* add fractions */
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if (fop1.h & FP_CARRY) { /* carry out? */
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FR_RSH_K (fop1, 4); /* renormalize */
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fop1.exp = fop1.exp + 1; } } /* incr exp */
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} /* end if fop2 */
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return StoreFPR (&fop1, op, r1, Q_RND_AS (op)); /* store result */
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}
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/* Floating point multiply
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Notes:
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- Exponent overflow/underflow is tested right after the exponent
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add, without regard to potential changes due to normalization
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- Exponent underflow is tested right after normalization, without
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regard to changes due to rounding
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- Single precision hardware multiply may generate up to 48b
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- Double precision multiply generates 56b with no guard bits
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*/
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int32 f_m (uint32 op, uint32 r1, uint32 r2, uint32 ea)
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{
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struct ufp fop1, fop2;
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struct ufp res = { 0, 0, 0, 0 };
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uint32 i;
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ReadFP2 (&fop2, op, r2, ea); /* get op2, norm */
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UnpackFPR (&fop1, op, r1); /* get op1, norm */
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if (fop1.h && fop2.h) { /* if both != 0 */
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res.sign = fop1.sign ^ fop2.sign; /* sign = diff */
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res.exp = fop1.exp + fop2.exp - FP_BIAS; /* exp = sum */
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if ((res.exp < 0) || (res.exp > FP_M_EXP)) /* ovf/undf? */
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return StoreFPX (&res, op, r1); /* early out */
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if ((fop1.l | fop2.l) == 0) { /* 24b x 24b? */
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for (i = 0; i < 24; i++) { /* 24 iterations */
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if (fop2.h & 1) res.h = res.h + fop1.h; /* add hi only */
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FR_RSH_K (res, 1); /* shift dp res */
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fop2.h = fop2.h >> 1; }
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}
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else { /* some low 0's */
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if (fop2.l != 0) { /* 56b x 56b? */
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for (i = 0; i < 32; i++) { /* do low 32b */
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if (fop2.l & 1) { FR_ADD (res, fop1); }
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FR_RSH_K (res, 1);
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fop2.l = fop2.l >> 1; } }
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for (i = 0; i < 24; i++) { /* do hi 24b */
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if (fop2.h & 1) { FR_ADD (res, fop1); }
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FR_RSH_K (res, 1);
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fop2.h = fop2.h >> 1; }
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}
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NormUFP (&res); /* normalize */
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if (res.exp < 0) /* underflow? */
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return StoreFPX (&res, op, r1); /* early out */
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}
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return StoreFPR (&res, op, r1, Q_RND (op)); /* store */
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}
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/* Floating point divide - see overflow/underflow notes for multiply */
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int32 f_d (uint32 op, uint32 r1, uint32 r2, uint32 ea)
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{
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struct ufp fop1, fop2;
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struct ufp quo = { 0, 0, 0, 0 };
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int32 i;
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ReadFP2 (&fop2, op, r2, ea); /* get op2, norm */
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UnpackFPR (&fop1, op, r1); /* get op1, norm */
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if (fop2.h == 0) return CC_C | CC_V; /* div by zero? */
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if (fop1.h) { /* dvd != 0? */
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quo.sign = fop1.sign ^ fop2.sign; /* sign = diff */
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quo.exp = fop1.exp - fop2.exp + FP_BIAS; /* exp = diff */
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if ((quo.exp < 0) || (quo.exp > FP_M_EXP)) /* ovf/undf? */
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return StoreFPX (&quo, op, r1); /* early out */
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if (!FR_GE (fop1, fop2)) {
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FR_LSH_K (fop1, 4); } /* ensure success */
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else { /* exp off by 1 */
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quo.exp = quo.exp + 1; /* incr exponent */
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if (quo.exp > FP_M_EXP) /* overflow? */
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return StoreFPX (&quo, op, r1); } /* early out */
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for (i = 0; i < (OP_DPFP (op)? 14: 6); i++) { /* 6/14 hex digits */
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FR_LSH_K (quo, 4); /* shift quotient */
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while (FR_GE (fop1, fop2)) { /* while sub works */
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FR_SUB (fop1, fop2); /* decrement */
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quo.l = quo.l + 1; } /* add quo bit */
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FR_LSH_K (fop1, 4); } /* shift divd */
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if (!OP_DPFP (op)) { /* single? */
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quo.h = quo.l; /* move quotient */
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if (fop1.h >= (fop2.h << 3)) quo.l = FP_ROUND;
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else quo.l = 0; }
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/* don't need to normalize */
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} /* end if fop1.h */
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return StoreFPR (&quo, op, r1, Q_RND (op)); /* store result */
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}
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/* Utility routines */
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/* Unpack floating point number */
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void UnpackFPR (struct ufp *fop, uint32 op, uint32 r1)
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{
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uint32 hi;
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||
|
||
if (OP_DPFP (op)) { /* double prec? */
|
||
hi = D[r1 >> 1].h; /* get hi */
|
||
fop->l = FP_GETFRL (D[r1 >> 1].l); } /* get lo */
|
||
else { hi = ReadFReg (r1); /* single prec */
|
||
fop->l = 0; } /* lo is zero */
|
||
fop->h = FP_GETFRH (hi); /* get hi frac */
|
||
if (fop->h || fop->l) { /* non-zero? */
|
||
fop->sign = FP_GETSIGN (hi); /* get sign */
|
||
fop->exp = FP_GETEXP (hi); /* get exp */
|
||
NormUFP (fop); } /* normalize */
|
||
else fop->sign = fop->exp = 0; /* clean zero */
|
||
return;
|
||
}
|
||
|
||
/* Read memory operand */
|
||
|
||
void ReadFP2 (struct ufp *fop, uint32 op, uint32 r2, uint32 ea)
|
||
{
|
||
uint32 hi;
|
||
|
||
if (OP_TYPE (op) > OP_RR) { /* mem ref? */
|
||
hi = ReadF (ea, VR); /* get hi */
|
||
if (OP_DPFP (op)) fop->l = ReadF (ea + 4, VR); /* dp? get lo */
|
||
else fop->l = 0; } /* sp, lo = 0 */
|
||
else { if (OP_DPFP (op)) { /* RR */
|
||
hi = D[r2 >> 1].h; /* dp? get dp reg */
|
||
fop->l = D[r2 >> 1].l; }
|
||
else {
|
||
hi = ReadFReg (r2); /* get sp reg */
|
||
fop->l = 0; } }
|
||
fop->h = FP_GETFRH (hi); /* get hi frac */
|
||
if (fop->h || fop->l) { /* non-zero? */
|
||
fop->sign = FP_GETSIGN (hi); /* get sign */
|
||
fop->exp = FP_GETEXP (hi); /* get exp */
|
||
NormUFP (fop); } /* normalize */
|
||
else fop->sign = fop->exp = 0; /* clean zero */
|
||
return;
|
||
}
|
||
|
||
/* Normalize unpacked floating point number */
|
||
|
||
void NormUFP (struct ufp *fop)
|
||
{
|
||
if ((fop->h & FP_M_FRH) || fop->l) { /* any fraction? */
|
||
while ((fop->h & FP_NORM) == 0) { /* until norm */
|
||
fop->h = (fop->h << 4) | ((fop->l >> 28) & 0xF);
|
||
fop->l = fop->l << 4;
|
||
fop->exp = fop->exp - 1; } }
|
||
else fop->sign = fop->exp = 0; /* clean 0 */
|
||
return;
|
||
}
|
||
|
||
/* Round fp number, store, generate condition codes */
|
||
|
||
uint32 StoreFPR (struct ufp *fop, uint32 op, uint32 r1, uint32 rnd)
|
||
{
|
||
uint32 hi, cc;
|
||
|
||
if (rnd && (fop->l & FP_ROUND)) { /* round? */
|
||
fop->h = fop->h + 1; /* add 1 to frac */
|
||
if (fop->h & FP_CARRY) { /* carry out? */
|
||
fop->h = fop->h >> 4; /* renormalize */
|
||
fop->exp = fop->exp + 1; } } /* incr exp */
|
||
if (fop->h == 0) { /* result 0? */
|
||
hi = fop->l = 0; /* store clean 0 */
|
||
cc = 0; }
|
||
else if (fop->exp < 0) { /* underflow? */
|
||
hi = fop->l = 0; /* store clean 0 */
|
||
cc = CC_V; }
|
||
else if (fop->exp > FP_M_EXP) { /* overflow? */
|
||
hi = (fop->sign)? 0xFFFFFFFF: 0x7FFFFFFF;
|
||
fop->l = 0xFFFFFFFF;
|
||
cc = (CC_V | ((fop->sign)? CC_L: CC_G)); }
|
||
else { hi = ((fop->sign & FP_M_SIGN) << FP_V_SIGN) | /* pack result */
|
||
((fop->exp & FP_M_EXP) << FP_V_EXP) |
|
||
((fop->h & FP_M_FRH) << FP_V_FRH);
|
||
cc = (fop->sign)? CC_L: CC_G; } /* set cc's */
|
||
if (OP_DPFP (op)) { /* double precision? */
|
||
D[r1 >> 1].h = hi;
|
||
D[r1 >> 1].l = fop->l; }
|
||
else { WriteFReg (r1, hi); }
|
||
return cc;
|
||
}
|
||
|
||
/* Generate exception result */
|
||
|
||
uint32 StoreFPX (struct ufp *fop, uint32 op, uint32 r1)
|
||
{
|
||
uint32 cc = CC_V;
|
||
|
||
if (fop->exp < 0) fop->h = fop->l = 0; /* undf? clean 0 */
|
||
else { fop->h = (fop->sign)? 0xFFFFFFFF: 0x7FFFFFFF; /* overflow */
|
||
fop->l = 0xFFFFFFFF;
|
||
cc = cc | ((fop->sign)? CC_L: CC_G); }
|
||
if (OP_DPFP (op)) { /* double precision? */
|
||
D[r1 >> 1].h = fop->h;
|
||
D[r1 >> 1].l = fop->l; }
|
||
else { WriteFReg (r1, fop->h); }
|
||
return cc;
|
||
}
|