26aa6de663
RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. WARNING: The core simulator files (scp.c, sim_*.c) have been reorganized. Unzip V3.2-0 to an empty directory before attempting to compile the source. IMPORTANT: If you are compiling for UNIX, please read the notes for Ethernet very carefully. You may need to download a new version of the pcap library, or make changes to the makefile, to get Ethernet support to work. 1. New Features in 3.2-0 1.1 SCP and libraries - Added SHOW <device> RADIX command. - Added SHOW <device> MODIFIERS command. - Added SHOW <device> NAMES command. - Added SET/SHOW <device> DEBUG command. - Added sim_vm_parse_addr and sim_vm_fprint_addr optional interfaces. - Added REG_VMAD flag. - Split SCP into separate libraries for easier modification. - Added more room to the device and unit flag fields. - Changed terminal multiplexor library to support unlimited. number of async lines. 1.2 All DECtapes - Added STOP_EOR flag to enable end-of-reel error stop - Added device debug support. 1.3 Nova and Eclipse - Added QTY and ALM multiplexors (Bruce Ray). 1.4 LGP-30 - Added LGP-30/LGP-21 simulator. 1.5 PDP-11 - Added format, address increment inhibit, transfer overrun detection to RK. - Added device debug support to HK, RP, TM, TQ, TS. - Added DEUNA/DELUA (XU) support (Dave Hittner). - Add DZ per-line logging. 1.6 18b PDP's - Added support for 1-4 (PDP-9)/1-16 (PDP-15) additional terminals. 1.7 PDP-10 - Added DEUNA/DELUA (XU) support (Dave Hittner). 1.8 VAX - Added extended memory to 512MB (Mark Pizzolato). - Added RXV21 support. 2. Bugs Fixed in 3.2-0 2.1 SCP - Fixed double logging of SHOW BREAK (found by Mark Pizzolato). - Fixed implementation of REG_VMIO. 2.2 Nova and Eclipse - Fixed device enable/disable support (found by Bruce Ray). 2.3 PDP-1 - Fixed bug in LOAD (found by Mark Crispin). 2.4 PDP-10 - Fixed bug in floating point unpack. - Fixed bug in FIXR (found by Phil Stone, fixed by Chris Smith). 2.6 PDP-11 - Fixed bug in RQ interrupt control (found by Tom Evans). 2.6 PDP-18B - Fixed bug in PDP-15 XVM g_mode implementation. - Fixed bug in PDP-15 indexed address calculation. - Fixed bug in PDP-15 autoindexed address calculation. - Fixed bugs in FPP-15 instruction decode. - Fixed clock response to CAF. - Fixed bug in hardware read-in mode bootstrap. - Fixed PDP-15 XVM instruction decoding errors. 2.7 VAX - Fixed PC read fault in EXTxV. - Fixed PC write fault in INSV.
263 lines
9 KiB
C
263 lines
9 KiB
C
/* id_tt.c: Interdata teletype
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Copyright (c) 2000-2004, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tt console
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29-Dec-03 RMS Added support for console backpressure
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25-Apr-03 RMS Revised for extended file support
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11-Jan-03 RMS Added TTP support
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22-Dec-02 RMS Added break support
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*/
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#include "id_defs.h"
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#include <ctype.h>
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#define UNIT_V_8B (UNIT_V_UF + 0) /* 8B */
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#define UNIT_V_KSR (UNIT_V_UF + 1) /* KSR33 */
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#define UNIT_8B (1 << UNIT_V_8B)
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#define UNIT_KSR (1 << UNIT_V_KSR)
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/* Device definitions */
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#define TTI 0
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#define TTO 1
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#define STA_OVR 0x80 /* overrun */
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#define STA_BRK 0x20 /* break */
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#define STA_MASK (STA_OVR | STA_BRK | STA_BSY) /* status mask */
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#define SET_EX (STA_OVR | STA_BRK) /* set EX */
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#define CMD_V_FDPX 4 /* full/half duplex */
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#define CMD_V_RD 2 /* read/write */
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extern uint32 int_req[INTSZ], int_enb[INTSZ];
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uint32 tt_sta = STA_BSY; /* status */
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uint32 tt_fdpx = 1; /* tt mode */
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uint32 tt_rd = 1, tt_chp = 0; /* tt state */
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uint32 tt_arm = 0; /* int arm */
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uint32 tt (uint32 dev, uint32 op, uint32 dat);
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t_stat tti_svc (UNIT *uptr);
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t_stat tto_svc (UNIT *uptr);
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t_stat tt_reset (DEVICE *dptr);
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t_stat tt_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat tt_set_break (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat tt_set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc);
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/* TT data structures
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tt_dev TT device descriptor
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tt_unit TT unit descriptors
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tt_reg TT register list
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tt_mod TT modifiers list
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*/
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DIB tt_dib = { d_TT, -1, v_TT, NULL, &tt, NULL };
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UNIT tt_unit[] = {
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{ UDATA (&tti_svc, UNIT_KSR, 0), KBD_POLL_WAIT },
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{ UDATA (&tto_svc, UNIT_KSR, 0), SERIAL_OUT_WAIT }
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};
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REG tt_reg[] = {
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{ HRDATA (STA, tt_sta, 8) },
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{ HRDATA (KBUF, tt_unit[TTI].buf, 8) },
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{ DRDATA (KPOS, tt_unit[TTI].pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (KTIME, tt_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
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{ HRDATA (TBUF, tt_unit[TTO].buf, 8) },
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{ DRDATA (TPOS, tt_unit[TTO].pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TTIME, tt_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
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{ FLDATA (IREQ, int_req[l_TT], i_TT) },
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{ FLDATA (IENB, int_enb[l_TT], i_TT) },
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{ FLDATA (IARM, tt_arm, 0) },
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{ FLDATA (RD, tt_rd, 0) },
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{ FLDATA (FDPX, tt_fdpx, 0) },
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{ FLDATA (CHP, tt_chp, 0) },
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{ HRDATA (DEVNO, tt_dib.dno, 8), REG_HRO },
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{ NULL } };
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MTAB tt_mod[] = {
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{ UNIT_KSR+UNIT_8B, UNIT_KSR, "KSR", "KSR", &tt_set_mode },
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{ UNIT_KSR+UNIT_8B, 0 , "7b" , "7B" , &tt_set_mode },
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{ UNIT_KSR+UNIT_8B, UNIT_8B , "8b" , "8B" , &tt_set_mode },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "ENABLED",
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&tt_set_enbdis, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, DEV_DIS, NULL, "DISABLED",
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&tt_set_enbdis, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "BREAK",
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&tt_set_break, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
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&set_dev, &show_dev, &tt_dib },
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{ 0 } };
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DEVICE tt_dev = {
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"TT", tt_unit, tt_reg, tt_mod,
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2, 10, 31, 1, 16, 8,
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NULL, NULL, &tt_reset,
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NULL, NULL, NULL,
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&tt_dib, 0 };
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/* Terminal: IO routine */
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uint32 tt (uint32 dev, uint32 op, uint32 dat)
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{
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uint32 old_rd, t;
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switch (op) { /* case IO op */
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case IO_ADR: /* select */
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return BY; /* byte only */
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case IO_OC: /* command */
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old_rd = tt_rd;
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tt_arm = int_chg (v_TT, dat, tt_arm); /* upd int ctrl */
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tt_fdpx = io_2b (dat, CMD_V_FDPX, tt_fdpx); /* upd full/half */
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tt_rd = io_2b (dat, CMD_V_RD, tt_rd); /* upd rd/write */
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if (tt_rd != old_rd) { /* rw change? */
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if (tt_rd? tt_chp: !sim_is_active (&tt_unit[TTO])) {
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tt_sta = 0; /* busy = 0 */
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if (tt_arm) SET_INT (v_TT); } /* req intr */
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else {
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tt_sta = STA_BSY; /* busy = 1 */
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CLR_INT (v_TT); } } /* clr int */
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else tt_sta = tt_sta & ~STA_OVR; /* clr ovflo */
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break;
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case IO_RD: /* read */
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tt_chp = 0; /* clear pend */
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if (tt_rd) tt_sta = (tt_sta | STA_BSY) & ~STA_OVR;
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return (tt_unit[TTI].buf & 0xFF);
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case IO_WD: /* write */
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tt_unit[TTO].buf = dat & 0xFF; /* save char */
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if (!tt_rd) tt_sta = tt_sta | STA_BSY; /* set busy */
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sim_activate (&tt_unit[TTO], tt_unit[TTO].wait);
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break;
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case IO_SS: /* status */
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t = tt_sta & STA_MASK; /* get status */
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if (t & SET_EX) t = t | STA_EX; /* test for EX */
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return t; }
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return 0;
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}
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/* Unit service routines */
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t_stat tti_svc (UNIT *uptr)
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{
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int32 out, temp;
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sim_activate (uptr, uptr->wait); /* continue poll */
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tt_sta = tt_sta & ~STA_BRK; /* clear break */
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if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */
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if (tt_rd) { /* read mode? */
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tt_sta = tt_sta & ~STA_BSY; /* clear busy */
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if (tt_arm) SET_INT (v_TT); /* if armed, intr */
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if (tt_chp) tt_sta = tt_sta | STA_OVR; } /* got char? overrun */
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tt_chp = 1; /* char pending */
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out = temp & 0x7F; /* echo is 7B */
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if (temp & SCPE_BREAK) { /* break? */
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tt_sta = tt_sta | STA_BRK; /* set status */
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uptr->buf = 0; } /* no character */
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else if (uptr->flags & UNIT_KSR) { /* KSR mode? */
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if (islower (out)) out = toupper (out); /* cvt to UC */
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uptr->buf = out | 0x80; } /* set high bit */
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else uptr->buf = temp & ((tt_unit[TTI].flags & UNIT_8B)? 0xFF: 0x7F);
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uptr->pos = uptr->pos + 1; /* incr count */
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if (!tt_fdpx) { /* half duplex? */
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if (out) sim_putchar (out); /* write char */
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tt_unit[TTO].pos = tt_unit[TTO].pos + 1; }
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return SCPE_OK;
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}
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t_stat tto_svc (UNIT *uptr)
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{
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int32 ch;
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t_stat r;
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if (uptr->flags & UNIT_KSR) { /* KSR mode? */
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ch = uptr->buf & 0x7F; /* mask to 7b */
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if (islower (ch)) ch = toupper (ch); } /* cvt to UC */
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else ch = uptr->buf & ((tt_unit[TTO].flags & UNIT_8B)? 0xFF: 0x7F);
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if ((uptr->flags & UNIT_8B) || /* KSR or 7b? */
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((ch != 0) && (ch != 0x7F))) { /* supr NULL, DEL */
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if ((r = sim_putchar_s (ch)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* try again */
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return ((r == SCPE_STALL)? SCPE_OK: r); } }
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if (!tt_rd) { /* write mode? */
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tt_sta = tt_sta & ~STA_BSY; /* clear busy */
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if (tt_arm) SET_INT (v_TT); } /* if armed, intr */
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uptr->pos = uptr->pos + 1; /* incr count */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat tt_reset (DEVICE *dptr)
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{
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if (dptr->flags & DEV_DIS) sim_cancel (&tt_unit[TTI]); /* dis? cancel poll */
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else sim_activate (&tt_unit[TTI], tt_unit[TTI].wait); /* activate input */
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sim_cancel (&tt_unit[TTO]); /* cancel output */
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tt_rd = tt_fdpx = 1; /* read, full duplex */
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tt_chp = 0; /* no char */
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tt_sta = STA_BSY; /* buffer empty */
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CLR_INT (v_TT); /* clear int */
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CLR_ENB (v_TT); /* disable int */
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tt_arm = 0; /* disarm int */
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return SCPE_OK;
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}
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/* Make mode flags uniform */
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t_stat tt_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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tt_unit[TTI].flags = (tt_unit[TTI].flags & ~(UNIT_KSR | UNIT_8B)) | val;
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tt_unit[TTO].flags = (tt_unit[TTO].flags & ~(UNIT_KSR | UNIT_8B)) | val;
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return SCPE_OK;
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}
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/* Set input break */
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t_stat tt_set_break (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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if (tt_dev.flags & DEV_DIS) return SCPE_NOFNC;
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tt_sta = tt_sta | STA_BRK;
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if (tt_rd) { /* read mode? */
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tt_sta = tt_sta & ~STA_BSY; /* clear busy */
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if (tt_arm) SET_INT (v_TT); } /* if armed, intr */
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sim_cancel (&tt_unit[TTI]); /* restart TT poll */
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sim_activate (&tt_unit[TTI], tt_unit[TTI].wait); /* so brk is seen */
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return SCPE_OK;
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}
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/* Set enabled/disabled */
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t_stat tt_set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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extern DEVICE ttp_dev;
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extern t_stat ttp_reset (DEVICE *dptr);
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tt_dev.flags = (tt_dev.flags & ~DEV_DIS) | val;
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ttp_dev.flags = (ttp_dev.flags & ~DEV_DIS) | (val ^ DEV_DIS);
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tt_reset (&tt_dev);
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ttp_reset (&ttp_dev);
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return SCPE_OK;
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}
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