591 lines
21 KiB
C
591 lines
21 KiB
C
/* sigma_map.c: XDS Sigma memory access routines
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Copyright (c) 2007, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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*/
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#include "sigma_defs.h"
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#define BVA_REG (RF_NUM << 2)
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#define BPAMASK ((cpu_tab[cpu_model].pamask << 2) | 0x3)
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#define NUM_MUNITS (MAXMEMSIZE / CPU_MUNIT_SIZE)
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/* Sigma 8-9 memory status words */
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#define S89_SR0_BADLMS 0x00800000 /* bad LMS */
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#define S89_SR0_RD (S89_SR0_BADLMS)
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#define S89_SR0_V_PORTS 12
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#define S89_SR1_FIXED 0x50C40000 /* always 1 */
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#define S89_SR1_M_MEMU 0xF /* mem unit */
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#define S89_SR1_V_MEMU 24
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#define S89_SR1_MARG 0x00F80000 /* margin write */
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#define S89_SR1_MAROFF 2 /* offset to read */
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/* 5X0 memory status words */
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#define S5X0_SR0_FIXED 0x40000000
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#define S5X0_SR0_BADLMS 0x00000004 /* bad LMS */
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#define S5X0_SR0_RD (S5X0_SR0_BADLMS)
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#define S5X0_SR0_V_PORTS 21
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#define S5X0_SR1_FIXED 0xB0000000 /* fixed */
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#define S5X0_SR1_M_MEMU 0x7 /* mem unit */
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#define S5X0_SR1_V_MEMU 25
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#define S5X0_SR1_V_SA 18 /* start addr */
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#define S8
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typedef struct {
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uint32 width; /* item width */
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uint32 dmask; /* data mask */
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uint32 cmask; /* control start mask */
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uint32 lnt; /* array length */
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uint32 opt; /* option control */
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} mmc_ctl_t;
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uint16 mmc_rel[VA_NUM_PAG];
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uint8 mmc_acc[VA_NUM_PAG];
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uint8 mmc_wlk[PA_NUM_PAG];
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uint32 mem_sr0[NUM_MUNITS];
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uint32 mem_sr1[NUM_MUNITS];
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mmc_ctl_t mmc_tab[8] = {
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{ 0, 0, 0, 0 },
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{ 2, 0x003, 0, MMC_L_CS1, CPUF_WLK }, /* map 1: 2b locks */
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{ 2, 0x003, MMC_M_CS2, MMC_L_CS2, CPUF_MAP }, /* map 2: 2b access ctls */
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{ 4, 0x00F, MMC_M_CS3, MMC_L_CS3, CPUF_WLK }, /* map 3: 4b locks */
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{ 8, 0x0FF, MMC_M_CS4, MMC_L_CS4, CPUF_MAP }, /* map 4: 8b relocation */
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{ 16, 0x7FF, MMC_M_CS5, MMC_L_CS5, CPUF_MAP }, /* map 5: 16b relocation */
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{ 0, 0, 0, 0 },
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{ 0, 0, 0, 0 }
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};
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extern uint32 *R;
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extern uint32 *M;
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extern uint32 PSW1, PSW2, PSW4;
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extern uint32 CC, PSW2_WLK;
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extern uint32 stop_op;
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extern uint32 cpu_model;
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extern uint32 chan_num;
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extern UNIT cpu_unit;
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extern cpu_var_t cpu_tab[];
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uint32 map_reloc (uint32 bva, uint32 acc, uint32 *bpa);
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uint32 map_viol (uint32 bva, uint32 bpa, uint32 tr);
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t_stat map_reset (DEVICE *dptr);
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uint32 map_las (uint32 rn, uint32 bva);
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/* Map data structures
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map_dev map device descriptor
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map_unit map units
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map_reg map register list
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*/
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UNIT map_unit = { UDATA (NULL, 0, 0) };
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REG map_reg[] = {
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{ BRDATA (REL, mmc_rel, 16, 13, VA_NUM_PAG) },
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{ BRDATA (ACC, mmc_acc, 16, 2, VA_NUM_PAG) },
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{ BRDATA (WLK, mmc_wlk, 16, 4, PA_NUM_PAG) },
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{ BRDATA (SR0, mem_sr0, 16, 32, NUM_MUNITS) },
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{ BRDATA (SR1, mem_sr1, 16, 32, NUM_MUNITS) },
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{ NULL }
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};
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DEVICE map_dev = {
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"MAP", &map_unit, map_reg, NULL,
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1, 16, 16, 1, 16, 32,
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NULL, NULL, &map_reset,
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NULL, NULL, NULL,
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NULL, 0
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};
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/* Read and write virtual routines - per length */
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uint32 ReadB (uint32 bva, uint32 *dat, uint32 acc)
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{
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uint32 bpa, sc, tr;
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sc = 24 - ((bva & 3) << 3);
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if (bva < BVA_REG) /* register access */
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*dat = (R[bva >> 2] >> sc) & BMASK;
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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*dat = (M[bpa >> 2] >> sc) & BMASK;
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} /* end else memory */
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return 0;
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}
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uint32 ReadH (uint32 bva, uint32 *dat, uint32 acc)
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{
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uint32 bpa, tr;
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if (bva < BVA_REG) { /* register access */
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if (bva & 2)
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*dat = R[bva >> 2] & HMASK;
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else *dat = (R[bva >> 2] >> 16) & HMASK;
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}
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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if (bva & 2)
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*dat = M[bpa >> 2] & HMASK;
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else *dat = (M[bpa >> 2] >> 16) & HMASK;
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} /* end else memory */
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return 0;
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}
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uint32 ReadW (uint32 bva, uint32 *dat, uint32 acc)
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{
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uint32 bpa, tr;
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if (bva < BVA_REG) /* register access */
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*dat = R[bva >> 2];
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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*dat = M[bpa >> 2];
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} /* end else memory */
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return 0;
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}
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uint32 ReadD (uint32 bva, uint32 *dat, uint32 *dat1, uint32 acc)
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{
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uint32 bpa, tr;
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if (bva < BVA_REG) { /* register access */
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*dat = R[(bva >> 2) & ~1]; /* force alignment */
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*dat1 = R[(bva >> 2) | 1];
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}
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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*dat = M[(bpa >> 2) & ~1]; /* force alignment */
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*dat1 = M[(bpa >> 2) | 1];
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} /* end else memory */
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return 0;
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}
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uint32 WriteB (uint32 bva, uint32 dat, uint32 acc)
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{
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uint32 bpa, sc, tr;
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sc = 24 - ((bva & 3) << 3);
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if (bva < BVA_REG) /* register access */
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R[bva >> 2] = (R[bva >> 2] & ~(BMASK << sc)) | ((dat & BMASK) << sc);
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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M[bpa >> 2] = (M[bpa >> 2] & ~(BMASK << sc)) | ((dat & BMASK) << sc);
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} /* end else memory */
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PSW2 |= PSW2_RA; /* state altered */
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return 0;
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}
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uint32 WriteH (uint32 bva, uint32 dat, uint32 acc)
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{
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uint32 bpa, tr;
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if (bva < BVA_REG) { /* register access */
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if (bva & 2)
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R[bva >> 2] = (R[bva >> 2] & ~HMASK) | (dat & HMASK);
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else R[bva >> 2] = (R[bva >> 2] & HMASK) | ((dat & HMASK) << 16);
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} /* end if register */
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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if (bva & 2)
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M[bpa >> 2] = (M[bpa >> 2] & ~HMASK) | (dat & HMASK);
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else M[bpa >> 2] = (M[bpa >> 2] & HMASK) | ((dat & HMASK) << 16);
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} /* end else memory */
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PSW2 |= PSW2_RA; /* state altered */
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return 0;
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}
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uint32 WriteW (uint32 bva, uint32 dat, uint32 acc)
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{
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uint32 bpa, tr;
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if (bva < BVA_REG) /* register access */
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R[bva >> 2] = dat & WMASK;
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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M[bpa >> 2] = dat & WMASK;
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} /* end else memory */
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PSW2 |= PSW2_RA; /* state altered */
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return 0;
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}
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uint32 WriteD (uint32 bva, uint32 dat, uint32 dat1, uint32 acc)
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{
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uint32 bpa, tr;
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if (bva < BVA_REG) { /* register access */
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R[(bva >> 2) & ~1] = dat & WMASK; /* force alignment */
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R[(bva >> 2) | 1] = dat1 & WMASK;
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}
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else { /* memory access */
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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M[(bpa >> 2) & ~1] = dat & WMASK; /* force alignment */
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M[(bpa >> 2) | 1] = dat1 & WMASK;
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} /* end else memory */
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PSW2 |= PSW2_RA; /* state altered */
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return 0;
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}
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/* General virtual read for instruction history */
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uint32 ReadHist (uint32 bva, uint32 *dat, uint32 *dat1, uint32 acc, uint32 lnt)
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{
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switch (lnt) { /* case on length */
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case BY: /* byte */
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return ReadB (bva, dat, acc);
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case HW: /* halfword */
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return ReadH (bva, dat, acc);
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case WD: /* word */
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return ReadW (bva, dat, acc);
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case DW: /* doubleword first */
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return ReadD (bva, dat, dat1, acc);
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} /* end case length */
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return SCPE_IERR;
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}
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/* Specialized virtual read and write word routines -
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treats all addresses as memory addresses */
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uint32 ReadMemVW (uint32 bva, uint32 *dat, uint32 acc)
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{
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uint32 bpa;
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uint32 tr;
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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*dat = M[bpa >> 2] & WMASK;
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return 0;
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}
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uint32 WriteMemVW (uint32 bva, uint32 dat, uint32 acc)
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{
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uint32 bpa;
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uint32 tr;
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if ((tr = map_reloc (bva, acc, &bpa)) != 0) /* relocate addr */
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return tr;
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M[bpa >> 2] = dat & WMASK;
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return 0;
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}
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/* Relocation routine */
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uint32 map_reloc (uint32 bva, uint32 acc, uint32 *bpa)
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{
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if ((acc != 0) && (PSW1 & PSW1_MM)) { /* virt, map on? */
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uint32 vpag = BVA_GETPAG (bva); /* virt page num */
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*bpa = ((mmc_rel[vpag] << BVA_V_PAG) + BVA_GETOFF (bva)) & BPAMASK;
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if (((PSW1 & PSW1_MS) || /* slave mode? */
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(PSW2 & (PSW2_MA9|PSW2_MA5X0))) && /* master prot? */
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(mmc_acc[vpag] >= acc)) /* access viol? */
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return map_viol (bva, *bpa, TR_MPR);
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}
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else *bpa = bva; /* no, physical */
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if ((acc == VW) && PSW2_WLK) { /* write check? */
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uint32 ppag = BPA_GETPAG (*bpa); /* phys page num */
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if (PSW2_WLK && mmc_wlk[ppag] && /* lock, key != 0 */
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(PSW2_WLK != mmc_wlk[ppag])) /* lock != key? */
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return map_viol (bva, *bpa, TR_WLK);
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}
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if (BPA_IS_NXM (*bpa)) /* memory exist? */
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return TR_NXM; /* don't set TSF */
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return 0;
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}
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/* Memory management error */
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uint32 map_viol (uint32 bva, uint32 bpa, uint32 tr)
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{
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uint32 vpag = BVA_GETPAG (bva); /* virt page num */
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if (QCPU_S9) /* Sigma 9? */
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PSW2 = (PSW2 & ~PSW2_TSF) | (vpag << PSW2_V_TSF); /* save address */
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PSW4 = bva >> 2; /* 5X0 address */
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if ((tr == TR_WLK) && !QCPU_5X0) /* wlock on S5-9? */
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tr = TR_MPR; /* mem prot trap */
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if (BPA_IS_NXM (bpa)) /* also check NXM */
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tr |= TR_NXM; /* on MPR or WLK */
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return tr;
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}
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/* Physical byte access routines */
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uint32 ReadPB (uint32 ba, uint32 *wd)
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{
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uint32 sc;
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ba = ba & BPAMASK;
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if (BPA_IS_NXM (ba))
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return TR_NXM;
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sc = 24 - ((ba & 3) << 3);
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*wd = (M[ba >> 2] >> sc) & BMASK;
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return 0;
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}
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uint32 WritePB (uint32 ba, uint32 wd)
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{
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uint32 sc;
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ba = ba & BPAMASK;
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if (BPA_IS_NXM (ba))
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return TR_NXM;
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sc = 24 - ((ba & 3) << 3);
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M[ba >> 2] = (M[ba >> 2] & ~(BMASK << sc)) | ((wd & BMASK) << sc);
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return 0;
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}
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/* Physical word access routines */
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uint32 ReadPW (uint32 pa, uint32 *wd)
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{
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pa = pa & cpu_tab[cpu_model].pamask;
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if (MEM_IS_NXM (pa))
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return TR_NXM;
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*wd = M[pa];
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return 0;
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}
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uint32 WritePW (uint32 pa, uint32 wd)
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{
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pa = pa & cpu_tab[cpu_model].pamask;
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if (MEM_IS_NXM (pa))
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return TR_NXM;
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M[pa] = wd;
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return 0;
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}
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/* LRA - load real address (extended memory systems only) */
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uint32 map_lra (uint32 rn, uint32 IR)
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{
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uint32 lnt, bva, bpa, vpag, ppag;
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uint32 tr;
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lnt = CC >> 2; /* length */
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CC = 0; /* clear */
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if ((tr = Ea (IR, &bva, VR, lnt)) != 0) { /* get eff addr */
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if (tr == TR_NXM) /* NXM trap? */
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CC = CC1|CC2;
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R[rn] = bva >> 2; /* fails */
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}
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else if (bva < BVA_REG) { /* reg ref? */
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CC = CC1|CC2;
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R[rn] = bva >> 2; /* fails */
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}
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else {
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vpag = BVA_GETPAG (bva); /* virt page num */
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bpa = ((mmc_rel[vpag] << BVA_V_PAG) + BVA_GETOFF (bva)) & BPAMASK;
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ppag = BPA_GETPAG (bpa); /* phys page num */
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if (MEM_IS_NXM (bpa)) /* NXM? */
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CC = CC1|CC2;
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R[rn] = (QCPU_S9? (mmc_wlk[ppag] << 24): 0) | /* result */
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(bpa >> lnt);
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CC |= mmc_acc[vpag]; /* access prot */
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}
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return 0;
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}
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/* MMC - load memory map control */
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uint32 map_mmc (uint32 rn, uint32 map)
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{
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uint32 tr;
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uint32 wd, i, map_width, maps_per_word, map_cmask, cs;
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map_width = mmc_tab[map].width; /* width in bits */
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maps_per_word = 32 / map_width;
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if (map != 1) /* maps 2-7? */
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map_cmask = mmc_tab[map].cmask; /* std ctl mask */
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else map_cmask = cpu_tab[cpu_model].mmc_cm_map1; /* model based */
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if ((map_width == 0) || /* validate map */
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((cpu_unit.flags & mmc_tab[map].opt) == 0) ||
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((map == 3) && !QCPU_5X0) ||
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((map == 5) && !QCPU_BIGM)) {
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if (QCPU_S89_5X0) /* S89, 5X0 trap */
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return TR_INVMMC;
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return stop_op? STOP_ILLEG: 0;
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}
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do {
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cs = (R[rn|1] >> MMC_V_CS) & map_cmask; /* ptr into map */
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if ((tr = ReadW ((R[rn] << 2) & BVAMASK, &wd, VR)) != 0)
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return tr;
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for (i = 0; i < maps_per_word; i++) { /* loop thru word */
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wd = ((wd << map_width) | (wd >> (32 - map_width))) & WMASK;
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switch (map) {
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case 1: case 3: /* write locks */
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mmc_wlk[cs] = wd & mmc_tab[map].dmask;
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break;
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case 2: /* access ctls */
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mmc_acc[cs] = wd & mmc_tab[map].dmask;
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break;
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case 4: case 5: /* relocation */
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mmc_rel[cs] = wd & mmc_tab[map].dmask;
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break;
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};
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|
cs = (cs + 1) % mmc_tab[map].lnt; /* incr mod lnt */
|
|
} /* end for */
|
|
R[rn] = (R[rn] + 1) & WMASK; /* incr mem ptr */
|
|
R[rn|1] = (R[rn|1] & ~(MMC_CNT | (map_cmask << MMC_V_CS))) |
|
|
(((MMC_GETCNT (R[rn|1]) - 1) & MMC_M_CNT) << MMC_V_CNT) |
|
|
((cs & map_cmask) << MMC_V_CS);
|
|
} while (MMC_GETCNT (R[rn|1]) != 0);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* LAS instruction (reused by LMS), without condition code settings */
|
|
|
|
uint32 map_las (uint32 rn, uint32 bva)
|
|
{
|
|
uint32 opnd, tr;
|
|
|
|
if ((bva < (RF_NUM << 2)) && QCPU_5X0) /* on 5X0, reg */
|
|
ReadW (bva, &opnd, VR); /* refs ignored */
|
|
else { /* go to mem */
|
|
if ((tr = ReadMemVW (bva, &opnd, VR)) != 0) /* read word */
|
|
return tr;
|
|
if ((tr = WriteMemVW (bva, opnd | WSIGN, VW)) != 0) /* set bit */
|
|
return tr;
|
|
}
|
|
R[rn] = opnd; /* store */
|
|
return 0;
|
|
}
|
|
|
|
/* Load memory status */
|
|
|
|
uint32 map_lms (uint32 rn, uint32 bva)
|
|
{
|
|
uint32 tr, wd, low, ppag;
|
|
uint32 memu = (bva >> 2) / CPU_MUNIT_SIZE;
|
|
|
|
if (CC == 0) /* LAS */
|
|
return map_las (rn, bva);
|
|
if (CC == 1) { /* read no par */
|
|
if ((tr = ReadW (bva, &wd, PH)) != 0)
|
|
return tr;
|
|
R[rn] = wd;
|
|
for (CC = CC3; wd != 0; CC ^= CC3) { /* calc odd par */
|
|
low = wd & -((int32) wd);
|
|
wd = wd & ~low;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
ppag = BPA_GETPAG (bva); /* phys page num */
|
|
wd = mem_sr0[memu]; /* save sr0 */
|
|
if (QCPU_S89)
|
|
switch (CC) { /* Sigma 8-9 */
|
|
case 0x2: /* read bad par */
|
|
if ((tr = ReadW (bva, &wd, VR)) != 0)
|
|
return tr;
|
|
R[rn] = wd;
|
|
break;
|
|
case 0x7: /* set margins */
|
|
mem_sr1[memu] = S89_SR1_FIXED |
|
|
((memu & S89_SR1_M_MEMU) << S89_SR1_V_MEMU) |
|
|
((R[rn] & S89_SR1_MARG) >> S89_SR1_MAROFF);
|
|
break;
|
|
case 0xB: /* read sr0, clr */
|
|
mem_sr0[memu] = mem_sr1[memu] = 0;
|
|
case 0x8: /* read sr0 */
|
|
R[rn] = (wd & S89_SR0_RD) |
|
|
(((1u << (chan_num + 1)) - 1) << (S89_SR0_V_PORTS - (chan_num + 1)));
|
|
break;
|
|
case 0x9: /* read sr1 */
|
|
R[rn] = mem_sr1[memu];
|
|
break;
|
|
case 0xA: case 0xE: /* read sr2 */
|
|
R[rn] = 0;
|
|
break;
|
|
case 0xF: /* clear word */
|
|
return WriteW (bva, 0, VW);
|
|
break;
|
|
default:
|
|
mem_sr0[memu] |= S89_SR0_BADLMS;
|
|
break;
|
|
}
|
|
else switch (CC) { /* 5X0 */
|
|
case 0x2: /* clear word */
|
|
return WriteW (bva, 0, VW);
|
|
case 0x6: /* read wlk */
|
|
R[rn] = (mmc_wlk[ppag & ~1] << 4) | mmc_wlk[ppag | 1];
|
|
break;
|
|
case 0x7: /* write wlk */
|
|
mmc_wlk[ppag & ~1] = (R[rn] >> 4) & 0xF;
|
|
mmc_wlk[ppag | 1] = R[rn] & 0xF;
|
|
break;
|
|
case 0xC: /* read sr0, clr */
|
|
mem_sr0[memu] = 0;
|
|
case 0x8: /* read sr0 */
|
|
R[rn] = S5X0_SR0_FIXED | (wd & S5X0_SR0_RD) |
|
|
(((1u << (chan_num + 1)) - 1) << (S5X0_SR0_V_PORTS - (chan_num + 1)));
|
|
break;
|
|
case 0xA: /* read sr1 */
|
|
R[rn] = S5X0_SR1_FIXED |
|
|
((memu & S5X0_SR1_M_MEMU) << S5X0_SR1_V_MEMU) |
|
|
(memu << S5X0_SR1_V_SA);
|
|
break;
|
|
case 0xE: /* trash mem */
|
|
return WriteW (bva, R[rn] & ~0xFF, VW);
|
|
default:
|
|
mem_sr0[memu] |= S5X0_SR0_BADLMS;
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Device reset */
|
|
|
|
t_stat map_reset (DEVICE *dptr)
|
|
{
|
|
uint32 i;
|
|
|
|
for (i = 0; i < VA_NUM_PAG; i++) { /* clear mmc arrays */
|
|
mmc_rel[i] = 0;
|
|
mmc_acc[i] = 0;
|
|
}
|
|
for (i = 0; i < PA_NUM_PAG; i++)
|
|
mmc_wlk[i] = 0;
|
|
return SCPE_OK;
|
|
}
|