5531ccb175
These changes facilitate more robust parameter type checking and helps to identify unexpected coding errors. Most simulators can now also be compiled with a C++ compiler without warnings. Additionally, these changes have also been configured to facilitate easier backporting of simulator and device simulation modules to run under the simh v3.9+ SCP framework.
428 lines
13 KiB
C
428 lines
13 KiB
C
/* gri_stddev.c: GRI-909 standard devices
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Copyright (c) 2001-2016, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tti S42-001 terminal input
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tto S42-002 terminal output
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hsr S42-004 high speed reader
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hsp S42-006 high speed punch
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rtc real time clock
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05-May-16 RMS Fixed calling sequence inconsistencies (Mark Pizzolato)
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28-Mar-15 RMS Revised to use sim_printf
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31-May-08 RMS Fixed declarations (Peter Schorn)
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30-Sep-06 RMS Fixed handling of non-printable characters in KSR mode
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22-Nov-05 RMS Revised for new terminal processing routines
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29-Dec-03 RMS Added support for console backpressure
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25-Apr-03 RMS Revised for extended file support
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22-Dec-02 RMS Added break support
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01-Nov-02 RMS Added 7b/8B support to terminal
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*/
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#include "gri_defs.h"
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#include "sim_tmxr.h"
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#include <ctype.h>
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uint32 hsr_stopioe = 1, hsp_stopioe = 1;
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extern uint16 M[];
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extern uint32 dev_done, ISR;
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t_stat tti_svc (UNIT *uhsr);
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t_stat tto_svc (UNIT *uhsr);
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t_stat tti_reset (DEVICE *dhsr);
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t_stat tto_reset (DEVICE *dhsr);
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t_stat tty_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat hsr_svc (UNIT *uhsr);
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t_stat hsp_svc (UNIT *uhsr);
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t_stat hsr_reset (DEVICE *dhsr);
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t_stat hsp_reset (DEVICE *dhsr);
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t_stat rtc_svc (UNIT *uhsr);
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t_stat rtc_reset (DEVICE *dhsr);
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int32 rtc_tps = 1000;
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/* TTI data structures
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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tti_mod TTI modifiers list
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*/
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UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_KSR, 0), KBD_POLL_WAIT };
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REG tti_reg[] = {
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{ ORDATA (BUF, tti_unit.buf, 8) },
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{ FLDATA (IRDY, dev_done, INT_V_TTI) },
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{ FLDATA (IENB, ISR, INT_V_TTI) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
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{ NULL }
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};
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MTAB tti_mod[] = {
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{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
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{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
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{ 0 }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL
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};
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/* TTO data structures
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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*/
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UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_KSR, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ ORDATA (BUF, tto_unit.buf, 8) },
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{ FLDATA (ORDY, dev_done, INT_V_TTO) },
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{ FLDATA (IENB, ISR, INT_V_TTO) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ NULL }
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};
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MTAB tto_mod[] = {
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{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL
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};
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/* HSR data structures
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hsr_dev HSR device descriptor
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hsr_unit HSR unit descriptor
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hsr_reg HSR register list
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hsr_mod HSR modifiers list
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*/
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UNIT hsr_unit = {
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UDATA (&hsr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT
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};
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REG hsr_reg[] = {
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{ ORDATA (BUF, hsr_unit.buf, 8) },
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{ FLDATA (IRDY, dev_done, INT_V_HSR) },
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{ FLDATA (IENB, ISR, INT_V_HSR) },
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{ DRDATA (POS, hsr_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, hsr_unit.wait, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, hsr_stopioe, 0) },
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{ NULL }
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};
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DEVICE hsr_dev = {
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"HSR", &hsr_unit, hsr_reg, NULL,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &hsr_reset,
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NULL, NULL, NULL
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};
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/* HSP data structures
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hsp_dev HSP device descriptor
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hsp_unit HSP unit descriptor
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hsp_reg HSP register list
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*/
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UNIT hsp_unit = {
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UDATA (&hsp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT
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};
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REG hsp_reg[] = {
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{ ORDATA (BUF, hsp_unit.buf, 8) },
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{ FLDATA (ORDY, dev_done, INT_V_HSP) },
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{ FLDATA (IENB, ISR, INT_V_HSP) },
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{ DRDATA (POS, hsp_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, hsp_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, hsp_stopioe, 0) },
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{ NULL }
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};
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DEVICE hsp_dev = {
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"HSP", &hsp_unit, hsp_reg, NULL,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &hsp_reset,
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NULL, NULL, NULL
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};
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/* RTC data structures
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rtc_dev RTC device descriptor
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rtc_unit RTC unit descriptor
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rtc_reg RTC register list
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*/
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UNIT rtc_unit = { UDATA (&rtc_svc, 0, 0), 16000 };
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REG rtc_reg[] = {
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{ FLDATA (RDY, dev_done, INT_V_RTC) },
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{ FLDATA (IENB, ISR, INT_V_RTC) },
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{ DRDATA (TIME, rtc_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, rtc_tps, 8), REG_NZ + PV_LEFT + REG_HIDDEN },
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{ NULL }
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};
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DEVICE rtc_dev = {
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"RTC", &rtc_unit, rtc_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &rtc_reset,
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NULL, NULL, NULL
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};
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/* Console terminal function processors */
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uint32 tty_rd (uint32 src)
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{
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return tti_unit.buf; /* return data */
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}
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t_stat tty_wr (uint32 dst, uint32 val)
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{
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tto_unit.buf = val & 0377; /* save char */
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dev_done = dev_done & ~INT_TTO; /* clear ready */
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sim_activate (&tto_unit, tto_unit.wait); /* activate unit */
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return SCPE_OK;
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}
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t_stat tty_fo (uint32 op)
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{
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if (op & TTY_IRDY)
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dev_done = dev_done & ~INT_TTI;
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if (op & TTY_ORDY)
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dev_done = dev_done & ~INT_TTO;
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return SCPE_OK;
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}
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uint32 tty_sf (uint32 op)
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{
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if (((op & TTY_IRDY) && (dev_done & INT_TTI)) ||
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((op & TTY_ORDY) && (dev_done & INT_TTO)))
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return 1;
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return 0;
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}
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/* Service routines */
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t_stat tti_svc (UNIT *uptr)
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{
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int32 c;
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sim_activate (uptr, uptr->wait); /* continue poll */
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if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
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return c;
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if (c & SCPE_BREAK) /* break? */
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uptr->buf = 0;
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else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags) | TTUF_KSR);
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dev_done = dev_done | INT_TTI; /* set ready */
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uptr->pos = uptr->pos + 1;
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return SCPE_OK;
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}
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t_stat tto_svc (UNIT *uptr)
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{
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int32 c;
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t_stat r;
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c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags) | TTUF_KSR);
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if (c >= 0) {
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if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
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sim_activate (uptr, uptr->wait); /* try again */
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return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
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}
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}
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dev_done = dev_done | INT_TTO; /* set ready */
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uptr->pos = uptr->pos + 1;
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return SCPE_OK;
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}
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/* Reset routines */
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t_stat tti_reset (DEVICE *dptr)
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{
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tmxr_set_console_units (&tti_unit, &tto_unit);
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tti_unit.buf = 0; /* clear buffer */
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dev_done = dev_done & ~INT_TTI; /* clear ready */
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sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
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return SCPE_OK;
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}
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t_stat tto_reset (DEVICE *dptr)
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{
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tto_unit.buf = 0; /* clear buffer */
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dev_done = dev_done | INT_TTO; /* set ready */
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sim_cancel (&tto_unit); /* deactivate unit */
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return SCPE_OK;
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}
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t_stat tty_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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tti_unit.flags = (tti_unit.flags & ~TT_MODE) | val;
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tto_unit.flags = (tto_unit.flags & ~TT_MODE) | val;
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return SCPE_OK;
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}
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/* High speed paper tape function processors */
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uint32 hsrp_rd (uint32 src)
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{
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return hsr_unit.buf; /* return data */
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}
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t_stat hsrp_wr (uint32 dst, uint32 val)
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{
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hsp_unit.buf = val & 0377; /* save char */
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dev_done = dev_done & ~INT_HSP; /* clear ready */
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sim_activate (&hsp_unit, hsp_unit.wait); /* activate unit */
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return SCPE_OK;
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}
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t_stat hsrp_fo (uint32 op)
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{
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if (op & PT_IRDY)
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dev_done = dev_done & ~INT_HSR;
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if (op & PT_ORDY)
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dev_done = dev_done & ~INT_HSP;
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if (op & PT_STRT)
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sim_activate (&hsr_unit, hsr_unit.wait);
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return SCPE_OK;
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}
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uint32 hsrp_sf (uint32 op)
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{
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if (((op & PT_IRDY) && (dev_done & INT_HSR)) ||
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((op & PT_ORDY) && (dev_done & INT_HSP)))
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return 1;
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return 0;
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}
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t_stat hsr_svc (UNIT *uptr)
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{
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int32 temp;
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if ((hsr_unit.flags & UNIT_ATT) == 0) /* attached? */
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return IORETURN (hsr_stopioe, SCPE_UNATT);
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if ((temp = getc (hsr_unit.fileref)) == EOF) { /* read char */
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if (feof (hsr_unit.fileref)) { /* err or eof? */
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if (hsr_stopioe)
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sim_printf ("HSR end of file\n");
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else return SCPE_OK;
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}
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else sim_perror ("HSR I/O error");
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clearerr (hsr_unit.fileref);
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return SCPE_IOERR;
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}
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dev_done = dev_done | INT_HSR; /* set ready */
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hsr_unit.buf = temp & 0377; /* save char */
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hsr_unit.pos = hsr_unit.pos + 1;
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return SCPE_OK;
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}
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t_stat hsp_svc (UNIT *uptr)
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{
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dev_done = dev_done | INT_HSP; /* set ready */
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if ((hsp_unit.flags & UNIT_ATT) == 0) /* attached? */
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return IORETURN (hsp_stopioe, SCPE_UNATT);
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if (putc (hsp_unit.buf, hsp_unit.fileref) == EOF) { /* write char */
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sim_perror ("HSP I/O error"); /* error? */
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clearerr (hsp_unit.fileref);
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return SCPE_IOERR;
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}
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hsp_unit.pos = hsp_unit.pos + 1;
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return SCPE_OK;
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}
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/* Reset routines */
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t_stat hsr_reset (DEVICE *dptr)
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{
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hsr_unit.buf = 0; /* clear buffer */
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dev_done = dev_done & ~INT_HSR; /* clear ready */
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sim_cancel (&hsr_unit); /* deactivate unit */
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return SCPE_OK;
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}
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t_stat hsp_reset (DEVICE *dptr)
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{
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hsp_unit.buf = 0; /* clear buffer */
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dev_done = dev_done | INT_HSP; /* set ready */
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sim_cancel (&hsp_unit); /* deactivate unit */
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return SCPE_OK;
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}
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/* Clock function processors */
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t_stat rtc_fo (uint32 op)
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{
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if (op & RTC_OFF) /* clock off? */
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sim_cancel (&rtc_unit);
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if ((op & RTC_ON) && !sim_is_active (&rtc_unit)) /* clock on? */
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sim_activate (&rtc_unit, sim_rtc_init (rtc_unit.wait));
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if (op & RTC_OV) /* clr ovflo? */
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dev_done = dev_done & ~INT_RTC;
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return SCPE_OK;
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}
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uint32 rtc_sf (uint32 op)
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{
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if ((op & RTC_OV) && (dev_done & INT_RTC))
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return 1;
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return 0;
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}
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t_stat rtc_svc (UNIT *uptr)
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{
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M[RTC_CTR] = (M[RTC_CTR] + 1) & DMASK; /* incr counter */
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if (M[RTC_CTR] == 0) /* ovflo? set ready */
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dev_done = dev_done | INT_RTC;
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sim_activate (&rtc_unit, sim_rtc_calb (rtc_tps)); /* reactivate */
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return SCPE_OK;
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}
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t_stat rtc_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&rtc_unit); /* declare clock unit */
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dev_done = dev_done & ~INT_RTC; /* clear ready */
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sim_cancel (&rtc_unit); /* stop clock */
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return SCPE_OK;
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}
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